Sync with the mvme188 codebase, various tweaks from the last 18 months which

had not been reported to aviion.

4 files changed, 53 insertions, 70 deletions

diff --git a/sys/arch/aviion/aviion/av400_machdep.c b/sys/arch/aviion/aviion/av400_machdep.c
index 9e5c86bef23..4f16206412d 100644
--- a/sys/arch/aviion/aviion/av400_machdep.c
+++ b/sys/arch/aviion/aviion/av400_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: av400_machdep.c,v 1.9 2007/12/12 20:36:24 miod Exp $	*/
+/*	$OpenBSD: av400_machdep.c,v 1.10 2007/12/13 18:51:01 miod Exp $	*/
 /*
  * Copyright (c) 2006, Miodrag Vallat.
  *
@@ -271,7 +271,8 @@ av400_bootstrap()
 }
 
 /*
- * return next safe spl to reenable interrupts.
+ * Return the next ipl >= ``curlevel'' at which we can reenable interrupts
+ * while keeping ``mask'' masked.
  */
 u_int
 safe_level(u_int mask, u_int curlevel)
@@ -307,8 +308,8 @@ av400_setipl(u_int level)
 		mask &= ~SLAVE_MASK;
 #endif
 
-	*(u_int32_t *)AV_IEN(cpu) = int_mask_reg[cpu] = mask;
 	av400_curspl[cpu] = level;
+	*(u_int32_t *)AV_IEN(cpu) = int_mask_reg[cpu] = mask;
 	/*
 	 * We do not flush the pipeline here, because interrupts are disabled,
 	 * and set_psr() will synchronize the pipeline.
@@ -334,8 +335,8 @@ av400_raiseipl(u_int level)
 			mask &= ~SLAVE_MASK;
 #endif
 
-		*(u_int32_t *)AV_IEN(cpu) = int_mask_reg[cpu] = mask;
 		av400_curspl[cpu] = level;
+		*(u_int32_t *)AV_IEN(cpu) = int_mask_reg[cpu] = mask;
 	}
 	/*
 	 * We do not flush the pipeline here, because interrupts are disabled,
@@ -432,15 +433,9 @@ av400_intr(u_int v, struct trapframe *eframe)
 	 */
 	do {
 		level = safe_level(cur_mask, old_spl);
-		setipl(level);
+		av400_setipl(level);
 
-		/*
-		 * Do not enable interrupts yet if we know, from cur_mask,
-		 * that we have not cleared enough conditions yet.
-		 * For now, only the timer interrupt requires its condition
-		 * to be cleared before interrupts are enabled.
-		 */
-		if (unmasked == 0 /* && (cur_mask & whatever) == 0 */) {
+		if (unmasked == 0) {
 			set_psr(get_psr() & ~PSR_IND);
 			unmasked = 1;
 		}
@@ -619,12 +614,12 @@ av400_clockintr(void *eframe)
 	CIO_LOCK;
 	write_cio(CIO_CSR1, CIO_GCB | CIO_CIP);  /* Ack the interrupt */
 
-	hardclock(eframe);
-
 	/* restart counter */
 	write_cio(CIO_CSR1, CIO_GCB | CIO_TCB | CIO_IE);
 	CIO_UNLOCK;
 
+	hardclock(eframe);
+
 	return (1);
 }
 
diff --git a/sys/arch/aviion/aviion/eh.S b/sys/arch/aviion/aviion/eh.S
index 7ccf6e8b3f9..1273eed8d2e 100644
--- a/sys/arch/aviion/aviion/eh.S
+++ b/sys/arch/aviion/aviion/eh.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: eh.S,v 1.3 2007/11/15 21:24:44 miod Exp $	*/
+/*	$OpenBSD: eh.S,v 1.4 2007/12/13 18:51:01 miod Exp $	*/
 /*
  * Copyright (c) 2006, Miodrag Vallat
  *
@@ -31,22 +31,12 @@
  */
 
 #define	PFSR_SAVE \
-	br.n	_ASM_LABEL(pfsr_av400); \
-	 or.u	TMP2, r0,   hi16(_C_LABEL(cmmu_shift))
+	NOP;	/* will be changed to	br.n pfsr_handler + 4 */ \
+	NOP	/* will be changed to	 first instruction of pfsr_handler */
 
 #include <m88k/m88k/eh_common.S>
 
-	text
-
-ASLOCAL(pfsr_av400)
-#if 0	/* done in delay slot from PFSR_SAVE */
-	or.u	TMP2, r0,   hi16(_C_LABEL(cmmu_shift))
-#endif
-	ld	TMP2, TMP2, lo16(_C_LABEL(cmmu_shift))
-	cmp	TMP3, TMP2, 2
-	bb1	lt,   TMP2, _ASM_LABEL(pfsr_av400_straight)
-
-ASLOCAL(pfsr_av400_double)
+ENTRY(pfsr_av400_double)
 	/*
 	 * 4 CMMUs per CPU. Almost as simple as the 2 CMMUs per CPU
 	 * situation...
@@ -55,7 +45,6 @@ ASLOCAL(pfsr_av400_double)
 	 * exceptions, we have to reset the fault status registers
 	 * after reading them.
 	 */
-
 	ld	TMP2, TMP,  CI_PFSR_I0
 	ld	TMP3, TMP2, r0
 	extu	TMP3, TMP3, 3<16>
@@ -79,7 +68,7 @@ ASLOCAL(pfsr_av400_double)
 	br.n	_ASM_LABEL(pfsr_done)
 	 st	TMP3, r31,  REG_OFF(EF_DPFSR)
 
-ASLOCAL(pfsr_av400_straight)
+ENTRY(pfsr_av400_straight)
 	/*
 	 * We have the simple 2 CMMUs per CPU mapping. Pick our couple;
 	 * no need to reset fault status registers in this case.
diff --git a/sys/arch/aviion/aviion/m8820x.c b/sys/arch/aviion/aviion/m8820x.c
index bd641abaa2e..caa9b75f234 100644
--- a/sys/arch/aviion/aviion/m8820x.c
+++ b/sys/arch/aviion/aviion/m8820x.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m8820x.c,v 1.4 2006/05/21 12:22:01 miod Exp $	*/
+/*	$OpenBSD: m8820x.c,v 1.5 2007/12/13 18:51:01 miod Exp $	*/
 /*
  * Copyright (c) 2004, 2006, Miodrag Vallat.
  *
@@ -36,17 +36,22 @@
 #include <machine/m8820x.h>
 #include <machine/prom.h>
 
+extern	u_int32_t pfsr_av400_straight[];
+extern	u_int32_t pfsr_av400_double[];
+
 /*
  * This routine sets up the CPU/CMMU configuration.
  */
 void
 m8820x_setup_board_config()
 {
+	extern u_int32_t pfsr_save[];
 	struct m8820x_cmmu *cmmu;
 	struct scm_cpuconfig scc;
 	int type, cpu_num, cmmu_num;
 	volatile u_int *cr;
 	u_int32_t whoami;
+	u_int32_t *m8820x_pfsr;
 
 	/*
 	 * First, find if any CPU0 CMMU is a 88204. If so, we can
@@ -164,7 +169,13 @@ knowledge:
 	}
 
 	max_cpus = scc.cpucount;
-	cmmu_shift = scc.igang == 1 ? 1 : 2;
+	if (scc.igang == 1) {
+		cmmu_shift = 1;
+		m8820x_pfsr = pfsr_av400_straight;
+	} else {
+		cmmu_shift = 2;
+		m8820x_pfsr = pfsr_av400_double;
+	}
 	max_cmmus = max_cpus << scc.igang;
 
 	/*
@@ -203,6 +214,14 @@ knowledge:
 			}
 		}
 	}
+
+	/*
+	 * Patch the exception handling code to invoke the correct pfsr
+	 * analysis chunk.
+	 */
+	pfsr_save[0] = 0xc4000000 |
+	    (((vaddr_t)m8820x_pfsr + 4 - (vaddr_t)pfsr_save) >> 2);
+	pfsr_save[1] = m8820x_pfsr[0];
 }
 
 /*
diff --git a/sys/arch/aviion/aviion/machdep.c b/sys/arch/aviion/aviion/machdep.c
index 8938d5e15ca..d6161ab72c4 100644
--- a/sys/arch/aviion/aviion/machdep.c
+++ b/sys/arch/aviion/aviion/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.17 2007/11/17 05:36:21 miod Exp $	*/
+/* $OpenBSD: machdep.c,v 1.18 2007/12/13 18:51:01 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -76,6 +76,9 @@
 #include <machine/prom.h>
 #include <machine/reg.h>
 #include <machine/trap.h>
+#ifdef M88100
+#include <machine/m88100.h>
+#endif
 
 #include <dev/cons.h>
 
@@ -241,7 +244,8 @@ cpu_startup()
 	 */
 	printf(version);
 	identifycpu();
-	printf("real mem  = %d\n", ctob(physmem));
+	printf("real mem = %u (%uMB)\n", ptoa(physmem),
+	    ptoa(physmem)/1024/1024);
 
 	/*
 	 * Find out how much space we need, allocate it,
@@ -286,7 +290,8 @@ cpu_startup()
 	phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
 	    VM_PHYS_SIZE, 0, FALSE, NULL);
 
-	printf("avail mem = %ld (%d pages)\n", ptoa(uvmexp.free), uvmexp.free);
+	printf("avail mem = %lu (%luMB)\n", ptoa(uvmexp.free),
+	    ptoa(uvmexp.free)/1024/1024);
 
 	/*
 	 * Set up buffers, so they can be used to read disk labels.
@@ -428,7 +433,7 @@ dumpconf(void)
 
 	/* aviion only uses a single segment. */
 	cpu_kcore_hdr.ram_segs[0].start = 0;
-	cpu_kcore_hdr.ram_segs[0].size = ctob(physmem);
+	cpu_kcore_hdr.ram_segs[0].size = ptoa(physmem);
 	cpu_kcore_hdr.cputype = cputyp;
 
 	/*
@@ -811,6 +816,12 @@ aviion_bootstrap()
 	set_cpu_number(master_cpu);
 	SET(curcpu()->ci_flags, CIF_ALIVE | CIF_PRIMARY);
 
+#ifdef M88100
+	if (CPU_IS88100) {
+		m88100_apply_patches();
+	}
+#endif
+
 	/*
 	 * Now that set_cpu_number() set us with a valid cpu_info pointer,
 	 * we need to initialize p_addr and curpcb before autoconf, for the
@@ -900,50 +911,19 @@ bootcnputc(dev, c)
 int
 getipl(void)
 {
-	u_int curspl, psr;
-
-	disable_interrupt(psr);
-	curspl = platform->getipl();
-	set_psr(psr);
-	return (int)curspl;
+	return (int)platform->getipl();
 }
 
 int
 setipl(int level)
 {
-	u_int curspl, psr;
-
-	disable_interrupt(psr);
-	curspl = platform->setipl((u_int)level);
-
-	/*
-	 * The flush pipeline is required to make sure the above change gets
-	 * through the data pipe and to the hardware; otherwise, the next
-	 * bunch of instructions could execute at the wrong spl protection.
-	 */
-	flush_pipeline();
-
-	set_psr(psr);
-	return (int)curspl;
+	return (int)platform->setipl((u_int)level);
 }
 
 int
 raiseipl(int level)
 {
-	u_int curspl, psr;
-
-	disable_interrupt(psr);
-	curspl = platform->raiseipl((u_int)level);
-
-	/*
-	 * The flush pipeline is required to make sure the above change gets
-	 * through the data pipe and to the hardware; otherwise, the next
-	 * bunch of instructions could execute at the wrong spl protection.
-	 */
-	flush_pipeline();
-
-	set_psr(psr);
-	return (int)curspl;
+	return (int)platform->raiseipl((u_int)level);
 }
 
 u_char hostaddr[6];