Oops, correct import this time.

7 files changed, 1107 insertions, 0 deletions

diff --git a/sys/arch/aviion/include/autoconf.h b/sys/arch/aviion/include/autoconf.h
new file mode 100644
index 00000000000..5a8d44b6e34
--- /dev/null
+++ b/sys/arch/aviion/include/autoconf.h
@@ -0,0 +1,55 @@
+/*	$OpenBSD: autoconf.h,v 1.1 2006/05/09 18:19:19 miod Exp $ */
+/*
+ * Copyright (c) 1999, Steve Murphree, Jr.
+ * Copyright (c) 1996 Nivas Madhur
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Nivas Madhur.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Autoconfiguration information.
+ */
+
+#ifndef _AVIION_AUTOCONF_H_
+#define _AVIION_AUTOCONF_H_
+
+#include <machine/bus.h>
+
+struct confargs {
+	bus_space_tag_t	ca_iot;
+	paddr_t		ca_paddr;	/* physical address */
+	paddr_t		ca_offset;	/* offset from parent */
+	u_int		ca_ipl;		/* interrupt level */
+};
+
+void	cmdline_parse(void);
+void	myetheraddr(u_char *);
+
+extern u_int bootdev, bootunit, bootpart;
+extern char bootargs[256];
+
+#endif
diff --git a/sys/arch/aviion/include/bus.h b/sys/arch/aviion/include/bus.h
new file mode 100644
index 00000000000..d786a62a892
--- /dev/null
+++ b/sys/arch/aviion/include/bus.h
@@ -0,0 +1,724 @@
+/*	$OpenBSD: bus.h,v 1.1 2006/05/09 18:18:49 miod Exp $	*/
+/*
+ * Copyright (c) 2004, Miodrag Vallat.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Simple aviion bus_space implementation.
+ *
+ * Currently, we only need specific handling for 32 bit read/writes in D16
+ * space, and this choice is made at compile time.  As a result, all the
+ * implementation can go through macros or inline functions, except for
+ * the management functions.
+ */
+
+#ifndef	_AVIION_BUS_H_
+#define	_AVIION_BUS_H_
+
+#include <machine/asm_macro.h>
+
+typedef	u_int32_t	bus_addr_t;
+typedef	u_int32_t	bus_size_t;
+
+typedef	u_int32_t	bus_space_handle_t;
+
+struct aviion_bus_space_tag {
+	int	(*bs_map)(bus_addr_t, bus_size_t, int, bus_space_handle_t *);
+	void	(*bs_unmap)(bus_space_handle_t, bus_size_t);
+	int	(*bs_subregion)(bus_space_handle_t, bus_size_t, bus_size_t,
+		    bus_space_handle_t *);
+	void *	(*bs_vaddr)(bus_space_handle_t);
+	/* alloc, free not implemented yet */
+};
+
+typedef const struct aviion_bus_space_tag *bus_space_tag_t;
+
+#define	BUS_SPACE_BARRIER_READ	0
+#define	BUS_SPACE_BARRIER_WRITE	1
+
+#define	BUS_SPACE_MAP_CACHEABLE	0x01
+#define	BUS_SPACE_MAP_LINEAR	0x02
+
+/* 
+ * General bus_space function set
+ */
+
+#define	bus_space_map(t,a,s,f,r)	((t)->bs_map(a,s,f,r))
+#define	bus_space_unmap(t,h,s)		((t)->bs_unmap(h,s))
+#define	bus_space_subregion(t,h,o,s,r)	((t)->bs_subregion(h,o,s,r))
+#define	bus_space_vaddr(t,h)		((t)->bs_vaddr(h))
+
+static void bus_space_barrier(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, bus_size_t, int);
+
+static __inline__ void
+bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, bus_size_t size, int flags)
+{
+	flush_pipeline();	/* overkill? */
+}
+
+/*
+ * Read/Write/Region functions for D8 and D16 access.
+ * Most of these are straightforward and assume that everything is properly
+ * aligned.
+ */
+
+#define	bus_space_read_1(tag, handle, offset) \
+	((void)(tag), *(volatile u_int8_t *)((handle) + (offset)))
+#define	bus_space_read_2(tag, handle, offset) \
+	((void)(tag), *(volatile u_int16_t *)((handle) + (offset)))
+
+static void bus_space_read_multi_1(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		*dest++ = bus_space_read_1(tag, 0, offset);
+}
+
+static void bus_space_read_multi_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int16_t *, size_t);
+
+static __inline__ void
+bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int16_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		*dest++ = bus_space_read_2(tag, 0, offset);
+}
+
+static void bus_space_read_raw_multi_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_raw_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 1;
+	while ((int)--size >= 0) {
+		*(u_int16_t *)dest =
+		    bus_space_read_2(tag, 0, offset);
+		dest += 2;
+	}
+}
+
+static void bus_space_read_region_1(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		*dest++ = bus_space_read_1(tag, 0, offset++);
+}
+
+static void bus_space_read_region_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int16_t *, size_t);
+
+static __inline__ void
+bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int16_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0) {
+		*dest++ = bus_space_read_2(tag, 0, offset);
+		offset += 2;
+	}
+}
+
+static void bus_space_read_raw_region_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_raw_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	size >>= 1;
+	offset += handle;
+	while ((int)--size >= 0) {
+		*(u_int16_t *)dest = bus_space_read_2(tag, 0, offset);
+		offset += 2;
+		dest += 2;
+	}
+}
+
+#define	bus_space_write_1(tag, handle, offset, value) \
+	((void)(tag), *(volatile u_int8_t *)((handle) + (offset)) = (value))
+#define	bus_space_write_2(tag, handle, offset, value) \
+	((void)(tag), *(volatile u_int16_t *)((handle) + (offset)) = (value))
+
+static void bus_space_write_multi_1(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_1(tag, 0, offset, *dest++);
+}
+
+static void bus_space_write_multi_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int16_t *, size_t);
+
+static __inline__ void
+bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int16_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_2(tag, 0, offset, *dest++);
+}
+
+static void bus_space_write_raw_multi_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_raw_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 1;
+	while ((int)--size >= 0) {
+		bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest);
+		dest += 2;
+	}
+}
+
+static void bus_space_set_multi_1(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t, size_t);
+
+static __inline__ void
+bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_1(tag, 0, offset, value);
+}
+
+static void bus_space_set_multi_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int16_t, size_t);
+
+static __inline__ void
+bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int16_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_2(tag, 0, offset, value);
+}
+
+static void bus_space_write_region_1(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_1(tag, 0, offset++, *dest++);
+}
+
+static void bus_space_write_region_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int16_t *, size_t);
+
+static __inline__ void
+bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int16_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0) {
+		bus_space_write_2(tag, 0, offset, *dest++);
+		offset += 2;
+	}
+}
+
+static void bus_space_write_raw_region_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_raw_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 1;
+	while ((int)--size >= 0) {
+		bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest);
+		offset += 2;
+		dest += 2;
+	}
+}
+
+static void bus_space_set_region_1(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t, size_t);
+
+static __inline__ void
+bus_space_set_region_1(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_1(tag, 0, offset++, value);
+}
+
+static void bus_space_set_region_2(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int16_t, size_t);
+
+static __inline__ void
+bus_space_set_region_2(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int16_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0) {
+		bus_space_write_2(tag, 0, offset, value);
+		offset += 2;
+	}
+}
+
+static void bus_space_copy_1(bus_space_tag_t, bus_space_handle_t, bus_addr_t,
+    bus_space_handle_t, bus_addr_t, bus_size_t);
+
+static __inline__ void
+bus_space_copy_1(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1,
+    bus_space_handle_t h2, bus_addr_t o2, bus_size_t count)
+{
+	o1 += h1;
+	o2 += h2;
+	while ((int)--count >= 0) {
+		*((volatile u_int8_t *)o1)++ = *((volatile u_int8_t *)o2)++;
+	}
+}
+
+static void bus_space_copy_2(bus_space_tag_t, bus_space_handle_t, bus_addr_t,
+    bus_space_handle_t, bus_addr_t, bus_size_t);
+
+static __inline__ void
+bus_space_copy_2(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1,
+    bus_space_handle_t h2, bus_addr_t o2, bus_size_t count)
+{
+	o1 += h1;
+	o2 += h2;
+	while ((int)--count >= 0) {
+		*(volatile u_int16_t *)o1 = *(volatile u_int16_t *)o2;
+		o1 += 2;
+		o2 += 2;
+	}
+}
+
+/*
+ * Unrestricted D32 access
+ */
+
+#ifndef	__BUS_SPACE_RESTRICT_D16__
+
+#define	bus_space_read_4(tag, handle, offset) \
+	((void)(tag), *(volatile u_int32_t *)((handle) + (offset)))
+
+static void bus_space_read_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		*dest++ = bus_space_read_4(tag, 0, offset);
+}
+
+static void bus_space_read_raw_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 2;
+	while ((int)--size >= 0) {
+		*(u_int32_t *)dest =
+		    bus_space_read_4(tag, 0, offset);
+		dest += 4;
+	}
+}
+
+static void bus_space_read_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0) {
+		*dest++ = bus_space_read_4(tag, 0, offset);
+		offset += 4;
+	}
+}
+
+static void bus_space_read_raw_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	size >>= 2;
+	offset += handle;
+	while ((int)--size >= 0) {
+		*(u_int32_t *)dest = bus_space_read_4(tag, 0, offset);
+		offset += 4;
+		dest += 4;
+	}
+}
+
+#define	bus_space_write_4(tag, handle, offset, value) \
+	((void)(tag), *(volatile u_int32_t *)((handle) + (offset)) = (value))
+
+static void bus_space_write_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_4(tag, 0, offset, *dest++);
+}
+
+static void bus_space_write_raw_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 2;
+	while ((int)--size >= 0) {
+		bus_space_write_4(tag, 0, offset, *(u_int32_t *)dest);
+		dest += 4;
+	}
+}
+
+static void bus_space_set_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t, size_t);
+
+static __inline__ void
+bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_4(tag, 0, offset, value);
+}
+
+static void bus_space_write_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0) {
+		bus_space_write_4(tag, 0, offset, *dest++);
+		offset += 4;
+	}
+}
+
+static void bus_space_write_raw_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 2;
+	while ((int)--size >= 0) {
+		bus_space_write_4(tag, 0, offset, *(u_int32_t *)dest);
+		offset += 4;
+		dest += 4;
+	}
+}
+
+static void bus_space_set_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t, size_t);
+
+static __inline__ void
+bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0) {
+		bus_space_write_4(tag, 0, offset, value);
+		offset += 4;
+	}
+}
+
+static void bus_space_copy_4(bus_space_tag_t, bus_space_handle_t, bus_addr_t,
+    bus_space_handle_t, bus_addr_t, bus_size_t);
+
+static __inline__ void
+bus_space_copy_4(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1,
+    bus_space_handle_t h2, bus_addr_t o2, bus_size_t count)
+{
+	o1 += h1;
+	o2 += h2;
+	while ((int)--count >= 0) {
+		*(volatile u_int32_t *)o1 = *(volatile u_int32_t *)o2;
+		o1 += 4;
+		o2 += 4;
+	}
+}
+
+#else	/* __BUS_SPACE_RESTRICT_D16__ */
+
+/*
+ * Restricted D32 access - done through two adjacent D16 access.
+ *
+ * The speed of the basic read and write routines is critical.
+ * This implementation uses a temporary variable on stack, and does
+ * two 16 bit load&store sequences. Since the stack is in Dcache, this
+ * is faster and spills fewer register than a register-only sequence
+ * (which would need to ld.h into two distinct registers, then extu
+ * the second one into itself, and or both in the result register).
+ */
+
+static u_int32_t d16_read_4(vaddr_t);
+static void d16_write_4(vaddr_t, u_int32_t);
+
+static __inline__ u_int32_t
+d16_read_4(vaddr_t va)
+{
+	u_int32_t tmp;
+
+	*(u_int16_t *)&tmp = *(volatile u_int16_t *)va;
+	*(u_int16_t *)((vaddr_t)&tmp + 2) = *(volatile u_int16_t *)(va + 2);
+
+	return tmp;
+}
+
+static __inline__ void
+d16_write_4(vaddr_t va, u_int32_t value)
+{
+	u_int32_t tmp = value;
+
+	*(volatile u_int16_t *)va = *(u_int16_t *)&tmp;
+	*(volatile u_int16_t *)(va + 2) = *(u_int16_t *)((vaddr_t)&tmp + 2);
+}
+
+#define	bus_space_read_4(tag, handle, offset) \
+	((void)(tag), d16_read_4((handle) + (offset)))
+
+static void bus_space_read_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		*dest++ = bus_space_read_4(tag, 0, offset);
+}
+
+static void bus_space_read_raw_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 1;
+	while ((int)--size >= 0) {
+		*(u_int16_t *)dest = bus_space_read_2(tag, 0, offset);
+		dest += 2;
+	}
+}
+
+static void bus_space_read_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *__dest, size_t count)
+{
+	u_int16_t *dest = (u_int16_t *)__dest;
+
+	offset += handle;
+	count <<= 1;
+	while ((int)--count >= 0) {
+		*dest++ = bus_space_read_2(tag, 0, offset);
+		offset += 2;
+	}
+}
+
+static void bus_space_read_raw_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_read_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	size >>= 1;
+	offset += handle;
+	while ((int)--size >= 0) {
+		*(u_int16_t *)dest = bus_space_read_2(tag, 0, offset);
+		offset += 2;
+		dest += 2;
+	}
+}
+
+#define	bus_space_write_4(tag, handle, offset, value) \
+	((void)(tag), d16_write_4((handle) + (offset), (value)))
+
+static void bus_space_write_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *dest, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_4(tag, 0, offset, *dest++);
+}
+
+static void bus_space_write_raw_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_raw_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 1;
+	while ((int)--size >= 0) {
+		bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest);
+		dest += 2;
+	}
+}
+
+static void bus_space_set_multi_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t, size_t);
+
+static __inline__ void
+bus_space_set_multi_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0)
+		bus_space_write_4(tag, 0, offset, value);
+}
+
+static void bus_space_write_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t *, size_t);
+
+static __inline__ void
+bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t *__dest, size_t count)
+{
+	u_int16_t *dest = (u_int16_t *)__dest;
+
+	offset += handle;
+	count <<= 1;
+	while ((int)--count >= 0) {
+		bus_space_write_2(tag, 0, offset, *dest++);
+		offset += 2;
+	}
+}
+
+static void bus_space_write_raw_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int8_t *, size_t);
+
+static __inline__ void
+bus_space_write_raw_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int8_t *dest, size_t size)
+{
+	offset += handle;
+	size >>= 1;
+	while ((int)--size >= 0) {
+		bus_space_write_2(tag, 0, offset, *(u_int16_t *)dest);
+		offset += 2;
+		dest += 2;
+	}
+}
+
+static void bus_space_set_region_4(bus_space_tag_t, bus_space_handle_t,
+    bus_addr_t, u_int32_t, size_t);
+
+static __inline__ void
+bus_space_set_region_4(bus_space_tag_t tag, bus_space_handle_t handle,
+    bus_addr_t offset, u_int32_t value, size_t count)
+{
+	offset += handle;
+	while ((int)--count >= 0) {
+		bus_space_write_4(tag, 0, offset, value);
+		offset += 4;
+	}
+}
+
+static void bus_space_copy_4(bus_space_tag_t, bus_space_handle_t, bus_addr_t,
+    bus_space_handle_t, bus_addr_t, bus_size_t);
+
+static __inline__ void
+bus_space_copy_4(bus_space_tag_t tag, bus_space_handle_t h1, bus_addr_t o1,
+    bus_space_handle_t h2, bus_addr_t o2, bus_size_t count)
+{
+	o1 += h1;
+	o2 += h2;
+	count <<= 1;
+	while ((int)--count >= 0) {
+		*(volatile u_int16_t *)o1 = *(volatile u_int16_t *)o2;
+		o1 += 2;
+		o2 += 2;
+	}
+}
+
+/*
+ * Extra D16 access functions (see vme.c)
+ */
+
+void d16_bcopy(const void *, void *, size_t);
+void d16_bzero(void *, size_t);
+
+#endif	/* __BUS_SPACE_RESTRICT_D16__ */
+
+#endif	/* _AVIION_BUS_H_ */
diff --git a/sys/arch/aviion/include/cpu.h b/sys/arch/aviion/include/cpu.h
new file mode 100644
index 00000000000..3510ef0954b
--- /dev/null
+++ b/sys/arch/aviion/include/cpu.h
@@ -0,0 +1,82 @@
+/* $OpenBSD: cpu.h,v 1.1 2006/05/09 18:19:21 miod Exp $ */
+/*
+ * Copyright (c) 1996 Nivas Madhur
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Lawrence Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef	_AVIION_CPU_H_
+#define	_AVIION_CPU_H_
+
+#include <sys/evcount.h>
+#include <m88k/cpu.h>
+
+#ifdef _KERNEL
+
+/* board dependent pointers */
+extern void	(*md_interrupt_func_ptr)(u_int, struct trapframe *);
+#define	md_interrupt_func	(*md_interrupt_func_ptr)
+extern u_int	(*md_getipl)(void);
+extern u_int	(*md_setipl)(u_int);
+extern u_int	(*md_raiseipl)(u_int);
+extern void	(*md_init_clocks)(void);
+
+struct intrhand {
+	SLIST_ENTRY(intrhand) ih_link;
+	int	(*ih_fn)(void *);
+	void	*ih_arg;
+	int	ih_ipl;
+	int	ih_wantframe;
+	struct evcount ih_count;
+};
+
+int	intr_establish(int, struct intrhand *, const char *);
+
+/*
+ * There are 256 possible vectors on a aviion platform (including
+ * onboard and VME vectors. Use intr_establish() to register a
+ * handler for the given vector. vector number is used to index
+ * into the intr_handlers[] table.
+ */
+#define	NVMEINTR	256
+typedef SLIST_HEAD(, intrhand) intrhand_t;
+extern intrhand_t intr_handlers[NVMEINTR];
+
+void	doboot(void);
+void	nmihand(void *);
+
+#endif /* _KERNEL */
+
+#endif
diff --git a/sys/arch/aviion/include/intr.h b/sys/arch/aviion/include/intr.h
new file mode 100644
index 00000000000..dbd1ed4057c
--- /dev/null
+++ b/sys/arch/aviion/include/intr.h
@@ -0,0 +1,55 @@
+/*	$OpenBSD: intr.h,v 1.1 2006/05/09 18:19:31 miod Exp $	*/
+/*
+ * Copyright (C) 2000 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AVIION_INTR_H_
+#define _AVIION_INTR_H_
+
+/*
+ * IPL levels.
+ * We use 6 as IPL_HIGH so that abort can be programmed at 7 so that
+ * it is always possible to break into the system unless interrupts
+ * are disabled.
+ */
+
+#define IPL_NONE	0
+#define IPL_SOFTCLOCK	1
+#define IPL_SOFTNET	1
+#define IPL_BIO		2
+#define IPL_NET		3
+#define IPL_TTY		3
+#define IPL_VM		3
+#define IPL_CLOCK	5
+#define IPL_STATCLOCK	5
+#define	IPL_SCHED	5
+#define IPL_HIGH	6
+#define IPL_NMI		7
+#define IPL_ABORT	7
+
+#include <m88k/intr.h>
+
+#endif /* _AVIION_INTR_H_ */
diff --git a/sys/arch/aviion/include/m8820x.h b/sys/arch/aviion/include/m8820x.h
new file mode 100644
index 00000000000..4d39e74c6ae
--- /dev/null
+++ b/sys/arch/aviion/include/m8820x.h
@@ -0,0 +1,62 @@
+#ifndef	_AVIION_M8820X_H_
+#define	_AVIION_M8820X_H_
+/*	$OpenBSD: m8820x.h,v 1.1 2006/05/09 18:19:36 miod Exp $ */
+/*
+ * Copyright (c) 2004, Miodrag Vallat.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1993-1992 Carnegie Mellon University
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+ * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie Mellon
+ * the rights to redistribute these changes.
+ */
+
+/*
+ * Code features to enable
+ */
+
+#define	M88200_HAS_SPLIT_ADDRESS
+
+#include <m88k/m8820x.h>
+
+#endif	/* _AVIION_M8820X_H_ */
diff --git a/sys/arch/aviion/include/param.h b/sys/arch/aviion/include/param.h
new file mode 100644
index 00000000000..2bbb019d23a
--- /dev/null
+++ b/sys/arch/aviion/include/param.h
@@ -0,0 +1,52 @@
+/*	$OpenBSD: param.h,v 1.1 2006/05/09 18:19:04 miod Exp $ */
+/*
+ * Copyright (c) 1999 Steve Murphree, Jr.
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1982, 1986, 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah $Hdr: machparam.h 1.11 89/08/14$
+ *
+ *	@(#)param.h	7.8 (Berkeley) 6/28/91
+ */
+
+#ifndef _MACHINE_PARAM_H_
+#define _MACHINE_PARAM_H_
+
+#define  _MACHINE       aviion
+#define  MACHINE        "aviion"
+
+#include <m88k/param.h>
+
+#define KERNBASE	0x00000000	/* start of kernel virtual */
+#define	KERNTEXTOFF	0x00001000	/* start of kernel text */
+
+#endif /* !_MACHINE_PARAM_H_ */
diff --git a/sys/arch/aviion/include/prom.h b/sys/arch/aviion/include/prom.h
new file mode 100644
index 00000000000..49863f505a4
--- /dev/null
+++ b/sys/arch/aviion/include/prom.h
@@ -0,0 +1,77 @@
+/*	$OpenBSD: prom.h,v 1.1 2006/05/09 18:19:43 miod Exp $	*/
+/*
+ * Copyright (c) 2006, Miodrag Vallat.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __AVIION_PROM_H__
+#define __AVIION_PROM_H__
+
+#include <sys/cdefs.h>
+
+/* SCM trap vector */
+#define	SCM_VECTOR		496
+
+/* system calls */
+#define	SCM_CHAR		0x00
+#define	SCM_OCHAR		0x20
+#define	SCM_PTLINE		0x21
+#define	SCM_OCRLF		0x26
+#define	SCM_HALT		0x63
+#define	SCM_STDIO		0x70
+#define	SCM_REBOOT		0x101
+#define	SCM_CPUID		0x102
+#define	SCM_MSIZE		0x103
+#define	SCM_REVNUM		0x104
+#define	SCM_HOSTID		0x107
+#define	SCM_INVALID		0x112
+#define	SCM_COMMID		0x114
+
+/* 88204 PROMs only system calls */
+#define	SCM_SYSID		0x31
+#define	SCM_CPUCONFIG		0x107
+
+struct	scm_cpuconfig {
+	u_int32_t	version;
+#define	SCM_CPUCONFIG_VERSION	0
+	u_int32_t	cpucount;	/* # of CPUs */
+	u_int16_t	igang, dgang;	/* # of CMMUs per CPU */
+	u_int32_t	isplit, dsplit;	/* CMMU split bits */
+	u_int32_t	:32;
+};
+
+int	scm_cpuconfig(struct scm_cpuconfig *);
+u_int	scm_cpuid(void);
+int	scm_getc(void);
+void	scm_getenaddr(u_char *);
+__dead void scm_halt(void);
+u_int	scm_memsize(void);
+u_int	scm_promver(void);
+void	scm_putc(int);
+void	scm_putcrlf(void);
+__dead void scm_reboot(const char *);
+u_int	scm_sysid(void);
+
+extern u_int32_t scmvec[2], osvec[2];		/* SCM trap vector copies */
+
+#endif /* __AVIION_PROM_H__ */