Switch hp300 wscons code to rasops, for DIO frame buffers.

Features:
- coloured kernel messages
- color support in console (use TERM=wsvt25)
- pretty Gallant wsfont, rather than the acceptable or ugly (depending upon
  the frame buffer) ROM font
- colormap ioctl support for Gatorbox and Topcat; DaVinci and Renaissance
  not done due to lack of hardware and/or documentation
- even more code factorization

tested on hyperion, and 4/6/8bpp catseye/topcat/kathmandu hardware, by
millert@ and I

1 files changed, 3 insertions, 28 deletions

diff --git a/sys/arch/hp300/dev/gboxreg.h b/sys/arch/hp300/dev/gboxreg.h
index f1d35c5fb24..64597b6cc85 100644
--- a/sys/arch/hp300/dev/gboxreg.h
+++ b/sys/arch/hp300/dev/gboxreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: gboxreg.h,v 1.1 2005/01/14 22:39:25 miod Exp $	*/
+/*	$OpenBSD: gboxreg.h,v 1.2 2005/01/24 21:36:39 miod Exp $	*/
 /*	$NetBSD: grf_gbreg.h,v 1.4 1994/10/26 07:23:53 cgd Exp $	*/
 
 /*
@@ -52,7 +52,7 @@
 
 #define tile_mover_waitbusy(regaddr)					\
 do {									\
-	while (((struct gboxfb *)(regaddr))->sec_interrupt & 0x10)	\
+	while (((struct gboxfb *)(regaddr))->regs.sec_interrupt & 0x10)	\
 		DELAY(1);						\
 } while (0)
 
@@ -69,32 +69,7 @@ do {									\
 } while (0)
 
 struct gboxfb {
-	u_int8_t :8;
-	u_int8_t reset;			/* reset register		0x01 */
-	u_int8_t sec_interrupt;		/* Secondary interrupt register 0x03 */
-	u_int8_t interrupt;		/* interrupt register		0x03 */
-	u_int8_t :8;
-	u_int8_t fbwmsb;		/* frame buffer width MSB	0x05 */
-	u_int8_t :8;
-	u_int8_t fbwlsb;		/* frame buffer width MSB	0x07 */
-	u_int8_t :8;
-	u_int8_t fbhmsb;		/* frame buffer height MSB	0x09 */
-	u_int8_t :8;
-	u_int8_t fbhlsb;		/* frame buffer height MSB	0x0b */
-	u_int8_t :8;
-	u_int8_t dwmsb;			/* display width MSB		0x0d */
-	u_int8_t :8;
-	u_int8_t dwlsb;			/* display width MSB		0x0f */
-	u_int8_t :8;
-	u_int8_t dhmsb;			/* display height MSB		0x11 */
-	u_int8_t :8;
-	u_int8_t dhlsb;			/* display height MSB		0x13 */
-	u_int8_t :8;
-	u_int8_t fbid;			/* Scondary frame buffer id	0x15 */
-	u_int8_t f1[0x5d-0x15-1];
-	u_int8_t fbomsb;		/* frame buffer offset MSB	0x5d */
-	u_int8_t :8;
-	u_int8_t fbolsb;		/* frame buffer offset LSB	0x5f */
+	struct diofbreg regs;
 	u_int8_t f2[0x4000-0x5f-1];
 	u_int8_t crtc_address;		/* CTR controller address reg 0x4000 */
 	u_int8_t status;		/* Status register	      0x4001 */