remove all those "black magic" inspired routines,

use PDC calls instead, which is more MI.
we also don't need pmap_map to be defined any more, unless
kernel mapping enforced through FORCE_MAP_KERNEL definition.

1 files changed, 51 insertions, 197 deletions

diff --git a/sys/arch/hppa/include/cpufunc.h b/sys/arch/hppa/include/cpufunc.h
index f6fd259b2d7..3694bc037ee 100644
--- a/sys/arch/hppa/include/cpufunc.h
+++ b/sys/arch/hppa/include/cpufunc.h
@@ -1,6 +1,35 @@
-/*	$OpenBSD: cpufunc.h,v 1.2 1998/08/29 01:56:55 mickey Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.3 1998/10/30 22:16:42 mickey Exp $	*/
 
 /*
+ * Copyright (c) 1998 Michael Shalayeff
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Michael Shalayeff.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
  *  (c) Copyright 1988 HEWLETT-PACKARD COMPANY
  *
  *  To anyone who acknowledges that this file is provided "AS IS"
@@ -29,15 +58,16 @@
  *	Author: Bob Wheeler, University of Utah CSL
  */
 
-#ifndef _HPPA_CPUFUNC_H_
-#define _HPPA_CPUFUNC_H_
+#ifndef _MACHINE_CPUFUNC_H_
+#define _MACHINE_CPUFUNC_H_
 
 #include <machine/psl.h>
 #include <machine/pte.h>
 
-#define tlbbtop(b) (((b) & ~PGOFSET) >> (PGSHIFT - 5))
+#define tlbbtop(b) ((b) >> (PGSHIFT - 5))
 #define tlbptob(p) ((p) << (PGSHIFT - 5))
 
+#define hptbtop(b) ((b) >> 17)
 
 /* Get space register for an address */
 static __inline u_int ldsid(vm_offset_t p) {
@@ -46,71 +76,9 @@ static __inline u_int ldsid(vm_offset_t p) {
 	return ret;
 }
 
-/* Disable SID hashing and flush all caches for S-CHIP */
-static __inline u_int disable_S_sid_hashing(void) {
-	register u_int t, ret;
-	__asm ("mfcpu	(0,%1)\n\t"	/* get cpu diagnosic register */
-	       "mfcpu	(0,%1)\n\t"	/* black magic */
-	       "copy	%1,%0\n\t"
-	       "depi	0,20,3,%1\n\t"	/* clear DHE, domain and IHE bits */
-	       "depi	1,16,1,%1\n\t"	/* enable quad-word stores */
-	       "depi	0,10,1,%1\n\t"	/* do not clear the DHPMC bit */
-	       "depi	0,14,1,%1\n\t"	/* do not clear the ILPMC bit */
-	       "mtcpu	(%1,0)\n\t"	/* set the cpu disagnostic register */
-	       "mtcpu	(%1,0)\n\t"	/* black magic */
-	       : "=r" (ret) : "r" (t));
-	return ret;
-}
-
-/* Disable SID hashing and flush all caches for T-CHIP */
-static __inline u_int disable_T_sid_hashing(void) {
-	register u_int t, ret;
-	__asm("mfcpu	(0,%1)\n\t"	/* get cpu diagnosic register */
-	      "mfcpu	(0,%1)\n\t"	/* black magic */
-	      "copy	%1,%0\n\t"
-	      "depi	0,18,1,%1\n\t"	/* clear DHE bit */
-	      "depi	0,20,1,%1\n\t"	/* clear IHE bit */
-	      "depi	0,10,1,%1\n\t"	/* do not clear the DHPMC bit */
-	      "depi	0,14,1,%1\n\t"	/* do not clear the ILPMC bit */
-	      "mtcpu	(%1,0)\n\t"	/* set the cpu disagnostic register */
-	      "mtcpu	(%1,0)\n\t"	/* black magic */
-	       : "=r" (ret) : "r" (t));
-	return ret;
-}
-
-/* Disable SID hashing and flush all caches for L-CHIP */
-static __inline u_int disable_L_sid_hashing(void) {
-	register u_int t, ret;
-	__asm("mfcpu2	(0,%1)\n\t"	/* get cpu diagnosic register  */
-/*	      ".word	0x14160600\n\t" */
-	      "copy	%1,%0\n\t"
-	      "depi	0,27,1,%1\n\t"	/* clear DHE bit */
-	      "depi	0,28,1,%1\n\t"	/* clear IHE bit */
-	      "depi	0,6,1,%1\n\t"	/* do not clear the L2IHPMC bit */
-	      "depi	0,8,1,%1\n\t"	/* do not clear the L2DHPMC bit */
-	      "depi	0,10,1,%1\n\t"	/* do not clear the L1IHPMC bit */
-	      "mtcpu2	(%1,0)"		/* set the cpu disagnostic register */ 
-/*	      ".word	0x14160240\n\t" */
-	       : "=r" (ret) : "r" (t));
-	return ret;
-}
-
-static __inline u_int get_dcpu_reg(void) {
-	register u_int ret;
-	__asm("mfcpu	(0,%0)\n\t"	/* Get cpu diagnostic register */
-	      "mfcpu	(0,%0)": "=r" (ret));	/* black magic */
-	return ret;
-}
-
 #define mtctl(v,r) __asm __volatile("mtctl %0,%1":: "r" (v), "i" (r))
 #define mfctl(r,v) __asm __volatile("mfctl %1,%0": "=r" (v): "i" (r))
 
-#define mtcpu(v,r) __asm __volatile("mtcpu %0,%1":: "r" (v), "i" (r))
-#define mfcpu(r,v) __asm __volatile("mfcpu %1,%0": "=r" (v): "i" (r))
-
-#define mtcpu2(v,r) __asm __volatile("mtcpu2 %0,%1":: "r" (v), "i" (r))
-#define mfcpu2(r,v) __asm __volatile("mfcpu2 %1,%0": "=r" (v): "i" (r))
-
 #define mtsp(v,r) __asm __volatile("mtsp %0,%1":: "r" (v), "i" (r))
 #define mfsp(r,v) __asm __volatile("mfsp %1,%0": "=r" (v): "i" (r))
 
@@ -125,19 +93,22 @@ static __inline u_int mtsm(u_int mask) {
 	return ret;
 }
 
+#if 0
 static __inline void set_psw(u_int psw) {
-	__asm __volatile("mtctl %%r0, %%cr17\n\t"
+	__asm __volatile("mtctl %0, %%cr22\n\t"
 			 "mtctl %%r0, %%cr17\n\t"
-			 "ldil L%%.+32, %%r21\n\t"
-			 "ldo R%%.+28(%%r21), %%r21\n\t"
-			 "mtctl %%r21, %%cr17\n\t"
-			 "ldo 4(%%r21), %%r21\n\t"
-			 "mtctl %%r21, %%cr17\n\t"
-			 "mtctl %0, %%cr22\n\t"
-			 "rfi\n\t"
-			 "nop\n\tnop\n\tnop\n\tnop"
-			 :: "r" (psw): "r21");
-}
+			 "mtctl %%r0, %%cr17\n\t"
+			 "ldil L%%., %0\n\t"
+			 "ldo R%%.+24(%0), %0\n\t"
+			 "mtctl %0, %%cr18\n\t"
+			 "ldo 4(%0), %0\n\t"
+			 "mtctl %0, %%cr18\n\t"
+			 "rfi\n\tnop\n\tnop"
+			 :: "r" (psw));
+}
+#else
+void set_psw __P((u_int psw));
+#endif
 
 #define	fdce(sp,off) __asm __volatile("fdce 0(%0,%1)":: "i" (sp), "r" (off))
 #define	fice(sp,off) __asm __volatile("fdce 0(%0,%1)":: "i" (sp), "r" (off))
@@ -212,129 +183,12 @@ pdtlbe(pa_space_t sp, vm_offset_t off)
 	__asm volatile("pdtlbe %%r0(%%sr1, %0)":: "r" (off));
 }
 
-static __inline void
-ibitlb(int i, vm_offset_t pa, vm_offset_t va, vm_size_t sz, u_int prot)
-{
-
-}
-
-static __inline void
-pbitlb(int i)
-{
-}
-
-static __inline void
-ibdtlb(int i, vm_offset_t pa, vm_offset_t va, vm_size_t sz, u_int prot)
-{
-
-}
-
-static __inline void
-pbdtlb(int i)
-{
-}
-
-static __inline void
-ibctlb(int i, vm_offset_t pa, vm_offset_t va, vm_size_t sz, u_int prot)
-{
-	register u_int psw, t;
-
-	rsm(PSW_R|PSW_I,psw);
-
-	t = 0x7fc1|((i&15)<<1);	/* index 127, lockin, override, mismatch */
-	mtcpu(t,8);		/* move to the dtlb diag reg */
-	mtcpu(t,8);		/* black magic */
-
-	prot |= TLB_DIRTY;
-	sz = (~sz >> 7) & 0x7f000;
-	pa = (tlbbtop(pa) & 0x7f000) | sz;
-	va = (va & 0x7f000) | sz;
-
-	idtlba(pa, 0, va);
-	idtlbp(prot, 0, va);
-
-	t |= 0x2000;		/* no lockout, PE force-ins disable */
-	mtcpu2(t,8);		/* move to the dtlb diagnostic register */
-
-	mtsm(psw);
-}
-
-static __inline void
-pbctlb(int i)
-{
-	register u_int psw, t;
-
-	rsm(PSW_R|PSW_I,psw);
-
-	t = 0xffc1|((i&15)<<1);	/* index 127, lockin, override, mismatch */
-	mtcpu(t,8);		/* move to the dtlb diag reg */
-	mtcpu(t,8);		/* black magic */
-
-	idtlba(0,0,0);		/* address does not matter */
-	idtlbp(0,0,0);
-
-	t |= 0x7f << 7;
-	mtcpu(t,8);		/* move to the dtlb diagnostic register */
-	mtcpu(t,8);		/* black magic */
-
-	mtsm(psw);
-}
-
-static __inline void
-iLbctlb(int i, vm_offset_t pa, vm_offset_t va, vm_offset_t sz, u_int prot)
-{
-	register u_int psw, t;
-
-	rsm(PSW_R|PSW_I,psw);
-
-	t = 0x6041| ((i&7)<<1);	/* lockin, PE force-insert disable,
-				   PE LRU-ins dis, BE force-ins enable
-				   set the block enter select bit */
-	mtcpu2(t, 8);		/* move to the dtlb diagnostic register */
-
-	prot |= TLB_DIRTY;
-	sz = (~sz >> 7) & 0x7f000;
-	pa = (tlbbtop(pa) & 0x7f000) | sz;
-	va = (va & 0x7f000) | sz;
-
-	/* we assume correct address/size alignment */
-	idtlba(pa, 0, va);
-	idtlbp(prot, 0, va);
-
-	t |= 0x2000;		/* no lockin, PE force-ins disable */
-	mtcpu2(t, 8);		/* move to the dtlb diagnostic register */
-
-	mtsm(psw);
-}
-
-static __inline void
-pLbctlb(int i)
-{
-	register u_int psw, t;
-
-	rsm(PSW_R|PSW_I,psw);
-
-	t = 0xc041| ((i&7)<<1);	/* lockout, PE force-insert disable,
-				   PE LRU-ins dis, BE force-ins enable
-				   set the block enter select bit */
-	mtcpu2(t,8);		/* move to the dtlb diagnostic register */
-
-	idtlba(0,0,0);		/* address does not matter */
-	idtlbp(0,0,0);
-
-	t |= 0x2000;		/* no lockout, PE force-ins disable */
-	mtcpu2(t,8);		/* move to the dtlb diagnostic register */
-
-	mtsm(psw);
-}
-
 #ifdef _KERNEL
 struct pdc_cache;
 void fcacheall __P((struct pdc_cache *));
 void ptlball __P((struct pdc_cache *));
+int btlb_insert __P((int i, pa_space_t space, vm_offset_t va, vm_offset_t pa,
+		     vm_size_t *lenp, u_int prot));
 #endif
 
-#endif /* _HPPA_CPUFUNC_H_ */
-
-
-
+#endif /* _MACHINE_CPUFUNC_H_ */