force alignment on the netisr and sir by mobving 'em into .data

and allocating space in the locore (ldcw require a 16byte alignment).
inform gcc that ldcw will change the memory (in asm()).
fix spl handling in the soft intrs piece.

2 files changed, 20 insertions, 12 deletions

diff --git a/sys/arch/hppa/hppa/locore.S b/sys/arch/hppa/hppa/locore.S
index bd9a0636f5e..2996f29c833 100644
--- a/sys/arch/hppa/hppa/locore.S
+++ b/sys/arch/hppa/hppa/locore.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: locore.S,v 1.68 2002/05/20 03:46:53 mickey Exp $	*/
+/*	$OpenBSD: locore.S,v 1.69 2002/05/20 07:59:11 mickey Exp $	*/
 
 /*
  * Copyright (c) 1998-2002 Michael Shalayeff
@@ -124,6 +124,14 @@ $trap_tmp_save			/* XXX assumed to be aligned on 2048 */
 	BSS(fpu_enable, 4)	/* bits to set in the ccr to enable fpu */
 	.export hppa_vtop, data
 	BSS(hppa_vtop, 4)	/* a vtop translation table addr (pa=va) */
+	.export netisr, data
+	.align 16
+netisr
+	.word	0
+	.export sir, data
+	.align 16
+sir
+	.word	0
 
 	.text
 	.import	$kernel_setup, entry
diff --git a/sys/arch/hppa/hppa/trap.c b/sys/arch/hppa/hppa/trap.c
index d060904ec74..e999992c02e 100644
--- a/sys/arch/hppa/hppa/trap.c
+++ b/sys/arch/hppa/hppa/trap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.c,v 1.42 2002/05/16 21:11:14 miod Exp $	*/
+/*	$OpenBSD: trap.c,v 1.43 2002/05/20 07:59:11 mickey Exp $	*/
 
 /*
  * Copyright (c) 1998-2001 Michael Shalayeff
@@ -89,7 +89,6 @@ const char *trap_type[] = {
 };
 int trap_types = sizeof(trap_type)/sizeof(trap_type[0]);
 
-u_int32_t sir;
 int want_resched, astpending;
 
 void syscall(struct trapframe *frame, int *args);
@@ -130,6 +129,7 @@ trap(type, frame)
 	int type;
 	struct trapframe *frame;
 {
+	extern u_int32_t sir;
 	struct proc *p = curproc;
 	struct pcb *pcbp;
 	vaddr_t va;
@@ -384,25 +384,25 @@ return;
 #endif
 		/* FALLTHROUGH */
 	case T_LOWERPL:
-		__asm __volatile ("ldcws 0(%1), %0"
-				  : "=r" (si) : "r" (&sir));
-		s = spl0();
+		__asm __volatile (
+		    "ldcws 0(%1), %0" : "=&r" (si) : "r" (&sir) : "memory");
 		if (si & SIR_CLOCK) {
-			splclock();
+			s = splsoftclock();
 			softclock();
-			spl0();
+			splx(s);
 		}
 
 		if (si & SIR_NET) {
 			register int ni;
 			/* use atomic "load & clear" */
-			__asm __volatile ("ldcws 0(%1), %0"
-					  : "=r" (ni) : "r" (&netisr));
-			splnet();
+			__asm __volatile (
+			    "ldcws 0(%1), %0"
+			    : "=&r" (ni) : "r" (&netisr) : "memory");
+			s = splnet();
 #define	DONETISR(m,c) if (ni & (1 << (m))) c()
 #include <net/netisr_dispatch.h>
+			splx(s);
 		}
-		splx(s);
 		break;
 
 	case T_DPROT: