debranch SMP, have fun

27 files changed, 1951 insertions, 123 deletions

diff --git a/sys/arch/i386/include/apicvar.h b/sys/arch/i386/include/apicvar.h
new file mode 100644
index 00000000000..aac452fca40
--- /dev/null
+++ b/sys/arch/i386/include/apicvar.h
@@ -0,0 +1,57 @@
+/*	$OpenBSD: apicvar.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/* $NetBSD: apicvar.h,v 1.1.2.3 2000/02/27 20:25:00 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_APICVAR_H_
+#define _I386_APICVAR_H_
+
+struct apic_attach_args {
+	const char *aaa_name;
+	int apic_id;
+	int apic_version;
+	int flags;
+#define IOAPIC_PICMODE		0x01
+#define IOAPIC_VWIRE		0x02
+	paddr_t apic_address;
+};
+
+void apic_format_redir(char *, char *, int, u_int32_t, u_int32_t);
+
+#endif /* !_I386_APICVAR_H_ */
diff --git a/sys/arch/i386/include/asm.h b/sys/arch/i386/include/asm.h
index 2126271a519..f2da5755a33 100644
--- a/sys/arch/i386/include/asm.h
+++ b/sys/arch/i386/include/asm.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: asm.h,v 1.7 2003/06/02 23:27:47 millert Exp $	*/
+/*	$OpenBSD: asm.h,v 1.8 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: asm.h,v 1.7 1994/10/27 04:15:56 cgd Exp $	*/
 
 /*-
@@ -61,6 +61,16 @@
 #define _C_LABEL(name)	name
 #define	_ASM_LABEL(x)	x
 
+#define CVAROFF(x, y)	_C_LABEL(x) + y
+
+#ifdef __STDC__
+# define __CONCAT(x,y)	x ## y
+# define __STRING(x)	#x
+#else
+# define __CONCAT(x,y)	x/**/y
+# define __STRING(x)	"x"
+#endif
+
 /*
  * WEAK ALIAS: create a weak alias
  */
diff --git a/sys/arch/i386/include/atomic.h b/sys/arch/i386/include/atomic.h
new file mode 100644
index 00000000000..e3be6b68b1b
--- /dev/null
+++ b/sys/arch/i386/include/atomic.h
@@ -0,0 +1,72 @@
+/*	$OpenBSD: atomic.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/* $NetBSD: atomic.h,v 1.1.2.2 2000/02/21 18:54:07 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ATOMIC_H_
+#define _ATOMIC_H_
+
+#ifndef _LOCORE
+
+static __inline u_int32_t
+i386_atomic_testset_ul (volatile u_int32_t *ptr, unsigned long val) {
+    __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
+    return val;
+}
+
+static __inline int
+i386_atomic_testset_i (volatile int *ptr, unsigned long val) {
+    __asm__ volatile ("xchgl %0,(%2)" :"=r" (val):"0" (val),"r" (ptr));
+    return val;
+}
+
+static __inline void 
+i386_atomic_setbits_l (volatile u_int32_t *ptr, unsigned long bits) {
+    __asm __volatile("lock ; orl %1,%0" :  "=m" (*ptr) : "ir" (bits));
+}
+
+static __inline void 
+i386_atomic_clearbits_l (volatile u_int32_t *ptr, unsigned long bits) {
+    bits = ~bits;
+    __asm __volatile("lock ; and %1,%0" :  "=m" (*ptr) : "ir" (bits));
+}
+
+#endif
+#endif
+
diff --git a/sys/arch/i386/include/biosvar.h b/sys/arch/i386/include/biosvar.h
index 4fc00866e87..7e4d98933b4 100644
--- a/sys/arch/i386/include/biosvar.h
+++ b/sys/arch/i386/include/biosvar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: biosvar.h,v 1.42 2003/11/27 00:31:55 espie Exp $	*/
+/*	$OpenBSD: biosvar.h,v 1.43 2004/06/13 21:49:16 niklas Exp $	*/
 
 /*
  * Copyright (c) 1997-1999 Michael Shalayeff
@@ -192,6 +192,8 @@ typedef struct _bios_consdev {
 	int	conspeed;
 } bios_consdev_t;
 
+#define BOOTARG_SMPINFO 6		/* struct mp_float[] */
+
 #if defined(_KERNEL) || defined (_STANDALONE)
 
 #ifdef _LOCORE
@@ -244,6 +246,8 @@ int  bios32_service(u_int32_t, bios32_entry_t, bios32_entry_info_t);
 
 extern u_int bootapiver;
 extern bios_memmap_t *bios_memmap;
+extern void *bios_smpinfo;
+extern bios_pciinfo_t *bios_pciinfo;
 
 #endif /* _KERNEL */
 #endif /* _LOCORE */
diff --git a/sys/arch/i386/include/cpu.h b/sys/arch/i386/include/cpu.h
index cc690de9219..9d66a9c496c 100644
--- a/sys/arch/i386/include/cpu.h
+++ b/sys/arch/i386/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.60 2004/06/06 17:34:37 grange Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.61 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: cpu.h,v 1.35 1996/05/05 19:29:26 christos Exp $	*/
 
 /*-
@@ -41,9 +41,19 @@
 /*
  * Definitions unique to i386 cpu support.
  */
-#include <machine/psl.h>
 #include <machine/frame.h>
+#include <machine/psl.h>
 #include <machine/segments.h>
+#include <machine/intrdefs.h>
+
+#ifdef MULTIPROCESSOR
+#include <machine/i82489reg.h>
+#include <machine/i82489var.h>
+
+/* XXX for now... */
+#define NLAPIC 1
+
+#endif
 
 /*
  * definitions of cpu-dependent requirements
@@ -60,16 +70,156 @@
  */
 #define clockframe intrframe
 
-#define	CLKF_USERMODE(frame)	USERMODE((frame)->if_cs, (frame)->if_eflags)
-#define	CLKF_PC(frame)		((frame)->if_eip)
-#define	CLKF_INTR(frame)	(IDXSEL((frame)->if_cs) == GICODE_SEL)
+#include <sys/device.h>
+#include <sys/lock.h>                  /* will also get LOCKDEBUG */
+#include <sys/proc.h>
+
+struct intrsource;
+
+/* XXX stuff to move to cpuvar.h later */
+struct cpu_info {
+	struct device ci_dev;		/* our device */
+	struct cpu_info *ci_self;	/* pointer to this structure */
+	struct schedstate_percpu ci_schedstate; /* scheduler state */
+	struct cpu_info *ci_next;	/* next cpu */
+	
+	/* 
+	 * Public members. 
+	 */
+	struct proc *ci_curproc; 	/* current owner of the processor */
+	struct simplelock ci_slock;	/* lock on this data structure */
+	cpuid_t ci_cpuid; 		/* our CPU ID */
+	u_int ci_apicid;		/* our APIC ID */
+#if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
+	u_long ci_spin_locks;		/* # of spin locks held */
+	u_long ci_simple_locks;		/* # of simple locks held */
+#endif
+
+	/*
+	 * Private members.
+	 */
+	struct proc *ci_fpcurproc;	/* current owner of the FPU */
+	int ci_fpsaving;		/* save in progress */
+
+	volatile u_int32_t ci_tlb_ipi_mask;
+
+	struct pcb *ci_curpcb;		/* VA of current HW PCB */
+	struct pcb *ci_idle_pcb;	/* VA of current PCB */
+	int ci_idle_tss_sel;		/* TSS selector of idle PCB */
+
+	struct intrsource *ci_isources[MAX_INTR_SOURCES];
+	u_int32_t	ci_ipending;
+	int		ci_ilevel;
+	int		ci_idepth;
+	u_int32_t	ci_imask[NIPL];
+	u_int32_t	ci_iunmask[NIPL];
+
+	paddr_t ci_idle_pcb_paddr;	/* PA of idle PCB */
+	u_long ci_flags;		/* flags; see below */
+	u_int32_t ci_ipis; 		/* interprocessor interrupts pending */
+	int sc_apic_version;  		/* local APIC version */
+	
+	u_int32_t	ci_level;
+	u_int32_t	ci_vendor[4];
+	u_int32_t	ci_signature;		/* X86 cpuid type */
+	u_int32_t	ci_feature_flags;	/* X86 CPUID feature bits */
+	u_int32_t	cpu_class;		/* CPU class */
+
+	struct cpu_functions *ci_func;	/* start/stop functions */
+	void (*cpu_setup)(const char *, int, int);	/* proc-dependant init */
+
+	int		ci_want_resched;
+	int		ci_astpending;
+
+	union descriptor *ci_gdt;
+
+	volatile int ci_ddb_paused;	/* paused due to other proc in ddb */
+#define CI_DDB_RUNNING		0
+#define CI_DDB_SHOULDSTOP	1
+#define CI_DDB_STOPPED		2
+#define CI_DDB_ENTERDDB		3
+#define CI_DDB_INDDB		4
+};
+
+/*
+ * Processor flag notes: The "primary" CPU has certain MI-defined
+ * roles (mostly relating to hardclock handling); we distinguish
+ * betwen the processor which booted us, and the processor currently
+ * holding the "primary" role just to give us the flexibility later to
+ * change primaries should we be sufficiently twisted.  
+ */
+
+#define	CPUF_BSP	0x0001		/* CPU is the original BSP */
+#define	CPUF_AP		0x0002		/* CPU is an AP */
+#define	CPUF_SP		0x0004		/* CPU is only processor */
+#define	CPUF_PRIMARY	0x0008		/* CPU is active primary processor */
+#define	CPUF_APIC_CD	0x0010		/* CPU has apic configured */
+
+#define	CPUF_PRESENT	0x1000		/* CPU is present */
+#define	CPUF_RUNNING	0x2000		/* CPU is running */
 
 /*
- * Preempt the current process if in interrupt from user mode,
+ * We statically allocate the CPU info for the primary CPU (or,
+ * the only CPU on uniprocessors), and the primary CPU is the
+ * first CPU on the CPU info list.
+ */
+extern struct cpu_info cpu_info_primary;
+extern struct cpu_info *cpu_info_list;
+
+#define	CPU_INFO_ITERATOR		int
+#define	CPU_INFO_FOREACH(cii, ci)	cii = 0, ci = cpu_info_list; \
+					ci != NULL; ci = ci->ci_next
+
+#ifdef MULTIPROCESSOR
+
+#define I386_MAXPROCS		32	/* because we use a bitmask */
+
+#define CPU_STARTUP(_ci)	((_ci)->ci_func->start(_ci))
+#define CPU_STOP(_ci)		((_ci)->ci_func->stop(_ci))
+#define CPU_START_CLEANUP(_ci)	((_ci)->ci_func->cleanup(_ci))
+
+#define cpu_number()		(i82489_readreg(LAPIC_ID)>>LAPIC_ID_SHIFT)
+#define	curcpu()		(cpu_info[cpu_number()])
+
+#define CPU_IS_PRIMARY(ci)	((ci)->ci_flags & CPUF_PRIMARY)
+
+extern struct cpu_info	*cpu_info[I386_MAXPROCS];
+extern u_long		 cpus_running;
+
+extern void cpu_boot_secondary_processors(void);
+extern void cpu_init_idle_pcbs(void);
+
+#else /* MULTIPROCESSOR */
+
+#define I386_MAXPROCS		1
+
+#define cpu_number()		0
+#define	curcpu()		(&cpu_info_primary)
+
+#define CPU_IS_PRIMARY(ci)	1
+
+/*
+ * definitions of cpu-dependent requirements
+ * referenced in generic code
+ */
+#define	cpu_swapin(p)			/* nothing */
+
+#endif
+
+#define curpcb			curcpu()->ci_curpcb
+
+#define want_resched (curcpu()->ci_want_resched)
+#define astpending (curcpu()->ci_astpending)
+
+/*
+ * Preemt the current process if in interrupt from user monre,
  * or after the current trap/syscall if in system mode.
  */
-int	want_resched;		/* resched() was called */
-#define	need_resched()		(want_resched = 1, setsoftast())
+extern void need_resched(struct cpu_info *);
+
+#define	CLKF_USERMODE(frame)	USERMODE((frame)->if_cs, (frame)->if_eflags)
+#define	CLKF_PC(frame)		((frame)->if_eip)
+#define	CLKF_INTR(frame)	(IDXSEL((frame)->if_cs) == GICODE_SEL)
 
 /*
  * Give a profiling tick to the current process when the user profiling
@@ -87,8 +237,13 @@ int	want_resched;		/* resched() was called */
 /*
  * We need a machine-independent name for this.
  */
-#define	DELAY(x)		delay(x)
-void	delay(int);
+extern void (*delay_func)(int);
+struct timeval;
+extern void (*microtime_func)(struct timeval *);
+
+#define	DELAY(x)		(*delay_func)(x)
+#define delay(x)		(*delay_func)(x)
+#define microtime(tv)		(*microtime_func)(tv)
 
 #if defined(I586_CPU) || defined(I686_CPU)
 /*
@@ -173,6 +328,7 @@ extern void (*update_cpuspeed)(void);
 void	dumpconf(void);
 void	cpu_reset(void);
 void	i386_proc0_tss_ldt_init(void);
+void	i386_init_pcb_tss_ldt(struct cpu_info *);
 void	cpuid(u_int32_t, u_int32_t *);
 
 /* locore.s */
@@ -189,6 +345,9 @@ void	proc_trampoline(void);
 void	initrtclock(void);
 void	startrtclock(void);
 void	rtcdrain(void *);
+void	i8254_delay(int);
+void	i8254_microtime(struct timeval *);
+void	i8254_initclocks(void);
 
 /* est.c */
 #if !defined(SMALL_KERNEL) && defined(I686_CPU)
@@ -213,8 +372,9 @@ int	k6_powernow_setperf(int);
 
 
 /* npx.c */
-void	npxdrop(void);
-void	npxsave(void);
+void	npxdrop(struct proc *);
+void	npxsave_proc(struct proc *, int);
+void	npxsave_cpu(struct cpu_info *, int);
 
 #if defined(GPL_MATH_EMULATE)
 /* math_emulate.c */
@@ -230,6 +390,7 @@ int	i386_set_ldt(struct proc *, void *, register_t *);
 
 /* isa_machdep.c */
 void	isa_defaultirq(void);
+void	isa_nodefaultirq(void);
 int	isa_nmi(void);
 
 /* pmap.c */
@@ -291,4 +452,12 @@ void	setconf(void);
 	{ "xcrypt", CTLTYPE_INT }, \
 }
 
+/*
+ * This needs to be included late since it relies on definitions higher
+ * up in this file.
+ */
+#if defined(MULTIPROCESSOR) && defined(_KERNEL)
+#include <sys/mplock.h>
+#endif
+
 #endif /* !_I386_CPU_H_ */
diff --git a/sys/arch/i386/include/cpufunc.h b/sys/arch/i386/include/cpufunc.h
index d90a120429b..832e4271142 100644
--- a/sys/arch/i386/include/cpufunc.h
+++ b/sys/arch/i386/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.11 2003/10/28 13:22:44 avsm Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.12 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.8 1994/10/27 04:15:59 cgd Exp $	*/
 
 /*
@@ -43,6 +43,8 @@
 #include <sys/cdefs.h>
 #include <sys/types.h>
 
+#include <machine/specialreg.h>
+
 static __inline void invlpg(u_int);
 static __inline void lidt(void *);
 static __inline void lldt(u_short);
@@ -55,6 +57,7 @@ static __inline u_int rcr3(void);
 static __inline void lcr4(u_int);
 static __inline u_int rcr4(void);
 static __inline void tlbflush(void);
+static __inline void tlbflushg(void);
 static __inline void disable_intr(void);
 static __inline void enable_intr(void);
 static __inline u_int read_eflags(void);
@@ -146,6 +149,39 @@ tlbflush(void)
 	__asm __volatile("movl %0,%%cr3" : : "r" (val));
 }
 
+static __inline void
+tlbflushg(void)
+{
+	/*
+	 * Big hammer: flush all TLB entries, including ones from PTE's
+	 * with the G bit set.  This should only be necessary if TLB
+	 * shootdown falls far behind.
+	 *
+	 * Intel Architecture Software Developer's Manual, Volume 3,
+	 *	System Programming, section 9.10, "Invalidating the
+	 * Translation Lookaside Buffers (TLBS)":
+	 * "The following operations invalidate all TLB entries, irrespective
+	 * of the setting of the G flag:
+	 * ...
+	 * "(P6 family processors only): Writing to control register CR4 to
+	 * modify the PSE, PGE, or PAE flag."
+	 *
+	 * (the alternatives not quoted above are not an option here.)
+	 *
+	 * If PGE is not in use, we reload CR3 for the benefit of
+	 * pre-P6-family processors.
+	 */
+
+#if defined(I686_CPU)
+	if (cpu_feature & CPUID_PGE) {
+		u_int cr4 = rcr4();
+		lcr4(cr4 & ~CR4_PGE);
+		lcr4(cr4);
+	} else
+#endif
+		tlbflush();
+}
+
 #ifdef notyet
 void	setidt(int idx, /*XXX*/caddr_t func, int typ, int dpl);
 #endif
diff --git a/sys/arch/i386/include/cpuvar.h b/sys/arch/i386/include/cpuvar.h
new file mode 100644
index 00000000000..5bf9f3342ae
--- /dev/null
+++ b/sys/arch/i386/include/cpuvar.h
@@ -0,0 +1,108 @@
+/*	$OpenBSD: cpuvar.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/* $NetBSD: cpuvar.h,v 1.1.2.3 2000/02/21 18:54:07 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1999 Stefan Grefen
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.  
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+struct cpu_functions {
+    int (*start)(struct cpu_info *);
+    int (*stop)(struct cpu_info *);
+    void (*cleanup)(struct cpu_info *);
+};
+
+extern struct cpu_functions mp_cpu_funcs;
+
+#define CPU_ROLE_SP	0
+#define CPU_ROLE_BP	1
+#define CPU_ROLE_AP	2
+
+struct cpu_attach_args {
+	const char *caa_name;
+	int cpu_number;
+	int cpu_role;
+	struct cpu_functions *cpu_func;
+	int cpu_signature;
+	int feature_flags;
+};
+
+#define MP_PICMODE	0x00000001      /* System booted in picmode */
+
+#ifdef _KERNEL
+
+int i386_ipi(int,int,int);
+void i386_self_ipi(int);
+int i386_ipi_init(int);
+
+void identifycpu(struct cpu_info *);
+void cpu_init(struct cpu_info *);
+void cpu_init_first(void);
+
+#endif
+
diff --git a/sys/arch/i386/include/db_machdep.h b/sys/arch/i386/include/db_machdep.h
index 69fb1d2cb30..c1f5b9b6dfe 100644
--- a/sys/arch/i386/include/db_machdep.h
+++ b/sys/arch/i386/include/db_machdep.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: db_machdep.h,v 1.9 2003/05/18 02:43:13 andreas Exp $	*/
+/*	$OpenBSD: db_machdep.h,v 1.10 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: db_machdep.h,v 1.9 1996/05/03 19:23:59 christos Exp $	*/
 
 /* 
@@ -120,5 +120,13 @@ void		db_task_name(/* task_t */);
 int kdb_trap(int, int, db_regs_t *);
 
 void db_machine_init(void);
+void db_enter_ddb(void);
+void db_leave_ddb(void);
+void db_startcpu(int cpu);
+void db_stopcpu(int cpu);
+void db_movetocpu(int cpu);
+void i386_ipi_db(struct cpu_info *);
+
+extern struct SIMPLELOCK ddb_mp_slock;
 
 #endif	/* _I386_DB_MACHDEP_H_ */
diff --git a/sys/arch/i386/include/gdt.h b/sys/arch/i386/include/gdt.h
index 1568b573a86..ba741e2c637 100644
--- a/sys/arch/i386/include/gdt.h
+++ b/sys/arch/i386/include/gdt.h
@@ -1,8 +1,8 @@
-/*	$OpenBSD: gdt.h,v 1.9 2002/03/14 01:26:33 millert Exp $	*/
-/*	$NetBSD: gdt.h,v 1.3 1996/02/27 22:32:11 jtc Exp $	*/
+/*	$OpenBSD: gdt.h,v 1.10 2004/06/13 21:49:16 niklas Exp $	*/
+/*	$NetBSD: gdt.h,v 1.7.10.6 2002/08/19 01:22:36 sommerfeld Exp $	*/
 
 /*-
- * Copyright (c) 1996 The NetBSD Foundation, Inc.
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
  * All rights reserved.
  *
  * This code is derived from software contributed to The NetBSD Foundation
@@ -37,10 +37,35 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifdef _KERNEL
+#ifndef _LOCORE
+
+struct cpu_info;
+struct pcb;
+struct pmap;
+union descriptor;
+
+void gdt_alloc_cpu(struct cpu_info *);
+int gdt_get_slot(void);
 void gdt_init(void);
-void tss_alloc(struct pcb *);
-void tss_free(struct pcb *);
+void gdt_init_cpu(struct cpu_info *);
+void gdt_reload_cpu(/* XXX struct cpu_info * */ void);
 void ldt_alloc(struct pmap *, union descriptor *, size_t);
 void ldt_free(struct pmap *);
+int tss_alloc(struct pcb *);
+void tss_free(int);
+void setgdt(int, void *, size_t, int, int, int, int);
 #endif
+
+/*
+ * The initial GDT size (as a descriptor count), and the maximum
+ * GDT size possible.
+ *
+ * These are actually not arbitrary.  To start with, they have to be
+ * multiples of 512 and at least 512, in order to work with the
+ * allocation strategy set forth by gdt_init and gdt_grow.  Then, the
+ * max cannot exceed 65536 since the selector field of a descriptor is
+ * just 16 bits, and used as free list link.
+ */
+
+#define MINGDTSIZ 512
+#define MAXGDTSIZ 8192
diff --git a/sys/arch/i386/include/i82093reg.h b/sys/arch/i386/include/i82093reg.h
new file mode 100644
index 00000000000..07ec03d8991
--- /dev/null
+++ b/sys/arch/i386/include/i82093reg.h
@@ -0,0 +1,124 @@
+/*	$OpenBSD: i82093reg.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/* $NetBSD: i82093reg.h,v 1.1.2.2 2000/02/21 18:54:07 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Typically, the first apic lives here.
+ */
+#define IOAPIC_BASE_DEFAULT	0xfec00000
+
+/*
+ * Memory-space registers.
+ */
+
+/*
+ * The externally visible registers are all 32 bits wide;
+ * store the register number of interest in IOAPIC_REG, and store/fetch
+ * the real value in IOAPIC_DATA.
+ */
+   
+
+
+#define	IOAPIC_REG		0x0000
+#define IOAPIC_DATA		0x0010
+
+/*
+ * Internal I/O APIC registers.
+ */
+
+#define IOAPIC_ID		0x00
+
+#define 	IOAPIC_ID_SHIFT		24
+#define		IOAPIC_ID_MASK		0x0f000000
+
+/* Version, and maximum interrupt pin number. */
+  
+#define IOAPIC_VER		0x01
+
+#define		IOAPIC_VER_SHIFT		0
+#define		IOAPIC_VER_MASK			0x000000ff
+
+#define		IOAPIC_MAX_SHIFT	       	16
+#define		IOAPIC_MAX_MASK	       	0x00ff0000
+
+/*
+ * Arbitration ID.  Same format as IOAPIC_ID register.
+ */
+#define IOAPIC_ARB		0x02
+
+/*
+ * Redirection table registers.
+ */
+
+#define IOAPIC_REDHI(pin)	(0x11 + ((pin)<<1))
+#define IOAPIC_REDLO(pin)	(0x10 + ((pin)<<1))
+
+#define IOAPIC_REDHI_DEST_SHIFT		24	   /* destination. */
+#define IOAPIC_REDHI_DEST_MASK		0xff000000
+
+#define IOAPIC_REDLO_MASK		0x00010000 /* 0=enabled; 1=masked */
+
+#define IOAPIC_REDLO_LEVEL		0x00008000 /* 0=edge, 1=level */
+#define IOAPIC_REDLO_RIRR		0x00004000 /* remote IRR; read only */
+#define IOAPIC_REDLO_ACTLO		0x00002000 /* 0=act. hi; 1=act. lo */
+#define IOAPIC_REDLO_DELSTS		0x00001000 /* 0=idle; 1=send pending */
+#define IOAPIC_REDLO_DSTMOD		0x00000800 /* 0=physical; 1=logical */
+
+#define IOAPIC_REDLO_DEL_MASK		0x00000700 /* del. mode mask */
+#define IOAPIC_REDLO_DEL_SHIFT		8
+
+#define IOAPIC_REDLO_DEL_FIXED		0
+#define IOAPIC_REDLO_DEL_LOPRI		1
+#define IOAPIC_REDLO_DEL_SMI		2
+#define IOAPIC_REDLO_DEL_NMI		4
+#define IOAPIC_REDLO_DEL_INIT		5
+#define IOAPIC_REDLO_DEL_EXTINT		7
+
+#define IOAPIC_REDLO_VECTOR_MASK	0x000000ff /* delivery vector */
+
+#define IMCR_ADDR		0x22
+#define IMCR_DATA		0x23
+
+#define IMCR_REGISTER		0x70
+#define		IMCR_PIC	0x00
+#define 	IMCR_APIC	0x01
+
+#define ioapic_asm_ack(num) \
+    movl	$0,_C_LABEL(local_apic) + LAPIC_EOI
diff --git a/sys/arch/i386/include/i82093var.h b/sys/arch/i386/include/i82093var.h
new file mode 100644
index 00000000000..c3d7ce586f3
--- /dev/null
+++ b/sys/arch/i386/include/i82093var.h
@@ -0,0 +1,103 @@
+/*	$OpenBSD: i82093var.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/* $NetBSD: i82093var.h,v 1.1 2003/02/26 21:26:10 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_I82093VAR_H_
+#define _I386_I82093VAR_H_
+
+#include <machine/apicvar.h>
+
+struct ioapic_pin 
+{
+	struct intrhand		*ip_handler; 
+	struct ioapic_pin	*ip_next; /* next pin on this vector */
+	struct mp_intr_map 	*ip_map;
+	int			ip_vector; /* IDT vector */
+	int			ip_type;
+	int			ip_minlevel;
+	int			ip_maxlevel;
+};
+
+struct ioapic_softc {
+	struct 			device sc_dev;	/* generic device glue */
+	struct ioapic_softc	*sc_next;
+	int			sc_apicid;
+	int			sc_apic_vers;
+	int			sc_apic_sz;	/* apic size*/
+	int			sc_flags;
+	paddr_t			sc_pa;		/* PA of ioapic */
+	volatile u_int32_t	*sc_reg;	/* KVA of ioapic addr */
+	volatile u_int32_t	*sc_data;	/* KVA of ioapic data */
+	struct ioapic_pin	*sc_pins;	/* sc_apic_sz entries */
+};      
+
+/*
+ * MP: intr_handle_t is bitfielded.
+ * ih&0xff -> line number.
+ * ih&0x10000000 -> if 0, old-style isa irq; if 1, routed via ioapic.
+ * (ih&0xff0000)>>16 -> ioapic id.
+ * (ih&0x00ff00)>>8 -> ioapic line.
+ */
+
+#define APIC_INT_VIA_APIC	0x10000000
+#define APIC_INT_APIC_MASK	0x00ff0000
+#define APIC_INT_APIC_SHIFT	16
+#define APIC_INT_PIN_MASK	0x0000ff00
+#define APIC_INT_PIN_SHIFT	8
+
+#define APIC_IRQ_APIC(x) ((x & APIC_INT_APIC_MASK) >> APIC_INT_APIC_SHIFT)
+#define APIC_IRQ_PIN(x) ((x & APIC_INT_PIN_MASK) >> APIC_INT_PIN_SHIFT)
+
+void   *apic_intr_establish(int, int, int, int (*)(void *), void *, char *); 
+void	apic_intr_disestablish(void *);
+
+void	ioapic_print_redir(struct ioapic_softc *, char *, int);
+void	ioapic_format_redir(char *, char *, int, u_int32_t, u_int32_t);
+struct ioapic_softc *ioapic_find(int);
+struct ioapic_softc *ioapic_find_bybase(int);
+
+void	ioapic_enable(void);
+void	lapic_vectorset(void); /* XXX */
+
+extern int ioapic_bsp_id;
+extern int nioapics;
+extern struct ioapic_softc *ioapics;
+
+#endif /* !_I386_I82093VAR_H_ */
diff --git a/sys/arch/i386/include/i82489reg.h b/sys/arch/i386/include/i82489reg.h
new file mode 100644
index 00000000000..9b850519370
--- /dev/null
+++ b/sys/arch/i386/include/i82489reg.h
@@ -0,0 +1,150 @@
+/*	$OpenBSD: i82489reg.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/*	$NetBSD: i82489reg.h,v 1.1.2.1 2000/02/20 16:30:27 sommerfeld Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+ * Registers and constants for the 82489DX and Pentium (and up) integrated
+ * "local" APIC.
+ */
+
+#define	LAPIC_ID		0x020		/* ID. RW */
+#	define LAPIC_ID_MASK		0x0f000000
+#	define LAPIC_ID_SHIFT		24
+
+#define LAPIC_VERS		0x030		/* Version. R */
+#	define LAPIC_VERSION_MASK	0x000000ff
+#	define LAPIC_VERSION_LVT_MASK	0x00ff0000
+#	define LAPIC_VERSION_LVT_SHIFT	16
+
+#define LAPIC_TPRI		0x080		/* Task Prio. RW */
+#	define LAPIC_TPRI_MASK		0x000000ff
+#	define LAPIC_TPRI_INT_MASK	0x000000f0
+#	define LAPIC_TPRI_SUB_MASK	0x0000000f
+
+#define LAPIC_APRI		0x090		/* Arbitration prio R */
+#	define LAPIC_APRI_MASK		0x000000ff
+
+#define LAPIC_PPRI		0x0a0		/* Processor prio. R */
+#define LAPIC_EOI		0x0b0		/* End Int. W */
+#define LAPIC_RRR		0x0c0		/* Remote read R */
+#define LAPIC_LDR		0x0d0		/* Logical dest. RW */
+#define LAPIC_DFR		0x0e0		/* Dest. format RW */
+
+#define LAPIC_SVR		0x0f0		/* Spurious intvec RW */
+#	define LAPIC_SVR_VECTOR_MASK	0x000000ff
+#	define LAPIC_SVR_VEC_FIX	0x0000000f
+#	define LAPIC_SVR_VEC_PROG	0x000000f0
+#	define LAPIC_SVR_ENABLE		0x00000100
+#	define LAPIC_SVR_SWEN		0x00000100
+#	define LAPIC_SVR_FOCUS		0x00000200
+#	define LAPIC_SVR_FDIS		0x00000200
+
+#define LAPIC_ISR	0x100			/* Int. status. R */
+#define LAPIC_TMR	0x180
+#define LAPIC_IRR	0x200
+#define LAPIC_ESR	0x280			/* Err status. R */
+
+#define LAPIC_ICRLO	0x300			/* Int. cmd. RW */
+#	define LAPIC_DLMODE_MASK	0x00000700
+#	define LAPIC_DLMODE_FIXED	0x00000000
+#	define LAPIC_DLMODE_LOW		0x00000100
+#	define LAPIC_DLMODE_SMI		0x00000200
+#	define LAPIC_DLMODE_RR		0x00000300
+#	define LAPIC_DLMODE_NMI		0x00000400
+#	define LAPIC_DLMODE_INIT	0x00000500
+#	define LAPIC_DLMODE_STARTUP	0x00000600
+
+#	define LAPIC_DSTMODE_LOG	0x00000800
+
+#	define LAPIC_DLSTAT_BUSY	0x00001000
+
+#	define LAPIC_LVL_ASSERT		0x00004000
+#	define LAPIC_LVL_DEASSERT	0x00000000
+
+#	define LAPIC_LVL_TRIG		0x00008000
+
+#	define LAPIC_RRSTAT_MASK	0x00030000
+#	define LAPIC_RRSTAT_INPROG	0x00010000
+#	define LAPIC_RRSTAT_VALID	0x00020000
+
+#	define LAPIC_DEST_MASK		0x000c0000
+#	define LAPIC_DEST_SELF		0x00040000
+#	define LAPIC_DEST_ALLINCL	0x00080000
+#	define LAPIC_DEST_ALLEXCL	0x000c0000
+
+#	define LAPIC_RESV2_MASK		0xfff00000
+
+
+#define LAPIC_ICRHI	0x310			/* Int. cmd. RW */
+#	define LAPIC_ID_MASK		0x0f000000
+#	define LAPIC_ID_SHIFT		24
+
+#define LAPIC_LVTT	0x320			/* Loc.vec.(timer) RW */
+#	define LAPIC_LVTT_VEC_MASK	0x000000ff
+#	define LAPIC_LVTT_DS		0x00001000
+#	define LAPIC_LVTT_M		0x00010000
+#	define LAPIC_LVTT_TM		0x00020000
+
+#define LAPIC_PCINT	0x340
+#define LAPIC_LVINT0	0x350			/* Loc.vec (LINT0) RW */
+#	define LAPIC_LVT_PERIODIC	0x00020000
+#	define LAPIC_LVT_MASKED		0x00010000
+#	define LAPIC_LVT_LEVTRIG	0x00008000
+#	define LAPIC_LVT_REMOTE_IRR	0x00004000
+#	define LAPIC_INP_POL		0x00002000
+#	define LAPIC_PEND_SEND		0x00001000
+
+#define LAPIC_LVINT1	0x360			/* Loc.vec (LINT1) RW */
+#define LAPIC_LVERR	0x370			/* Loc.vec (ERROR) RW */
+#define LAPIC_ICR_TIMER	0x380			/* Initial count RW */
+#define LAPIC_CCR_TIMER	0x390			/* Current count RO */
+
+#define LAPIC_DCR_TIMER	0x3e0			/* Divisor config register */
+#	define LAPIC_DCRT_DIV1		0x0b
+#	define LAPIC_DCRT_DIV2		0x00
+#	define LAPIC_DCRT_DIV4		0x01
+#	define LAPIC_DCRT_DIV8		0x02
+#	define LAPIC_DCRT_DIV16		0x03
+#	define LAPIC_DCRT_DIV32		0x08
+#	define LAPIC_DCRT_DIV64		0x09
+#	define LAPIC_DCRT_DIV128	0x0a
+
+#define LAPIC_BASE		0xfee00000
+
+#define LAPIC_IRQ_MASK(i)	(1 << ((i) + 1))
diff --git a/sys/arch/i386/include/i82489var.h b/sys/arch/i386/include/i82489var.h
new file mode 100644
index 00000000000..3c4632872ce
--- /dev/null
+++ b/sys/arch/i386/include/i82489var.h
@@ -0,0 +1,113 @@
+/*	$OpenBSD: i82489var.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/*	$NetBSD: i82489var.h,v 1.1.2.2 2000/02/21 18:46:14 sommerfeld Exp $	*/
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Frank van der Linden.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_I82489VAR_H_
+#define _I386_I82489VAR_H_
+
+static __inline__ u_int32_t i82489_readreg(int);
+static __inline__ void i82489_writereg(int, u_int32_t);
+
+#ifdef _KERNEL
+extern volatile u_int32_t local_apic[];
+#endif
+
+static __inline__ u_int32_t
+i82489_readreg(reg)
+	int reg;
+{
+	return *((volatile u_int32_t *)(((volatile u_int8_t *)local_apic)
+	    + reg));
+}
+
+static __inline__ void
+i82489_writereg(reg, val)
+	int reg;
+	u_int32_t val;
+{
+	*((volatile u_int32_t *)(((volatile u_int8_t *)local_apic) + reg)) =
+	    val;
+}
+
+/*
+ * "spurious interrupt vector"; vector used by interrupt which was
+ * aborted because the CPU masked it after it happened but before it
+ * was delivered.. "Oh, sorry, i caught you at a bad time".
+ * Low-order 4 bits must be all ones.
+ */
+extern void i386_spurious(void);
+extern void Xintrspurious(void);
+#define LAPIC_SPURIOUS_VECTOR		0xef
+
+/*
+ * Vector used for inter-processor interrupts.
+ */
+extern void Xintripi(void);
+#define LAPIC_IPI_VECTOR		IPL_IPI
+
+/*
+ * Vector used for local apic timer interrupts.
+ */
+
+extern void Xintrltimer(void);
+#define LAPIC_TIMER_VECTOR		IPL_CLOCK
+
+/*
+ * Vectors to be used for self-soft-interrupts.
+ */
+
+#define LAPIC_SOFTCLOCK_VECTOR		IPL_SOFTCLOCK
+#define LAPIC_SOFTNET_VECTOR		IPL_SOFTNET
+#define LAPIC_SOFTTTY_VECTOR		IPL_SOFTTTY
+
+extern void Xintrsoftclock(void);
+extern void Xintrsoftnet(void);
+extern void Xintrsofttty(void);
+
+extern void (*apichandler[])(void);
+
+struct cpu_info;
+
+extern void lapic_boot_init(paddr_t);
+extern void lapic_initclocks(void);
+extern void lapic_set_lvt(void);
+extern void lapic_set_softvectors(void);
+extern void lapic_enable(void);
+extern void lapic_calibrate_timer(struct cpu_info *);
+
+#endif
diff --git a/sys/arch/i386/include/i8259.h b/sys/arch/i386/include/i8259.h
new file mode 100644
index 00000000000..f1c4462e4d0
--- /dev/null
+++ b/sys/arch/i386/include/i8259.h
@@ -0,0 +1,154 @@
+/*	$OpenBSD: i8259.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/*	$NetBSD: i8259.h,v 1.3 2003/05/04 22:01:56 fvdl Exp $	*/
+
+/*-
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)icu.h	5.6 (Berkeley) 5/9/91
+ */
+
+#ifndef	_I386_I8259_H_
+#define	_I386_I8259_H_
+
+#include <dev/isa/isareg.h>
+
+#ifndef	_LOCORE
+
+/*
+ * Interrupt "level" mechanism variables, masks, and macros
+ */
+extern	unsigned imen;		/* interrupt mask enable */
+extern unsigned i8259_setmask(unsigned);
+
+#define SET_ICUS()	(outb(IO_ICU1 + 1, imen), outb(IO_ICU2 + 1, imen >> 8))
+
+extern void i8259_default_setup(void);
+extern void i8259_reinit(void);
+
+#endif /* !_LOCORE */
+
+/*
+ * Interrupt enable bits -- in order of priority
+ */
+#define	IRQ_SLAVE	2
+
+/*
+ * Interrupt Control offset into Interrupt descriptor table (IDT)
+ */
+#define	ICU_OFFSET	32		/* 0-31 are processor exceptions */
+#define	ICU_LEN		16		/* 32-47 are ISA interrupts */
+
+
+#define ICU_HARDWARE_MASK
+
+/*
+ * These macros are fairly self explanatory.  If ICU_SPECIAL_MASK_MODE is
+ * defined, we try to take advantage of the ICU's `special mask mode' by only
+ * EOIing the interrupts on return.  This avoids the requirement of masking and
+ * unmasking.  We can't do this without special mask mode, because the ICU
+ * would also hold interrupts that it thinks are of lower priority.
+ *
+ * Many machines do not support special mask mode, so by default we don't try
+ * to use it.
+ */
+
+#define	IRQ_BIT(num)	(1 << ((num) % 8))
+#define	IRQ_BYTE(num)	((num) >> 3)
+
+#define i8259_late_ack(num)
+
+#ifdef ICU_SPECIAL_MASK_MODE
+
+#define	i8259_asm_ack1(num)
+#define	i8259_asm_ack2(num) \
+	movb	$(0x60|IRQ_SLAVE),%al	/* specific EOI for IRQ2 */	;\
+	outb	%al,$IO_ICU1
+#define	i8259_asm_mask(num)
+#define	i8259_asm_unmask(num) \
+	movb	$(0x60|(num%8)),%al	/* specific EOI */		;\
+	outb	%al,$ICUADDR
+
+#else /* ICU_SPECIAL_MASK_MODE */
+
+#ifndef	AUTO_EOI_1
+#define	i8259_asm_ack1(num) \
+	movb	$(0x60|(num%8)),%al	/* specific EOI */		;\
+	outb	%al,$IO_ICU1
+#else
+#define	i8259_asm_ack1(num)
+#endif
+
+#ifndef AUTO_EOI_2
+#define	i8259_asm_ack2(num) \
+	movb	$(0x60|(num%8)),%al	/* specific EOI */		;\
+	outb	%al,$IO_ICU2		/* do the second ICU first */	;\
+	movb	$(0x60|IRQ_SLAVE),%al	/* specific EOI for IRQ2 */	;\
+	outb	%al,$IO_ICU1
+#else
+#define	i8259_asm_ack2(num)
+#endif
+
+#ifndef DUMMY_NOPS
+#define PIC_MASKDELAY
+#endif
+
+#ifdef PIC_MASKDELAY
+#define MASKDELAY	pushl %eax ; inb $0x84,%al ; popl %eax
+#else
+#define MASKDELAY
+#endif
+
+#ifdef ICU_HARDWARE_MASK
+
+#define	i8259_asm_mask(num) \
+	movb	CVAROFF(imen, IRQ_BYTE(num)),%al			;\
+	orb	$IRQ_BIT(num),%al					;\
+	movb	%al,CVAROFF(imen, IRQ_BYTE(num))			;\
+	MASKDELAY							;\
+	outb	%al,$(ICUADDR+1)
+#define	i8259_asm_unmask(num) \
+	cli								;\
+	movb	CVAROFF(imen, IRQ_BYTE(num)),%al			;\
+	andb	$~IRQ_BIT(num),%al					;\
+	movb	%al,CVAROFF(imen, IRQ_BYTE(num))			;\
+	MASKDELAY							;\
+	outb	%al,$(ICUADDR+1)					;\
+	sti
+
+#else /* ICU_HARDWARE_MASK */
+
+#define	i8259_asm_mask(num)
+#define	i8259_asm_unmask(num)
+
+#endif /* ICU_HARDWARE_MASK */
+#endif /* ICU_SPECIAL_MASK_MODE */
+
+#endif /* !_X86_I8259_H_ */
diff --git a/sys/arch/i386/include/intr.h b/sys/arch/i386/include/intr.h
index 00ba2cea665..9d7a7816cf0 100644
--- a/sys/arch/i386/include/intr.h
+++ b/sys/arch/i386/include/intr.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intr.h,v 1.20 2004/05/23 00:06:01 tedu Exp $	*/
+/*	$OpenBSD: intr.h,v 1.21 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: intr.h,v 1.5 1996/05/13 06:11:28 mycroft Exp $	*/
 
 /*
@@ -33,85 +33,31 @@
 #ifndef _I386_INTR_H_
 #define _I386_INTR_H_
 
-/*
- * Intel APICs (advanced programmable interrupt controllers) have
- * bytesized priority registers where the upper nibble is the actual
- * interrupt priority level (a.k.a. IPL).  Interrupt vectors are
- * closely tied to these levels as interrupts whose vectors' upper
- * nibble is lower than or equal to the current level are blocked.
- * Not all 256 possible vectors are available for interrupts in
- * APIC systems, only
- *
- * For systems where instead the older ICU (interrupt controlling
- * unit, a.k.a. PIC or 82C59) is used, the IPL is not directly useful,
- * since the interrupt blocking is handled via interrupt masks instead
- * of levels.  However the IPL is easily used as an offset into arrays
- * of masks.
- */
-#define IPLSHIFT 4	/* The upper nibble of vectors is the IPL.	*/
-#define NIPL 16		/* Four bits of information gives as much.	*/
-#define IPL(level) ((level) >> IPLSHIFT)	/* Extract the IPL.	*/
-/* XXX Maybe this IDTVECOFF definition should be elsewhere? */
-#define IDTVECOFF 0x20	/* The lower 32 IDT vectors are reserved.	*/
+#include <machine/intrdefs.h>
 
-/*
- * This macro is only defined for 0 <= x < 14, i.e. there are fourteen
- * distinct priority levels available for interrupts.
- */
-#define MAKEIPL(priority) (IDTVECOFF + ((priority) << IPLSHIFT))
+#ifndef _LOCORE
 
-/*
- * Interrupt priority levels.
- * XXX We are somewhat sloppy about what we mean by IPLs, sometimes
- * XXX we refer to the eight-bit value suitable for storing into APICs'
- * XXX priority registers, other times about the four-bit entity found
- * XXX in the former values' upper nibble, which can be used as offsets
- * XXX in various arrays of our implementation.  We are hoping that
- * XXX the context will provide enough information to not make this
- * XXX sloppy naming a real problem.
- */
-#define	IPL_NONE	0		/* nothing */
-#define	IPL_SOFTCLOCK	MAKEIPL(0)	/* timeouts */
-#define	IPL_SOFTNET	MAKEIPL(1)	/* protocol stacks */
-#define	IPL_BIO		MAKEIPL(2)	/* block I/O */
-#define	IPL_NET		MAKEIPL(3)	/* network */
-#define	IPL_SOFTTTY	MAKEIPL(4)	/* delayed terminal handling */
-#define	IPL_TTY		MAKEIPL(5)	/* terminal */
-#define	IPL_VM		MAKEIPL(6)	/* memory allocation */
-#define IPL_IMP		IPL_VM		/* XXX - should not be here. */
-#define	IPL_AUDIO	MAKEIPL(7)	/* audio */
-#define	IPL_CLOCK	MAKEIPL(8)	/* clock */
-#define	IPL_STATCLOCK	MAKEIPL(9)	/* statclock */
-#define	IPL_HIGH	MAKEIPL(9)	/* everything */
-
-/* Interrupt sharing types. */
-#define	IST_NONE	0	/* none */
-#define	IST_PULSE	1	/* pulsed */
-#define	IST_EDGE	2	/* edge-triggered */
-#define	IST_LEVEL	3	/* level-triggered */
-
-/* Soft interrupt masks. */
-#define	SIR_CLOCK	31
-#define	SIR_NET		30
-#define	SIR_TTY		29
+#ifdef MULTIPROCESSOR
+#include <machine/i82489reg.h>
+#include <machine/i82489var.h>
+#include <machine/cpu.h>
+#endif
 
-#ifndef _LOCORE
+extern volatile u_int32_t lapic_tpr;	/* Current interrupt priority level. */
 
-volatile int cpl;	/* Current interrupt priority level.		*/
-volatile int ipending;	/* Interrupts pending.				*/
-volatile int astpending;/* Asynchronous software traps (softints) pending. */
-int imask[NIPL];	/* Bitmasks telling what interrupts are blocked. */
-int iunmask[NIPL];	/* Bitmasks telling what interrupts are accepted. */
+extern volatile u_int32_t ipending;	/* Interrupts pending. */
+extern int imask[];	/* Bitmasks telling what interrupts are blocked. */
+extern int iunmask[];	/* Bitmasks telling what interrupts are accepted. */
 
 #define IMASK(level) imask[IPL(level)]
 #define IUNMASK(level) iunmask[IPL(level)]
 
 extern void Xspllower(void);
 
-int splraise(int);
-int spllower(int);
-void splx(int);
-void softintr(int);
+extern int splraise(int);
+extern int spllower(int);
+extern void splx(int);
+extern void softintr(int, int);
 
 /* SPL asserts */
 #ifdef DIAGNOSTIC
@@ -140,6 +86,7 @@ void splassert_check(int, const char *);
 #define	splaudio()	splraise(IPL_AUDIO)
 #define	splclock()	splraise(IPL_CLOCK)
 #define	splstatclock()	splhigh()
+#define splipi()	splraise(IPL_IPI)
 
 /*
  * Software interrupt masks
@@ -158,12 +105,40 @@ void splassert_check(int, const char *);
 #define	splvm()		splraise(IPL_VM)
 #define splimp()	splvm()
 #define	splhigh()	splraise(IPL_HIGH)
+#define	splsched()	splraise(IPL_SCHED)
+#define spllock() 	splhigh()
 #define	spl0()		spllower(IPL_NONE)
 
 #define	setsoftast()	(astpending = 1)
-#define	setsoftclock()	softintr(1 << SIR_CLOCK)
-#define	setsoftnet()	softintr(1 << SIR_NET)
-#define	setsofttty()	softintr(1 << SIR_TTY)
+#define	setsoftclock()	softintr(1 << SIR_CLOCK, IPL_SOFTCLOCK)
+#define	setsoftnet()	softintr(1 << SIR_NET, IPL_SOFTNET)
+#define	setsofttty()	softintr(1 << SIR_TTY, IPL_SOFTTTY)
+
+#define I386_IPI_HALT		0x00000001
+#define I386_IPI_MICROSET	0x00000002
+#define I386_IPI_FLUSH_FPU	0x00000004
+#define I386_IPI_SYNCH_FPU	0x00000008
+#define I386_IPI_TLB		0x00000010
+#define I386_IPI_MTRR		0x00000020
+#define I386_IPI_GDT		0x00000040
+#define I386_IPI_DDB		0x00000080	/* synchronize while in ddb */
+
+#define I386_NIPI	8
+
+struct cpu_info;
+
+#ifdef MULTIPROCESSOR
+int i386_send_ipi(struct cpu_info *, int);
+void i386_broadcast_ipi(int);
+void i386_multicast_ipi(int, int);
+void i386_ipi_handler(void);
+void i386_intlock(struct intrframe);
+void i386_intunlock(struct intrframe);
+void i386_softintlock(void);
+void i386_softintunlock(void);
+
+extern void (*ipifunc[I386_NIPI])(struct cpu_info *);
+#endif
 
 #endif /* !_LOCORE */
 
diff --git a/sys/arch/i386/include/intrdefs.h b/sys/arch/i386/include/intrdefs.h
new file mode 100644
index 00000000000..c2c998b76b3
--- /dev/null
+++ b/sys/arch/i386/include/intrdefs.h
@@ -0,0 +1,127 @@
+/*	$OpenBSD: intrdefs.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/*	$NetBSD: intrdefs.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $	*/
+
+#ifndef _i386_INTRDEFS_H
+#define _i386_INTRDEFS_H
+
+/*
+ * Intel APICs (advanced programmable interrupt controllers) have
+ * bytesized priority registers where the upper nibble is the actual
+ * interrupt priority level (a.k.a. IPL).  Interrupt vectors are
+ * closely tied to these levels as interrupts whose vectors' upper
+ * nibble is lower than or equal to the current level are blocked.
+ * Not all 256 possible vectors are available for interrupts in
+ * APIC systems, only
+ *
+ * For systems where instead the older ICU (interrupt controlling
+ * unit, a.k.a. PIC or 82C59) is used, the IPL is not directly useful,
+ * since the interrupt blocking is handled via interrupt masks instead
+ * of levels.  However the IPL is easily used as an offset into arrays
+ * of masks.
+ */
+#define IPLSHIFT 4	/* The upper nibble of vectors is the IPL.	*/
+#define NIPL 16		/* Four bits of information gives as much.	*/
+#define IPL(level) ((level) >> IPLSHIFT)	/* Extract the IPL.	*/
+/* XXX Maybe this IDTVECOFF definition should be elsewhere? */
+#define IDTVECOFF 0x20	/* The lower 32 IDT vectors are reserved.	*/
+
+/*
+ * This macro is only defined for 0 <= x < 14, i.e. there are fourteen
+ * distinct priority levels available for interrupts.
+ */
+#define MAKEIPL(priority) (IDTVECOFF + ((priority) << IPLSHIFT))
+
+/*
+ * Interrupt priority levels.
+ *
+ * XXX We are somewhat sloppy about what we mean by IPLs, sometimes
+ * XXX we refer to the eight-bit value suitable for storing into APICs'
+ * XXX priority registers, other times about the four-bit entity found
+ * XXX in the former values' upper nibble, which can be used as offsets
+ * XXX in various arrays of our implementation.  We are hoping that
+ * XXX the context will provide enough information to not make this
+ * XXX sloppy naming a real problem.
+ * 
+ * There are tty, network and disk drivers that use free() at interrupt
+ * time, so imp > (tty | net | bio).
+ *
+ * Since run queues may be manipulated by both the statclock and tty,
+ * network, and disk drivers, clock > imp.
+ *
+ * IPL_HIGH must block everything that can manipulate a run queue.
+ *
+ * XXX Ultimately we may need serial drivers to run at the absolute highest
+ * XXX priority to avoid overruns, then we must make serial > high.
+ *
+ * The level numbers are picked to fit into APIC vector priorities.
+ */
+#define	IPL_NONE	0		/* nothing */
+#define	IPL_SOFTCLOCK	MAKEIPL(0)	/* timeouts */
+#define	IPL_SOFTNET	MAKEIPL(1)	/* protocol stacks */
+#define	IPL_BIO		MAKEIPL(2)	/* block I/O */
+#define	IPL_NET		MAKEIPL(3)	/* network */
+#define	IPL_SOFTTTY	MAKEIPL(4)	/* delayed terminal handling */
+#define	IPL_TTY		MAKEIPL(5)	/* terminal */
+#define	IPL_VM		MAKEIPL(6)	/* memory allocation */
+#define IPL_IMP		IPL_VM		/* XXX - should not be here. */
+#define	IPL_AUDIO	MAKEIPL(7)	/* audio */
+#define	IPL_CLOCK	MAKEIPL(8)	/* clock */
+#define	IPL_SCHED	IPL_CLOCK
+#define	IPL_STATCLOCK	MAKEIPL(9)	/* statclock */
+#define	IPL_HIGH	MAKEIPL(9)	/* everything */
+#define	IPL_IPI		MAKEIPL(10)	/* interprocessor interrupt */
+
+/* Interrupt sharing types. */
+#define	IST_NONE	0	/* none */
+#define	IST_PULSE	1	/* pulsed */
+#define	IST_EDGE	2	/* edge-triggered */
+#define	IST_LEVEL	3	/* level-triggered */
+
+/*
+ * Local APIC masks. Must not conflict with SIR_* below, and must
+ * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first.
+ */
+#define LIR_IPI		31
+#define LIR_TIMER	30
+
+/* Soft interrupt masks. */
+#define	SIR_CLOCK	29
+#define	SIR_NET		28
+#define	SIR_TTY		27
+
+
+/*
+ * Maximum # of interrupt sources per CPU. 32 to fit in one word.
+ * ioapics can theoretically produce more, but it's not likely to
+ * happen. For multiple ioapics, things can be routed to different
+ * CPUs.
+ */
+#define MAX_INTR_SOURCES	32
+#define NUM_LEGACY_IRQS		16
+
+/*
+ * Low and high boundaries between which interrupt gates will
+ * be allocated in the IDT.
+ */
+#define IDT_INTR_LOW	(0x20 + NUM_LEGACY_IRQS)
+#define IDT_INTR_HIGH	0xef
+
+#define I386_IPI_HALT		0x00000001
+#define I386_IPI_MICROSET	0x00000002
+#define I386_IPI_FLUSH_FPU	0x00000004
+#define I386_IPI_SYNCH_FPU	0x00000008
+#define I386_IPI_TLB		0x00000010
+#define I386_IPI_MTRR		0x00000020
+#define I386_IPI_GDT		0x00000040
+#define I386_IPI_DDB		0x00000080	/* synchronize while in ddb */
+
+#define I386_NIPI	8
+
+#define I386_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
+			 "FPU synch IPI", "TLB shootdown IPI", \
+			 "MTRR update IPI", "GDT update IPI", \
+			 "DDB IPI" }
+
+#define IREENT_MAGIC	0x18041969
+
+#endif /* _I386_INTRDEFS_H */
diff --git a/sys/arch/i386/include/lock.h b/sys/arch/i386/include/lock.h
new file mode 100644
index 00000000000..a647999a532
--- /dev/null
+++ b/sys/arch/i386/include/lock.h
@@ -0,0 +1,119 @@
+/*	$OpenBSD: lock.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/*	$NetBSD: lock.h,v 1.1.2.2 2000/05/03 14:40:55 sommerfeld Exp $	*/
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Machine-dependent spin lock operations.
+ */
+
+#ifndef _I386_LOCK_H_
+#define	_I386_LOCK_H_
+
+typedef	__volatile int		__cpu_simple_lock_t;
+
+#define	__SIMPLELOCK_LOCKED	1
+#define	__SIMPLELOCK_UNLOCKED	0
+
+/*
+ * compiler barrier: prevent reordering of instructions.
+ * XXX something similar will move to <sys/cdefs.h>
+ * or thereabouts.
+ * This prevents the compiler from reordering code around
+ * this "instruction", acting as a sequence point for code generation.
+ */
+
+#define __lockbarrier() __asm __volatile("": : :"memory")
+
+#ifdef LOCKDEBUG
+
+extern void __cpu_simple_lock_init(__cpu_simple_lock_t *);
+extern void __cpu_simple_lock(__cpu_simple_lock_t *);
+extern int __cpu_simple_lock_try(__cpu_simple_lock_t *);
+extern void __cpu_simple_unlock(__cpu_simple_lock_t *);
+
+#else
+
+#include <machine/atomic.h>
+
+static __inline void __cpu_simple_lock_init(__cpu_simple_lock_t *)
+	__attribute__((__unused__));
+static __inline void __cpu_simple_lock(__cpu_simple_lock_t *)
+	__attribute__((__unused__));
+static __inline int __cpu_simple_lock_try(__cpu_simple_lock_t *)
+	__attribute__((__unused__));
+static __inline void __cpu_simple_unlock(__cpu_simple_lock_t *)
+	__attribute__((__unused__));
+
+static __inline void
+__cpu_simple_lock_init(__cpu_simple_lock_t *lockp)
+{
+	*lockp = __SIMPLELOCK_UNLOCKED;
+	__lockbarrier();
+}
+
+static __inline void
+__cpu_simple_lock(__cpu_simple_lock_t *lockp)
+{
+	while (i386_atomic_testset_i(lockp, __SIMPLELOCK_LOCKED)
+	    == __SIMPLELOCK_LOCKED) {
+		continue;	/* spin */
+	}
+	__lockbarrier();
+}
+
+static __inline int
+__cpu_simple_lock_try(__cpu_simple_lock_t *lockp)
+{
+	int r = (i386_atomic_testset_i(lockp, __SIMPLELOCK_LOCKED)
+	    == __SIMPLELOCK_UNLOCKED);
+
+	__lockbarrier();
+
+	return (r);
+}
+
+static __inline void
+__cpu_simple_unlock(__cpu_simple_lock_t *lockp)
+{
+	__lockbarrier();
+	*lockp = __SIMPLELOCK_UNLOCKED;
+}
+
+#endif /* !LOCKDEBUG */
+
+#endif /* _I386_LOCK_H_ */
diff --git a/sys/arch/i386/include/mp.h b/sys/arch/i386/include/mp.h
new file mode 100644
index 00000000000..d12e8a54aca
--- /dev/null
+++ b/sys/arch/i386/include/mp.h
@@ -0,0 +1,222 @@
+/*	$OpenBSD: mp.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+
+/*-
+ * Copyright (c) 1996 SigmaSoft, Th. Lockert <tholo@sigmasoft.com>
+ * Copyright (c) 2000 Niklas Hallqvist.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by SigmaSoft, Th.  Lockert.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MACHINE_MP_H
+#define _MACHINE_MP_H
+
+/*
+ * Configuration structures as defined in the Intel MP specification,
+ * version 1.4
+ */
+
+/*
+ * MP Floating Pointer structure; must be located on 16-byte boundary
+ */
+struct mp_float {
+	u_int8_t	signature[4];
+#define	MPF_SIGNATURE	"_MP_"
+	u_int32_t	pointer;
+	u_int8_t	length;
+	u_int8_t	revision;
+	u_int8_t	checksum;
+	u_int8_t	feature1;
+#define	MP_CONF_EXTENDED	0
+#define	MP_CONF_2_ISA		1
+#define	MP_CONF_2_EISA_NO_8	2
+#define	MP_CONF_2_EISA		3
+#define	MP_CONF_2_MCA		4
+#define	MP_CONF_2_ISA_PCI	5
+#define	MP_CONF_2_EISA_PCI	6
+#define	MP_CONF_2_MCA_PCI	7
+	u_int8_t	feature2;
+#define	MP_IMCR		0x80
+	u_int8_t	feature3;
+	u_int8_t	feature4;
+	u_int8_t	feature5;
+};
+
+/*
+ * MP configuration table header
+ */
+struct mp_conf {
+	u_int8_t	signature[4];
+#define	MPC_SIGNATURE	"PCMP"
+	u_int16_t	length;
+	u_int8_t	revision;
+	u_int8_t	checksum;
+	u_int8_t	oem[8];
+	u_int8_t	product[12];
+	u_int32_t	oem_pointer;
+	u_int16_t	oem_length;
+	u_int16_t	entry_count;
+	u_int32_t	local_apic;
+	u_int16_t	ext_length;
+	u_int8_t	et_checksum;
+	u_int8_t	reserved;
+};
+
+/*
+ * Processor entry
+ */
+struct mp_proc {
+	u_int8_t	type;
+#define	MP_PROCESSOR	0
+	u_int8_t	local_apic;
+	u_int8_t	apic_version;
+	u_int8_t	flags;
+#define	MP_ENABLE	0x01
+#define	MP_BOOTCPU	0x02
+	u_int32_t	cpu_signature;
+#define	MP_STEPPING	0x0000000F
+#define	MP_MODEL	0x000000F0
+#define	MP_FAMILY	0x00000F00
+	u_int32_t	feature_flags;
+#define	MP_FP		0x00000001
+#define	MP_MCE		0x00000080
+#define	MP_CX8		0x00000100
+#define	MP_APIC		0x00000200
+	u_int32_t	reserved1;
+	u_int32_t	reserved2;
+};
+
+/*
+ * Bus entry
+ */
+struct mp_bus {
+	u_int8_t	type;
+#define	MP_BUS		1
+	u_int8_t	bus_id;
+	u_int8_t	bustype[6]	__attribute((packed));
+#define	MP_BUS_CBUS	"CBUS  "
+#define	MP_BUS_CBUSII	"CBUSII"
+#define	MP_BUS_EISA	"EISA  "
+#define	MP_BUS_FUTURE	"FUTURE"
+#define	MP_BUS_INTERN	"INTERN"
+#define	MP_BUS_ISA	"ISA   "
+#define	MP_BUS_MBI	"MBI   "
+#define	MP_BUS_MBII	"MBII  "
+#define	MP_BUS_MCA	"MCA   "
+#define	MP_BUS_MPI	"MPI   "
+#define	MP_BUS_MPSA	"MPSA  "
+#define	MP_BUS_NUBUS	"NUBUS "
+#define	MP_BUS_PCI	"PCI   "
+#define	MP_BUS_PCCARD	"PCMCIA"
+#define	MP_BUS_TC	"TC    "
+#define	MP_BUS_VLB	"VL    "
+#define	MP_BUS_VME	"VME   "
+#define	MP_BUS_XPRESS	"XPRESS"
+};
+
+/*
+ * I/O APIC entry
+ */
+struct mp_apic {
+	u_int8_t	type;
+#define	MP_IOAPIC	2
+	u_int8_t	apic_id;
+	u_int8_t	apic_version;
+	u_int8_t	apic_flags;
+#define	MP_APIC_ENABLE	0x80
+	u_int32_t	apic_address;
+};
+
+/*
+ * I/O Interrupt Assignment entry
+ * Local Interrupt Assignment entry
+ */
+struct mp_irq {
+	u_int8_t	type;
+#define	MP_INTSRC	3
+#define	MP_LOCINTSRC	4
+	u_int8_t	irqtype;
+#define	MP_INT_NORMAL	0
+#define	MP_INT_NMI	1
+#define	MP_INT_SMI	2
+#define	MP_INT_EXT	3
+	u_int16_t	irqflags;
+	u_int8_t	bus_id;
+	u_int8_t	source_irq;
+	u_int8_t	destination_apic;
+#define	MP_ALL_APIC	0xFF
+	u_int8_t	apic_intr;
+};
+
+/*
+ * System Address Space Mapping entry
+ */
+struct mp_map {
+	u_int8_t	type;
+#define	MP_SYSMAP	128
+	u_int8_t	length;
+	u_int8_t	bus;
+	u_int8_t	address_type;
+#define	MP_ADDR_IO	0
+#define	MP_ADDR_MEM	1
+#define	MP_ADDR_PRE	2
+	u_int64_t	address_base;
+	u_int64_t	address_length;
+};
+
+/*
+ * Bus Hierarchy Descriptor entry
+ */
+struct mp_bushier {
+	u_int8_t	type;
+#define	MP_BUSHIER	129
+	u_int8_t	length;
+	u_int8_t	bus_id;
+	u_int8_t	bus_info;
+#define	MP_BUS_SUB	0x01
+	u_int8_t	parent;
+	u_int8_t	reserved1;
+	u_int16_t	reserved2;
+};
+
+/*
+ * Compatibility Bus Address Space Modifier entry
+ */
+struct mp_buscompat {
+	u_int8_t	type;
+#define	MP_BUSCOMPAT	130
+	u_int8_t	length;
+	u_int8_t	bus_id;
+	u_int8_t	modifier;
+#define	MP_COMPAT_SUB	0x01
+	u_int32_t	range;
+};
+
+#ifdef _KERNEL
+extern int napics;
+#endif /* _KERNEL */
+
+#endif /* _MACHINE_MP_H */
diff --git a/sys/arch/i386/include/mpbiosreg.h b/sys/arch/i386/include/mpbiosreg.h
new file mode 100644
index 00000000000..d42aed04cdc
--- /dev/null
+++ b/sys/arch/i386/include/mpbiosreg.h
@@ -0,0 +1,155 @@
+/*	$OpenBSD: mpbiosreg.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/* $NetBSD: mpbiosreg.h,v 1.1.2.3 2000/02/29 13:17:51 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_MPBIOSREG_H_
+#define _I386_MPBIOSREG_H_
+
+#define BIOS_BASE		(0xf0000)
+#define BIOS_SIZE		(0x10000)
+#define BIOS_COUNT		(BIOS_SIZE)
+
+/*
+ * Multiprocessor config table entry types.
+ */
+
+#define MPS_MCT_CPU	0
+#define MPS_MCT_BUS	1
+#define MPS_MCT_IOAPIC	2
+#define MPS_MCT_IOINT	3
+#define MPS_MCT_LINT	4
+
+#define MPS_MCT_NTYPES	5
+
+/*
+ * Interrupt typess
+ */
+
+#define MPS_INTTYPE_INT		0
+#define MPS_INTTYPE_NMI		1
+#define MPS_INTTYPE_SMI		2
+#define MPS_INTTYPE_ExtINT	3
+
+#define MPS_INTPO_DEF		0
+#define MPS_INTPO_ACTHI		1
+#define MPS_INTPO_ACTLO		3
+
+#define MPS_INTTR_DEF		0
+#define MPS_INTTR_EDGE		1
+#define MPS_INTTR_LEVEL		3
+
+
+/* MP Floating Pointer Structure */
+struct mpbios_fps {
+	u_int32_t	signature;
+/* string defined by the Intel MP Spec as identifying the MP table */
+#define MP_FP_SIG		0x5f504d5f	/* _MP_ */
+	
+	u_int32_t 	pap;
+	u_int8_t  	length;
+	u_int8_t  	spec_rev;
+	u_int8_t  	checksum;
+	u_int8_t  	mpfb1;	/* system configuration */
+	u_int8_t  	mpfb2;	/* flags */
+#define MPFPS_FLAG_IMCR		0x80	/* IMCR present */
+	u_int8_t  	mpfb3;	/* unused */
+	u_int8_t  	mpfb4;	/* unused */
+	u_int8_t  	mpfb5;	/* unused */
+};
+
+/* MP Configuration Table Header */
+struct mpbios_cth {
+	u_int32_t	signature;
+#define MP_CT_SIG		0x504d4350 	/* PCMP */
+	
+	u_int16_t 	base_len;
+	u_int8_t  	spec_rev;
+	u_int8_t  	checksum;
+	u_int8_t  	oem_id[8];
+	u_int8_t  	product_id[12];
+	u_int32_t	oem_table_pointer;
+	u_int16_t 	oem_table_size;
+	u_int16_t 	entry_count;
+	u_int32_t	apic_address;
+	u_int16_t	ext_len;
+	u_int8_t  	ext_cksum;
+	u_int8_t  	reserved;
+};
+
+struct mpbios_proc {
+	u_int8_t  type;
+	u_int8_t  apic_id;
+	u_int8_t  apic_version;
+	u_int8_t  cpu_flags;
+#define PROCENTRY_FLAG_EN	0x01
+#define PROCENTRY_FLAG_BP	0x02
+	u_long  cpu_signature;
+	u_long  feature_flags;
+	u_long  reserved1;
+	u_long  reserved2;
+};
+
+struct mpbios_bus {
+	u_int8_t  type;
+	u_int8_t  bus_id;
+	char    bus_type[6];
+};
+
+struct mpbios_ioapic {
+	u_int8_t  type;
+	u_int8_t  apic_id;
+	u_int8_t  apic_version;
+	u_int8_t  apic_flags;
+#define IOAPICENTRY_FLAG_EN	0x01
+	void   *apic_address;
+};
+
+struct mpbios_int {
+	u_int8_t  type;
+	u_int8_t  int_type;
+	u_int16_t int_flags;
+	u_int8_t  src_bus_id;
+	u_int8_t  src_bus_irq;
+	u_int8_t  dst_apic_id;
+#define MPS_ALL_APICS	0xff
+	u_int8_t  dst_apic_int;
+};
+
+#endif /* !_I386_MPBIOSREG_H_ */
diff --git a/sys/arch/i386/include/mpbiosvar.h b/sys/arch/i386/include/mpbiosvar.h
new file mode 100644
index 00000000000..b617041b4d9
--- /dev/null
+++ b/sys/arch/i386/include/mpbiosvar.h
@@ -0,0 +1,88 @@
+/*	$OpenBSD: mpbiosvar.h,v 1.2 2004/06/13 21:49:16 niklas Exp $	*/
+/* $NetBSD: mpbiosvar.h,v 1.1.2.3 2000/02/29 13:17:20 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by RedBack Networks Inc.
+ *
+ * Author: Bill Sommerfeld
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _I386_MPBIOSVAR_H_
+#define _I386_MPBIOSVAR_H_
+
+#define MP_TRAMPOLINE  (2 * PAGE_SIZE)
+
+#if !defined(_LOCORE)
+
+#include <machine/mpbiosreg.h>
+
+struct mp_bus 
+{
+	char *mb_name;		/* XXX bus name */
+	int mb_idx;		/* XXX bus index */
+	void (*mb_intr_print) (int);
+	void (*mb_intr_cfg)(const struct mpbios_int *, u_int32_t *);
+	struct mp_intr_map *mb_intrs;
+	u_int32_t mb_data;	/* random bus-specific datum. */
+};
+
+struct mp_intr_map
+{
+	struct mp_intr_map *next;
+	struct mp_bus *bus;
+	int bus_pin;
+	struct ioapic_softc *ioapic;
+	int ioapic_pin;
+	int ioapic_ih;		/* int handle, for apic_intr_est */
+	int type;		/* from mp spec intr record */
+ 	int flags;		/* from mp spec intr record */
+	u_int32_t redir;
+};
+
+#if defined(_KERNEL)
+extern int mp_verbose;
+extern struct mp_bus *mp_busses;
+extern struct mp_intr_map *mp_intrs;
+extern int mp_isa_bus;
+extern int mp_eisa_bus;
+
+void mpbios_scan(struct device *);
+int mpbios_probe(struct device *);
+#endif
+
+#endif
+
+#endif /* !_I386_MPBIOSVAR_H_ */
diff --git a/sys/arch/i386/include/npx.h b/sys/arch/i386/include/npx.h
index d6f906efb46..810c7817bee 100644
--- a/sys/arch/i386/include/npx.h
+++ b/sys/arch/i386/include/npx.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: npx.h,v 1.6 2004/02/01 19:05:23 deraadt Exp $	*/
+/*	$OpenBSD: npx.h,v 1.7 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: npx.h,v 1.11 1994/10/27 04:16:11 cgd Exp $	*/
 
 /*-
@@ -180,5 +180,8 @@ struct	emcsts {
 
 void    process_xmm_to_s87(const struct savexmm *, struct save87 *);
 void    process_s87_to_xmm(const struct save87 *, struct savexmm *);
+struct cpu_info;
+
+void	npxinit(struct cpu_info *);
 
 #endif /* !_I386_NPX_H_ */
diff --git a/sys/arch/i386/include/param.h b/sys/arch/i386/include/param.h
index 0d1dfb68fd9..335d7737cbb 100644
--- a/sys/arch/i386/include/param.h
+++ b/sys/arch/i386/include/param.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: param.h,v 1.27 2004/04/19 22:55:49 deraadt Exp $	*/
+/*	$OpenBSD: param.h,v 1.28 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: param.h,v 1.29 1996/03/04 05:04:26 cgd Exp $	*/
 
 /*-
@@ -99,7 +99,7 @@
 #define	USPACE		(UPAGES * NBPG)	/* total size of u-area */
 
 #ifndef MSGBUFSIZE
-#define MSGBUFSIZE	2*NBPG		/* default message buffer size */
+#define MSGBUFSIZE	4*NBPG		/* default message buffer size */
 #endif
 
 /*
diff --git a/sys/arch/i386/include/pcb.h b/sys/arch/i386/include/pcb.h
index 611ab5996a8..641f8874f17 100644
--- a/sys/arch/i386/include/pcb.h
+++ b/sys/arch/i386/include/pcb.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pcb.h,v 1.11 2004/02/01 19:05:23 deraadt Exp $	*/
+/*	$OpenBSD: pcb.h,v 1.12 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: pcb.h,v 1.21 1996/01/08 13:51:42 mycroft Exp $	*/
 
 /*-
@@ -75,7 +75,8 @@ struct pcb {
 	int	vm86_eflags;		/* virtual eflags for vm86 mode */
 	int	vm86_flagmask;		/* flag mask for vm86 mode */
 	void	*vm86_userp;		/* XXX performance hack */
-	struct pmap *pcb_pmap;		/* back pointer to our pmap */
+	struct  pmap *pcb_pmap;         /* back pointer to our pmap */
+	struct	cpu_info *pcb_fpcpu;	/* cpu holding our fpu state */
 	u_long	pcb_iomap[NIOPORTS/32];	/* I/O bitmap */
 	u_char	pcb_iomap_pad;	/* required; must be 0xff, says intel */
 };
@@ -88,8 +89,4 @@ struct md_coredump {
 	long	md_pad[8];
 };    
 
-#ifdef _KERNEL
-struct pcb *curpcb;		/* our current running pcb */
-#endif
-
 #endif /* _I386_PCB_H_ */
diff --git a/sys/arch/i386/include/pmap.h b/sys/arch/i386/include/pmap.h
index 74013d8824c..a7089d958fd 100644
--- a/sys/arch/i386/include/pmap.h
+++ b/sys/arch/i386/include/pmap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.h,v 1.34 2004/05/20 09:20:42 kettenis Exp $	*/
+/*	$OpenBSD: pmap.h,v 1.35 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: pmap.h,v 1.44 2000/04/24 17:18:18 thorpej Exp $	*/
 
 /*
@@ -236,6 +236,12 @@
 #define PG_PVLIST	PG_AVAIL2	/* mapping has entry on pvlist */
 #define	PG_X		PG_AVAIL3	/* executable mapping */
 
+/*
+ * Number of PTE's per cache line.  4 byte pte, 32-byte cache line
+ * Used to avoid false sharing of cache lines.
+ */
+#define NPTECL			8
+
 #ifdef _KERNEL
 /*
  * pmap data structures: see pmap.c for details of locking.
@@ -272,6 +278,7 @@ struct pmap {
 	union descriptor *pm_ldt;	/* user-set LDT */
 	int pm_ldt_len;			/* number of LDT entries */
 	int pm_ldt_sel;			/* LDT selector */
+	uint32_t pm_cpus;		/* mask oc CPUs using map */
 };
 
 /* pm_flags */
@@ -330,19 +337,7 @@ struct pv_page {
 };
 
 /*
- * pmap_remove_record: a record of VAs that have been unmapped, used to
- * flush TLB.  If we have more than PMAP_RR_MAX then we stop recording.
- */
-
-#define PMAP_RR_MAX	16	/* max of 16 pages (64K) */
-
-struct pmap_remove_record {
-	int prr_npages;
-	vaddr_t prr_vas[PMAP_RR_MAX];
-};
-
-/*
- * Global kernel variables
+ * global kernel variables
  */
 
 extern pd_entry_t	PTD[];
@@ -394,6 +389,10 @@ int		pmap_exec_fixup(struct vm_map *, struct trapframe *,
 
 vaddr_t reserve_dumppages(vaddr_t); /* XXX: not a pmap fn */
 
+void	pmap_tlb_shootdown(pmap_t, vaddr_t, pt_entry_t, int32_t *);
+void	pmap_tlb_shootnow(int32_t);
+void	pmap_do_tlb_shootdown(struct cpu_info *);
+
 #define PMAP_GROWKERNEL		/* turn on pmap_growkernel interface */
 
 /*
diff --git a/sys/arch/i386/include/proc.h b/sys/arch/i386/include/proc.h
index ff0bc4b1bb3..e5393cd22e4 100644
--- a/sys/arch/i386/include/proc.h
+++ b/sys/arch/i386/include/proc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: proc.h,v 1.3 2003/06/02 23:27:47 millert Exp $	*/
+/*	$OpenBSD: proc.h,v 1.4 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: proc.h,v 1.10 1995/08/06 05:33:23 mycroft Exp $	*/
 
 /*
@@ -38,6 +38,7 @@
 struct mdproc {
 	struct	trapframe *md_regs;	/* registers on current frame */
 	int	md_flags;		/* machine-dependent flags */
+	int	md_tss_sel;		/* TSS selector */
 };
 
 /* md_flags */
diff --git a/sys/arch/i386/include/segments.h b/sys/arch/i386/include/segments.h
index ac01a2a2e26..3519f0a42ed 100644
--- a/sys/arch/i386/include/segments.h
+++ b/sys/arch/i386/include/segments.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: segments.h,v 1.12 2003/11/16 20:30:06 avsm Exp $	*/
+/*	$OpenBSD: segments.h,v 1.13 2004/06/13 21:49:16 niklas Exp $	*/
 /*	$NetBSD: segments.h,v 1.23 1996/02/01 22:31:03 mycroft Exp $	*/
 
 /*-
@@ -124,7 +124,7 @@ struct region_descriptor {
 #endif
 
 #ifdef _KERNEL
-extern union descriptor gdt[], ldt[];
+extern union descriptor *gdt, ldt[];
 extern struct gate_descriptor idt_region[];
 extern struct gate_descriptor *idt;
 
@@ -132,6 +132,13 @@ void setgate(struct gate_descriptor *, void *, int, int, int, int);
 void setregion(struct region_descriptor *, void *, size_t);
 void setsegment(struct segment_descriptor *, void *, size_t, int, int,
     int, int);
+void unsetgate(struct gate_descriptor *);
+void cpu_init_idt(void);
+
+int idt_vec_alloc(int, int);
+void idt_vec_set(int, void (*)(void));
+void idt_vec_free(int);
+
 #endif /* _KERNEL */
 
 #endif /* !_LOCORE */
@@ -220,7 +227,8 @@ void setsegment(struct segment_descriptor *, void *, size_t, int, int,
 #define	GAPM16CODE_SEL	8	/* 16 bit APM code descriptor */
 #define	GAPMDATA_SEL	9	/* APM data descriptor */
 #define	GICODE_SEL	10	/* Interrupt code descriptor (same as Kernel code) */
-#define	NGDT		11
+#define GCPU_SEL	11	/* per-CPU segment */
+#define	NGDT		12
 
 /*
  * Entries in the Local Descriptor Table (LDT)
diff --git a/sys/arch/i386/include/types.h b/sys/arch/i386/include/types.h
index 0da0bdc06e2..53f8a187136 100644
--- a/sys/arch/i386/include/types.h
+++ b/sys/arch/i386/include/types.h
@@ -1,5 +1,5 @@
 /*	$NetBSD: types.h,v 1.12 1995/12/24 01:08:03 mycroft Exp $	*/
-/*	$OpenBSD: types.h,v 1.13 2003/06/02 23:27:47 millert Exp $	*/
+/*	$OpenBSD: types.h,v 1.14 2004/06/13 21:49:16 niklas Exp $	*/
 
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
@@ -72,5 +72,6 @@ typedef	unsigned long long	 uint64_t;
 typedef int32_t			register_t;
 
 #define __HAVE_NWSCONS
+#define __HAVE_CPUINFO
 
 #endif	/* _MACHTYPES_H_ */