When reading MXCSR from userland sigcontext or a ptrace request,

mask out invalid bits to prevent a protect fault.

Original diff by joshe@; further feedback and ok kettenis@

1 files changed, 16 insertions, 1 deletions

diff --git a/sys/arch/i386/isa/npx.c b/sys/arch/i386/isa/npx.c
index ade5e5872f2..0699d910b03 100644
--- a/sys/arch/i386/isa/npx.c
+++ b/sys/arch/i386/isa/npx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: npx.c,v 1.53 2010/09/29 15:11:31 joshe Exp $	*/
+/*	$OpenBSD: npx.c,v 1.54 2011/03/20 21:44:08 guenther Exp $	*/
 /*	$NetBSD: npx.c,v 1.57 1996/05/12 23:12:24 mycroft Exp $	*/
 
 #if 0
@@ -97,6 +97,11 @@
 #define	clts()			__asm("clts")
 #define	stts()			lcr0(rcr0() | CR0_TS)
 
+/*
+ * The mxcsr_mask for this host, taken from fxsave() on the primary CPU
+ */
+uint32_t	fpu_mxcsr_mask;
+
 int npxintr(void *);
 static int npxprobe1(struct isa_attach_args *);
 static int x86fpflags_to_siginfo(u_int32_t);
@@ -351,6 +356,16 @@ npxinit(struct cpu_info *ci)
 		printf("%s: WARNING: Pentium FDIV bug detected!\n",
 		    ci->ci_dev.dv_xname);
 	}
+	if (fpu_mxcsr_mask == 0 && i386_use_fxsave) {
+		struct savexmm xm __attribute__((aligned(16)));
+
+		bzero(&xm, sizeof(xm));
+		fxsave(&xm);
+		if (xm.sv_env.en_mxcsr_mask)
+			fpu_mxcsr_mask = xm.sv_env.en_mxcsr_mask;
+		else
+			fpu_mxcsr_mask = __INITIAL_MXCSR_MASK__;
+	}
 	lcr0(rcr0() | (CR0_TS));
 }