diff options
| author | Paul Irofti <pirofti@cvs.openbsd.org> | 2010-09-24 10:30:30 +0000 |
|---|---|---|
| committer | Paul Irofti <pirofti@cvs.openbsd.org> | 2010-09-24 10:30:30 +0000 |
| commit | 96564fe2f4faed51094b510dcedf3727772ff928 (patch) | |
| tree | 068fc7d802a653882e56815f8012c32df242f37e /sys/arch/i386 | |
| parent | 44ac50792bd1758adb3feaf7a26aa0eeeaf7f934 (diff) | |
Fix bus space mapping bugs for GPIO's and MFGPT's and while at it add proper
defines for the constants used while mapping.
Okay miod@, deraadt@.
Diffstat (limited to 'sys/arch/i386')
| -rw-r--r-- | sys/arch/i386/pci/glxpcib.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/sys/arch/i386/pci/glxpcib.c b/sys/arch/i386/pci/glxpcib.c index c1c1dc92e7d..824480bf2cf 100644 --- a/sys/arch/i386/pci/glxpcib.c +++ b/sys/arch/i386/pci/glxpcib.c @@ -1,4 +1,4 @@ -/* $OpenBSD: glxpcib.c,v 1.12 2010/09/22 04:24:19 pirofti Exp $ */ +/* $OpenBSD: glxpcib.c,v 1.13 2010/09/24 10:30:29 pirofti Exp $ */ /* * Copyright (c) 2007 Marc Balmer <mbalmer@openbsd.org> @@ -40,8 +40,12 @@ #define AMD5536_REV_MASK 0xff #define AMD5536_TMC 0x51400050 +#define MSR_LBAR_ENABLE 0x100000000ULL + /* Multi-Functional General Purpose Timer */ #define MSR_LBAR_MFGPT 0x5140000d +#define MSR_MFGPT_SIZE 0x40 +#define MSR_MFGPT_ADDR_MASK 0xffc0 #define AMD5536_MFGPT0_CMP1 0x00000000 #define AMD5536_MFGPT0_CMP2 0x00000002 #define AMD5536_MFGPT0_CNT 0x00000004 @@ -107,6 +111,8 @@ /* GPIO */ #define MSR_LBAR_GPIO 0x5140000c +#define MSR_GPIO_SIZE 0x100 +#define MSR_GPIO_ADDR_MASK 0xff00 #define AMD5536_GPIO_NPINS 32 #define AMD5536_GPIOH_OFFSET 0x80 /* high bank register offset */ #define AMD5536_GPIO_OUT_VAL 0x00 /* output value */ @@ -204,8 +210,9 @@ glxpcib_attach(struct device *parent, struct device *self, void *aux) /* Attach the watchdog timer */ sc->sc_iot = pa->pa_iot; wa = rdmsr(MSR_LBAR_MFGPT); - if (wa & 0x100000000ULL && - !bus_space_map(sc->sc_iot, wa & 0xffff, 64, 0, &sc->sc_ioh)) { + if (wa & MSR_LBAR_ENABLE && + !bus_space_map(sc->sc_iot, wa & MSR_MFGPT_ADDR_MASK, + MSR_MFGPT_SIZE, 0, &sc->sc_ioh)) { /* count in seconds (as upper level desires) */ bus_space_write_2(sc->sc_iot, sc->sc_ioh, AMD5536_MFGPT0_SETUP, @@ -219,9 +226,9 @@ glxpcib_attach(struct device *parent, struct device *self, void *aux) /* map GPIO I/O space */ sc->sc_gpio_iot = pa->pa_iot; ga = rdmsr(MSR_LBAR_GPIO); - if (ga & 0x100000000ULL && - !bus_space_map(sc->sc_gpio_iot, ga & 0xffff, 0xff, 0, - &sc->sc_gpio_ioh)) { + if (ga & MSR_LBAR_ENABLE && + !bus_space_map(sc->sc_gpio_iot, ga & MSR_GPIO_ADDR_MASK, + MSR_GPIO_SIZE, 0, &sc->sc_gpio_ioh)) { printf(", gpio"); /* initialize pin array */ |