Some implementations of HitSyncDCache() call pmap_extract() for va->pa

conversion. Because pmap_extract() acquires the PTE mutex, a "locking
against myself" panic is triggered if the cache routine gets called in
a context where the mutex is already held.

In the pmap, all calls to HitSyncDCache() are for a whole page. Add a
new cache routine, HitSyncDCachePage(), which gets both the va and the
pa of a page. This removes the need of the va->pa conversion. The new
routine has the same signature as SyncDCachePage(), allowing reuse of
the same routine for cache implementations that do not need differences
between "Hit" and non-"Hit" routines.

With the diff, POWER Indigo2 R8000 boots multiuser again. Tested on sgi
GENERIC-IP27.MP and octeon GENERIC.MP, too.

Diff from miod@, ok kettenis@

1 files changed, 5 insertions, 1 deletions

diff --git a/sys/arch/loongson/include/cpu.h b/sys/arch/loongson/include/cpu.h
index 51d004f955c..6120b24e787 100644
--- a/sys/arch/loongson/include/cpu.h
+++ b/sys/arch/loongson/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.5 2015/08/15 22:31:38 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.6 2016/01/05 05:27:54 visa Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -54,6 +54,8 @@
 	Loongson2_SyncICache((ci))
 #define	Mips_SyncDCachePage(ci, va, pa)		\
 	Loongson2_SyncDCachePage((ci), (va), (pa))
+#define	Mips_HitSyncDCachePage(ci, va, pa)	\
+	Loongson2_SyncDCachePage((ci), (va), (pa))
 #define	Mips_HitSyncDCache(ci, va, l)	\
 	Loongson2_HitSyncDCache((ci), (va), (l))
 #define	Mips_IOSyncDCache(ci, va, l, h)	\
@@ -73,6 +75,8 @@
 	Loongson3_SyncICache((ci))
 #define	Mips_SyncDCachePage(ci, va, pa)		\
 	Loongson3_SyncDCachePage((ci), (va), (pa))
+#define	Mips_HitSyncDCachePage(ci, va, pa)	\
+	Loongson3_SyncDCachePage((ci), (va), (pa))
 #define	Mips_HitSyncDCache(ci, va, l)	\
 	Loongson3_HitSyncDCache((ci), (va), (l))
 #define	Mips_IOSyncDCache(ci, va, l, h)	\