Common pmap defines and code for all m68k platforms using Motorola (or

compatible) MMU.

2 files changed, 312 insertions, 0 deletions

diff --git a/sys/arch/m68k/include/pmap_motorola.h b/sys/arch/m68k/include/pmap_motorola.h
new file mode 100644
index 00000000000..7c71352bdab
--- /dev/null
+++ b/sys/arch/m68k/include/pmap_motorola.h
@@ -0,0 +1,160 @@
+/*	$OpenBSD: pmap_motorola.h,v 1.1 2001/11/30 20:54:50 miod Exp $	*/
+
+/* 
+ * Copyright (c) 1987 Carnegie-Mellon University
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)pmap.h	8.1 (Berkeley) 6/10/93
+ */
+
+#ifndef	_PMAP_MOTOROLA_H_
+#define	_PMAP_MOTOROLA_H_
+
+#include <machine/cpu.h>
+#include <machine/pte.h>
+
+/*
+ * Pmap stuff
+ */
+struct pmap {
+	pt_entry_t		*pm_ptab;	/* KVA of page table */
+	st_entry_t		*pm_stab;	/* KVA of segment table */
+	int			pm_stfree;	/* 040: free lev2 blocks */
+	st_entry_t		*pm_stpa;	/* 040: ST phys addr */
+	short			pm_sref;	/* segment table ref count */
+	short			pm_count;	/* pmap reference count */
+	struct simplelock	pm_lock;	/* lock on pmap */
+	struct pmap_statistics	pm_stats;	/* pmap statistics */
+	long			pm_ptpages;	/* more stats: PT pages */
+};
+
+typedef struct pmap	*pmap_t;
+
+/*
+ * On the 040 we keep track of which level 2 blocks are already in use
+ * with the pm_stfree mask.  Bits are arranged from LSB (block 0) to MSB
+ * (block 31).  For convenience, the level 1 table is considered to be
+ * block 0.
+ *
+ * MAX[KU]L2SIZE control how many pages of level 2 descriptors are allowed.
+ * for the kernel and users.  8 implies only the initial "segment table"
+ * page is used.  WARNING: don't change MAXUL2SIZE unless you can allocate
+ * physically contiguous pages for the ST in pmap.c!
+ */
+#define	MAXKL2SIZE	32
+#define MAXUL2SIZE	8
+#define l2tobm(n)	(1 << (n))
+#define	bmtol2(n)	(ffs(n) - 1)
+
+/*
+ * Macros for speed
+ */
+#define PMAP_ACTIVATE(pmap, loadhw)					\
+{									\
+        if ((loadhw))							\
+                loadustp(m68k_btop((paddr_t)(pmap)->pm_stpa));		\
+}
+
+/*
+ * For each vm_page_t, there is a list of all currently valid virtual
+ * mappings of that page.  An entry is a pv_entry, the list is pv_table.
+ */
+struct pv_entry {
+	struct pv_entry	*pv_next;	/* next pv_entry */
+	struct pmap	*pv_pmap;	/* pmap where mapping lies */
+	vaddr_t		pv_va;		/* virtual address for mapping */
+	st_entry_t	*pv_ptste;	/* non-zero if VA maps a PT page */
+	struct pmap	*pv_ptpmap;	/* if pv_ptste, pmap for PT page */
+	int		pv_flags;	/* flags */
+};
+
+#define	PV_CI		0x01	/* header: all entries are cache inhibited */
+#define PV_PTPAGE	0x02	/* header: entry maps a page table page */
+
+struct pv_page;
+
+struct pv_page_info {
+	TAILQ_ENTRY(pv_page) pgi_list;
+	struct pv_entry *pgi_freelist;
+	int pgi_nfree;
+};
+
+/*
+ * This is basically:
+ * ((PAGE_SIZE - sizeof(struct pv_page_info)) / sizeof(struct pv_entry))
+ */
+#if PAGE_SHIFT == 13
+#define	NPVPPG	340
+#elif PAGE_SHIFT == 12
+#define	NPVPPG	170
+#endif
+
+struct pv_page {
+	struct pv_page_info pvp_pgi;
+	struct pv_entry pvp_pv[NPVPPG];
+};
+
+#ifdef	_KERNEL
+
+extern struct pmap	kernel_pmap_store;
+
+#define pmap_kernel()	(&kernel_pmap_store)
+#define	active_pmap(pm) \
+	((pm) == pmap_kernel() || (pm) == curproc->p_vmspace->vm_map.pmap)
+#define	active_user_pmap(pm) \
+	(curproc && \
+	 (pm) != pmap_kernel() && (pm) == curproc->p_vmspace->vm_map.pmap)
+
+extern struct pv_entry	*pv_table;	/* array of entries, one per page */
+
+#define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
+#define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
+
+#define	pmap_update()			/* nothing */
+
+extern pt_entry_t	*Sysmap;
+extern char		*vmmap;		/* map for mem, dumps, etc. */
+
+#ifdef M68K_MMU_HP
+void	pmap_prefer __P((vaddr_t, vaddr_t *));
+#define	PMAP_PREFER(foff, vap)	pmap_prefer((foff), (vap))
+#endif
+
+vaddr_t	pmap_map __P((vaddr_t, paddr_t, paddr_t, int));
+
+#endif	/* _KERNEL */
+
+#endif /* !_PMAP_MOTOROLA_H_ */
diff --git a/sys/arch/m68k/include/pte_motorola.h b/sys/arch/m68k/include/pte_motorola.h
new file mode 100644
index 00000000000..a250eaa82e1
--- /dev/null
+++ b/sys/arch/m68k/include/pte_motorola.h
@@ -0,0 +1,152 @@
+/*	$OpenBSD: pte_motorola.h,v 1.1 2001/11/30 20:54:50 miod Exp $	*/
+
+/*
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1982, 1986, 1990, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah $Hdr: pte.h 1.13 92/01/20$
+ *
+ *	@(#)pte.h	8.1 (Berkeley) 6/10/93
+ */
+
+#ifndef	_PTE_MOTOROLA_H_
+#define	_PTE_MOTOROLA_H_
+
+/*
+ * m68k hardware with motorola MMU segment/page table entries
+ */
+
+#if 0
+struct ste {
+	unsigned int	sg_pfnum:20;	/* page table frame number */
+	unsigned int	:8;		/* reserved at 0 */
+	unsigned int	:1;		/* reserved at 1 */
+	unsigned int	sg_prot:1;	/* write protect bit */
+	unsigned int	sg_v:2;		/* valid bits */
+};
+
+struct ste40 {
+	unsigned int	sg_ptaddr:24;	/* page table page addr */
+	unsigned int	:4;		/* reserved at 0 */
+	unsigned int	sg_u;		/* hardware modified (dirty) bit */
+	unsigned int	sg_prot:1;	/* write protect bit */
+	unsigned int	sg_v:2;		/* valid bits */
+};
+
+struct pte {
+	unsigned int	pg_pfnum:20;	/* page frame number or 0 */
+	unsigned int	:3;
+	unsigned int	pg_w:1;		/* is wired */
+	unsigned int	:1;		/* reserved at zero */
+	unsigned int	pg_ci:1;	/* cache inhibit bit */
+	unsigned int	:1;		/* reserved at zero */
+	unsigned int	pg_m:1;		/* hardware modified (dirty) bit */
+	unsigned int	pg_u:1;		/* hardware used (reference) bit */
+	unsigned int	pg_prot:1;	/* write protect bit */
+	unsigned int	pg_v:2;		/* valid bit */
+};
+#endif
+
+typedef int	st_entry_t;	/* segment table entry */
+typedef int	pt_entry_t;	/* Mach page table entry */
+
+#define	PT_ENTRY_NULL	((pt_entry_t *) 0)
+#define	ST_ENTRY_NULL	((st_entry_t *) 0)
+
+#define	SG_V		0x00000002	/* segment is valid */
+#define	SG_NV		0x00000000
+#define	SG_PROT		0x00000004	/* access protection mask */
+#define	SG_RO		0x00000004
+#define	SG_RW		0x00000000
+#define	SG_U		0x00000008	/* modified bit (68040) */
+#define	SG_FRAME	0xfffff000
+#define	SG_IMASK	0xffc00000
+#define	SG_ISHIFT	22
+#define	SG_PMASK	0x003ff000
+#define	SG_PSHIFT	12
+
+/* 68040 additions */
+#define	SG4_MASK1	0xfe000000
+#define	SG4_SHIFT1	25
+#define	SG4_MASK2	0x01fc0000
+#define	SG4_SHIFT2	18
+#define	SG4_MASK3	0x0003f000
+#define	SG4_SHIFT3	12
+#define	SG4_ADDR1	0xfffffe00
+#define	SG4_ADDR2	0xffffff00
+#define	SG4_LEV1SIZE	128
+#define	SG4_LEV2SIZE	128
+#define	SG4_LEV3SIZE	64
+
+#define	PG_V		0x00000001
+#define	PG_NV		0x00000000
+#define	PG_PROT		0x00000004
+#define	PG_U		0x00000008
+#define	PG_M		0x00000010
+#define	PG_W		0x00000100
+#define	PG_RO		0x00000004
+#define	PG_RW		0x00000000
+#define	PG_FRAME	0xfffff000
+#define	PG_CI		0x00000040
+#define PG_SHIFT	12
+#define	PG_PFNUM(x)	(((x) & PG_FRAME) >> PG_SHIFT)
+
+/* 68040 additions */
+#define	PG_CMASK	0x00000060	/* cache mode mask */
+#define	PG_CWT		0x00000000	/* writethrough caching */
+#define	PG_CCB		0x00000020	/* copyback caching */
+#define	PG_CIS		0x00000040	/* cache inhibited serialized */
+#define	PG_CIN		0x00000060	/* cache inhibited nonserialized */
+#define	PG_SO		0x00000080	/* supervisor only */
+
+#define M68K_STSIZE	(MAXUL2SIZE*SG4_LEV2SIZE*sizeof(st_entry_t))
+					/* user process segment table size */
+#define M68K_MAX_PTSIZE	0x400000	/* max size of UPT */
+#define M68K_MAX_KPTSIZE 0x100000	/* max memory to allocate to KPT */
+#define M68K_PTBASE	0x10000000	/* UPT map base address */
+#define M68K_PTMAXSIZE	0x70000000	/* UPT map maximum size */
+
+/*
+ * Kernel virtual address to page table entry and to physical address.
+ */
+#define	kvtopte(va) \
+	(&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])
+#define	ptetokv(pt) \
+	((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
+#define	kvtophys(va) \
+	((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET))
+
+#endif /* !_PTE_MOTOROLA_H_ */