diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2007-11-22 23:30:12 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2007-11-22 23:30:12 +0000 |
| commit | 98803743fe4599010ed7599ea93efdb5b66de049 (patch) | |
| tree | 29b59f05d4653073033fdb1d2ea1660cf1adee71 /sys/arch/m88k | |
| parent | cc50a872bba6c27bc4be728c57d373773b6ef253 (diff) | |
Do not reenable interrupts for netsted interrupts if interrupts were
previously disabled on 88110, similar to a recent 88100 fix.
Diffstat (limited to 'sys/arch/m88k')
| -rw-r--r-- | sys/arch/m88k/m88k/eh_common.S | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/sys/arch/m88k/m88k/eh_common.S b/sys/arch/m88k/m88k/eh_common.S index 0a081b9d564..d4e87ecc160 100644 --- a/sys/arch/m88k/m88k/eh_common.S +++ b/sys/arch/m88k/m88k/eh_common.S @@ -1,4 +1,4 @@ -/* $OpenBSD: eh_common.S,v 1.37 2007/11/22 23:29:27 miod Exp $ */ +/* $OpenBSD: eh_common.S,v 1.38 2007/11/22 23:30:11 miod Exp $ */ /* * Mach Operating System * Copyright (c) 1993-1991 Carnegie Mellon University @@ -2162,8 +2162,8 @@ ASLOCAL(m88110_fpu_enable) * take care of any data access exceptions...... */ or r30, r0, r31 /* get a copy of the e.f. pointer */ - ld r2, r31, REG_OFF(EF_EPSR) - bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* if in kernel mode */ + ld r6, r31, REG_OFF(EF_EPSR) + bb1 PSR_SUPERVISOR_MODE_BIT, r6, 1f /* if in kernel mode */ ldcr r31, CPU ld r31, r31, CI_CURPCB @@ -2182,7 +2182,7 @@ ASLOCAL(m88110_fpu_enable) ld r2, r30, REG_OFF(EF_VECTOR) bcnd.n eq0, r2, 8f - ld r14, r30, REG_OFF(EF_RET) /* load return value XXX!!! */ + ld r14, r30, REG_OFF(EF_RET) cmp r3, r2, 1 /* is an interrupt? */ bb1.n eq, r3, 8f cmp r3, r2, 11 /* or NMI? */ @@ -2191,12 +2191,14 @@ ASLOCAL(m88110_fpu_enable) #ifdef DDB cmp r3, r2, 130 /* DDB break exception */ bb1.n eq, r3, 8f - cmp r3, r2, 132 /* DDB entry exception */ bb1.n eq, r3, 8f #endif - /* turn interrupts back on */ + /* turn interrupts back on unless they were not enabled when the + trap occured */ + bb1 PSR_INTERRUPT_DISABLE_BIT, r6, 8f + ldcr r2, PSR clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> stcr r2, PSR |