diff options
| author | Martin Reindl <martin@cvs.openbsd.org> | 2004-12-14 14:50:56 +0000 |
|---|---|---|
| committer | Martin Reindl <martin@cvs.openbsd.org> | 2004-12-14 14:50:56 +0000 |
| commit | cdc7995df40491d67962f86a405d15c9e0d88682 (patch) | |
| tree | 81cc64aed94be9fb89e182833c9e0b2e8ec9824d /sys/arch/mac68k/include | |
| parent | 30c1bf297e8c0da0684c753242d9a7959043e6c8 (diff) | |
sync with NetBSD, ok miod@
Diffstat (limited to 'sys/arch/mac68k/include')
| -rw-r--r-- | sys/arch/mac68k/include/psc.h | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/sys/arch/mac68k/include/psc.h b/sys/arch/mac68k/include/psc.h index 59f28b5f51b..999e30b6c41 100644 --- a/sys/arch/mac68k/include/psc.h +++ b/sys/arch/mac68k/include/psc.h @@ -1,8 +1,8 @@ -/* $OpenBSD: psc.h,v 1.4 2002/03/14 03:15:55 millert Exp $ */ -/* $NetBSD: psc.h,v 1.3 1998/04/24 05:27:24 scottr Exp $ */ +/* $OpenBSD: psc.h,v 1.5 2004/12/14 14:50:55 martin Exp $ */ +/* $NetBSD: psc.h,v 1.5 2004/03/26 12:15:46 wiz Exp $ */ /*- - * Copyright (c) 1997 David Huang <khym@bga.com> + * Copyright (c) 1997 David Huang <khym@azeotrope.org> * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -72,6 +72,9 @@ int remove_psc_lev6_intr(int); */ /* PSC interrupt registers */ +#define PSC_ISR_BASE 0x100 /* ISR is BASE + 0x10 * level */ +#define PSC_IER_BASE 0x104 /* IER is BASE + 0x10 * level */ + #define PSC_LEV3_ISR 0x130 /* level 3 interrupt status register */ #define PSC_LEV3_IER 0x134 /* level 3 interrupt enable register */ #define PSCINTR_ENET 0 /* Ethernet interrupt */ @@ -89,10 +92,24 @@ int remove_psc_lev6_intr(int); #define PSC_LEV6_IER 0x164 /* level 6 interrupt enable register */ /* PSC DMA channel control registers */ +#define PSC_CTLBASE 0xc00 + +#define PSC_SCSI_CTL 0xc00 /* SCSI control/status */ #define PSC_ENETRD_CTL 0xc10 /* MACE receive DMA channel control/status */ #define PSC_ENETWR_CTL 0xc20 /* MACE transmit DMA channel control/status */ +#define PSC_FDC_CTL 0xc30 /* Floppy disk */ +#define PSC_SCCA_CTL 0xc40 /* SCC channel A */ +#define PSC_SCCB_CTL 0xc50 /* SCC channel B */ +#define PSC_SCCATX_CTL 0xc60 /* SCC channel A transmit */ /* PSC DMA channels */ +#define PSC_ADDRBASE 0x1000 +#define PSC_LENBASE 0x1004 +#define PSC_CMDBASE 0x1008 + +#define PSC_SCSI_ADDR 0x1000 /* SCSI DMA address register */ +#define PSC_SCSI_LEN 0x1004 /* SCSI DMA buffer count */ +#define PSC_SCSI_CMD 0x1008 /* SCSI DMA command register */ #define PSC_ENETRD_ADDR 0x1020 /* MACE receive DMA address register */ #define PSC_ENETRD_LEN 0x1024 /* MACE receive DMA buffer count */ #define PSC_ENETRD_CMD 0x1028 /* MACE receive DMA command register */ |