diff options
| author | Martin Pieuchot <mpi@cvs.openbsd.org> | 2012-08-30 18:14:27 +0000 |
|---|---|---|
| committer | Martin Pieuchot <mpi@cvs.openbsd.org> | 2012-08-30 18:14:27 +0000 |
| commit | 32972f39c5ccd273a581772a01b7243a39952c92 (patch) | |
| tree | 989c22d66328602dc1064e5c9fb730cca91d48be /sys/arch/macppc/include/bus.h | |
| parent | 8f669f7aa4f735e08b585b27c459d4a45163ab14 (diff) | |
Add the possibility to map DMA memory non-cached, based on the i386/amd64
implementation. For the moment only the BUS_DMA_NOCACHE macro is required
to build drm on macppc but it will be used soon.
ok kettenis@
Diffstat (limited to 'sys/arch/macppc/include/bus.h')
| -rw-r--r-- | sys/arch/macppc/include/bus.h | 35 |
1 files changed, 22 insertions, 13 deletions
diff --git a/sys/arch/macppc/include/bus.h b/sys/arch/macppc/include/bus.h index 462766c33ef..eb00af8b577 100644 --- a/sys/arch/macppc/include/bus.h +++ b/sys/arch/macppc/include/bus.h @@ -1,4 +1,4 @@ -/* $OpenBSD: bus.h,v 1.20 2012/08/24 10:05:25 jsg Exp $ */ +/* $OpenBSD: bus.h,v 1.21 2012/08/30 18:14:26 mpi Exp $ */ /* * Copyright (c) 1997 Per Fogelstrom. All rights reserved. @@ -81,6 +81,14 @@ void bus_space_free(bus_space_tag_t tag, bus_space_handle_t handle, #define BUS_SPACE_MAP_LINEAR 0x02 #define BUS_SPACE_MAP_PREFETCHABLE 0x04 +/* + * void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t); + * + * Get the kernel virtual address for the mapped bus space. + * Only allowed for regions mapped with BUS_SPACE_MAP_LINEAR. + */ +#define bus_space_vaddr(t, h) ((void *)(h)) + #define bus_space_read(n,m) \ static __inline CAT3(u_int,m,_t) \ CAT(bus_space_read_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \ @@ -439,18 +447,19 @@ bus_space_copy_4(void *v, bus_space_handle_t h1, bus_space_handle_t h2, #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ -#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ -#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ -#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ -#define BUS_DMA_COHERENT 0x008 /* hint: map memory DMA coherent */ -#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ -#define BUS_DMA_BUS2 0x020 -#define BUS_DMA_BUS3 0x040 -#define BUS_DMA_BUS4 0x080 -#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ -#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ -#define BUS_DMA_STREAMING 0x400 /* hint: sequential, unidirectional */ -#define BUS_DMA_ZERO 0x800 /* zero memory in dmamem_alloc */ +#define BUS_DMA_WAITOK 0x0000 /* safe to sleep (pseudo-flag) */ +#define BUS_DMA_NOWAIT 0x0001 /* not safe to sleep */ +#define BUS_DMA_ALLOCNOW 0x0002 /* perform resource allocation now */ +#define BUS_DMA_COHERENT 0x0008 /* hint: map memory DMA coherent */ +#define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */ +#define BUS_DMA_BUS2 0x0020 +#define BUS_DMA_BUS3 0x0040 +#define BUS_DMA_BUS4 0x0080 +#define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */ +#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */ +#define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */ +#define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */ +#define BUS_DMA_NOCACHE 0x1000 /* map memory uncached */ /* Forwards needed by prototypes below. */ |