Basic R8000 processor support. R8000 processors require MMU-specific code,

exception-specific code, clock-specific code, and L1 cache-specific code. L2
cache is per-design, of which only two exist: SGI Power Indigo2 (IP26) and SGI
Power Challenge (IP21) and are not covered by this commit.

R8000 processors also are 64-bit only processors with 64-bit coprocessor 0
registers, and lack so-called ``compatibility'' memory spaces allowing 32-bit
code to run with sign-extended addresses and registers.

The intrusive changes are covered by #ifdef CPU_R8000 stanzas. However,
trap() is split into a high-level wrapper and a new function, itsa(),
responsible for the actual trap servicing (which name couldn't be helped
because I'm an incorrigible punster). While an R8000 exception may cause
(via trap() ) multiple exceptions to be serviced, non-R8000 processors will
always service one exception in trap(), but they are nevertheless affected
by this code split.

1 files changed, 7 insertions, 2 deletions

diff --git a/sys/arch/mips64/include/cache.h b/sys/arch/mips64/include/cache.h
index 300b6b4d00f..7942cd9838b 100644
--- a/sys/arch/mips64/include/cache.h
+++ b/sys/arch/mips64/include/cache.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache.h,v 1.4 2012/06/24 20:20:37 miod Exp $	*/
+/*	$OpenBSD: cache.h,v 1.5 2012/09/29 21:37:03 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -66,6 +66,11 @@ CACHE_PROTOS(Mips4k)
 CACHE_PROTOS(Mips5k)
 
 /*
+ * MIPS (SGI, really) R8000.
+ */
+CACHE_PROTOS(tfp)
+
+/*
  * MIPS/NEC R10000/R120000/R140000/R16000.
  */
 CACHE_PROTOS(Mips10k)
@@ -75,7 +80,7 @@ CACHE_PROTOS(Mips10k)
  * bus_dmamap_sync()].
  */
 #define	CACHE_SYNC_R	0	/* WB invalidate, WT invalidate */
-#define	CACHE_SYNC_W	1	/* WB writeback + invalidate, WT unaffected */
+#define	CACHE_SYNC_W	1	/* WB writeback, WT unaffected */
 #define	CACHE_SYNC_X	2	/* WB writeback + invalidate, WT invalidate */
 
 extern vaddr_t cache_valias_mask;