diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2009-12-25 21:02:19 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2009-12-25 21:02:19 +0000 |
| commit | 3836ca8306b726cffaf7e80d5dfb0a635b09c6b0 (patch) | |
| tree | add3a4bf286f00beaa238d506fad53482f7f0d2e /sys/arch/mips64/include/cpu.h | |
| parent | ca308c11ec65dd43d8b9a8592692d0479e41c60b (diff) | |
Pass both the virtual address and the physical address of the memory range
when invoking the cache functions. The physical address is needed when
operating on physically-indexed caches, such as the L2 cache on Loongson
processors.
Preprocessor abuse makes sure that the physical address computation gets
compiled out when running on a kernel compiled for virtually-indexed
caches only, such as the sgi kernel.
Diffstat (limited to 'sys/arch/mips64/include/cpu.h')
| -rw-r--r-- | sys/arch/mips64/include/cpu.h | 43 |
1 files changed, 16 insertions, 27 deletions
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h index 8ef35ced8ef..34cb7ecc529 100644 --- a/sys/arch/mips64/include/cpu.h +++ b/sys/arch/mips64/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.47 2009/12/07 19:05:57 miod Exp $ */ +/* $OpenBSD: cpu.h,v 1.48 2009/12/25 21:02:13 miod Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -212,7 +212,7 @@ extern vaddr_t uncached_base; /* * Location of exception vectors. */ -#define RESET_EXC_VEC (CKSEG0_BASE + 0x3fc00000) +#define RESET_EXC_VEC (CKSEG1_BASE + 0x1fc00000) #define TLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000000) #define XTLB_MISS_EXC_VEC (CKSEG0_BASE + 0x00000080) #define CACHE_ERR_EXC_VEC (CKSEG0_BASE + 0x00000100) @@ -563,43 +563,32 @@ void tlb_set_pid(int); void tlb_set_wired(int); /* - * Define soft selected cache functions. + * Available cache operation routines. See <machine/cpu.h> for more. */ -#define Mips_SyncCache() (*(sys_config._SyncCache))() -#define Mips_InvalidateICache(a, l) \ - (*(sys_config._InvalidateICache))((a), (l)) -#define Mips_SyncDCachePage(a) \ - (*(sys_config._SyncDCachePage))((a)) -#define Mips_HitSyncDCache(a, l) \ - (*(sys_config._HitSyncDCache))((a), (l)) -#define Mips_IOSyncDCache(a, l, h) \ - (*(sys_config._IOSyncDCache))((a), (l), (h)) -#define Mips_HitInvalidateDCache(a, l) \ - (*(sys_config._HitInvalidateDCache))((a), (l)) int Loongson2_ConfigCache(void); void Loongson2_SyncCache(void); -void Loongson2_InvalidateICache(vaddr_t, int); -void Loongson2_SyncDCachePage(vaddr_t); -void Loongson2_HitSyncDCache(vaddr_t, int); -void Loongson2_IOSyncDCache(vaddr_t, int, int); -void Loongson2_HitInvalidateDCache(vaddr_t, int); +void Loongson2_InvalidateICache(vaddr_t, size_t); +void Loongson2_SyncDCachePage(paddr_t); +void Loongson2_HitSyncDCache(paddr_t, size_t); +void Loongson2_HitInvalidateDCache(paddr_t, size_t); +void Loongson2_IOSyncDCache(paddr_t, size_t, int); int Mips5k_ConfigCache(void); void Mips5k_SyncCache(void); -void Mips5k_InvalidateICache(vaddr_t, int); +void Mips5k_InvalidateICache(vaddr_t, size_t); void Mips5k_SyncDCachePage(vaddr_t); -void Mips5k_HitSyncDCache(vaddr_t, int); -void Mips5k_IOSyncDCache(vaddr_t, int, int); -void Mips5k_HitInvalidateDCache(vaddr_t, int); +void Mips5k_HitSyncDCache(vaddr_t, size_t); +void Mips5k_HitInvalidateDCache(vaddr_t, size_t); +void Mips5k_IOSyncDCache(vaddr_t, size_t, int); int Mips10k_ConfigCache(void); void Mips10k_SyncCache(void); -void Mips10k_InvalidateICache(vaddr_t, int); +void Mips10k_InvalidateICache(vaddr_t, size_t); void Mips10k_SyncDCachePage(vaddr_t); -void Mips10k_HitSyncDCache(vaddr_t, int); -void Mips10k_IOSyncDCache(vaddr_t, int, int); -void Mips10k_HitInvalidateDCache(vaddr_t, int); +void Mips10k_HitSyncDCache(vaddr_t, size_t); +void Mips10k_HitInvalidateDCache(vaddr_t, size_t); +void Mips10k_IOSyncDCache(vaddr_t, size_t, int); void tlb_flush(int); void tlb_flush_addr(vaddr_t); |