Use a shorter form to load XKPHYS constants in .S code, shaves a few text

bytes, no functional change.

3 files changed, 37 insertions, 23 deletions

diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 99b41598cd0..4b4b42c046a 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.18 2007/05/07 18:42:12 kettenis Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.19 2007/06/18 20:25:53 miod Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -70,8 +70,10 @@
  * Cache Coherency Attributes
  * We only list values common to r4k and r5k.
  */
+#if !defined(_LOCORE)
 #define	CCA_NC			2UL	/* uncached, write-around */
 #define	CCA_NONCOHERENT		3UL	/* cached, non-coherent, write-back */
+#endif
 
 #ifdef __LP64__
 #define	XKPHYS_BASE		0x8000000000000000UL
diff --git a/sys/arch/mips64/mips64/cache_r10k.S b/sys/arch/mips64/mips64/cache_r10k.S
index 3a07f9ce12c..82cfd70de64 100644
--- a/sys/arch/mips64/mips64/cache_r10k.S
+++ b/sys/arch/mips64/mips64/cache_r10k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r10k.S,v 1.4 2007/05/27 09:23:04 miod Exp $ */
+/*	$OpenBSD: cache_r10k.S,v 1.5 2007/06/18 20:25:55 miod Exp $ */
 
 /*
  * Copyright (c) 2004 Opsycon AB (www.opsycon.se)
@@ -47,6 +47,10 @@
 
 	.set	mips3
 
+#define	LOAD_XKPHYS(reg, cca) \
+	li	reg, cca | 0x10; \
+	dsll	reg, reg, 59
+
 /*
  *  Skip the .h file. Noone else need to know!
  */
@@ -210,7 +214,7 @@ LEAF(Mips10k_SyncCache, 0)
  * Sync the instruction cache.
  */
 
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, t1			# Compute end address
 	PTR_SUBU t1, 128
 
@@ -229,7 +233,7 @@ LEAF(Mips10k_SyncCache, 0)
  * the selected cache and differs from Hit in that sense.
  */
 
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, t2			# End address
 	PTR_SUBU t1, t1, 128
 1:
@@ -247,7 +251,7 @@ LEAF(Mips10k_SyncCache, 0)
 	PTR_ADDU t0, t0, 128
 
 /* Do L2 */
-	LA	t3, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
 	lw	ta0, CpuSecondaryCacheSize	# XXX Need set size here.
 10:
 	cache	IndexWBInvalidate_S, 0(t3)
@@ -314,12 +318,13 @@ END(Mips10k_InvalidateICachePage)
  *----------------------------------------------------------------------------
  */
 LEAF(Mips10k_InvalidateICache, 0)
+	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
 	and	a0, 0x00ffffff			# Reduce addr to cache index
 	PTR_ADDU a1, 63				# Round up size
 	PTR_ADDU a1, a0				# Add extra from address
 	and	a0, -64				# Align start address
 	PTR_SUBU a1, a1, a0
-	PTR_ADDU a0, XKPHYS_NONCOHERENT		# a0 now new XKPHYS address
+	PTR_ADDU a0, a2				# a0 now new XKPHYS address
 	srl	a1, a1, 6			# Number of unrolled loops
 1:
 	addu	a1, -1
@@ -354,9 +359,10 @@ END(Mips10k_InvalidateICache)
  *----------------------------------------------------------------------------
  */
 LEAF(Mips10k_SyncDCachePage, 0)
+	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
 	dsll	a0, 34
 	dsrl	a0, 34
-	PTR_ADDU a0, XKPHYS_NONCOHERENT		# a0 now new XKPHYS address
+	PTR_ADDU a0, a2				# a0 now new XKPHYS address
 	and	a0, ~PAGE_MASK			# Page align start address
 	PTR_ADDU a1, a0, PAGE_SIZE-128
 
diff --git a/sys/arch/mips64/mips64/cache_r5k.S b/sys/arch/mips64/mips64/cache_r5k.S
index 2d421c5cffa..42865600a29 100644
--- a/sys/arch/mips64/mips64/cache_r5k.S
+++ b/sys/arch/mips64/mips64/cache_r5k.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.S,v 1.18 2007/05/27 09:23:04 miod Exp $ */
+/*	$OpenBSD: cache_r5k.S,v 1.19 2007/06/18 20:25:55 miod Exp $ */
 
 /*
  * Copyright (c) 1998-2004 Opsycon AB (www.opsycon.se)
@@ -55,6 +55,10 @@
 
 	.set	mips3
 
+#define	LOAD_XKPHYS(reg, cca) \
+	li	reg, cca | 0x10; \
+	dsll	reg, reg, 59
+
 /*
  *  Skip the .h file. Noone else need to know!
  */
@@ -169,7 +173,7 @@
 LEAF(Mips5k_ConfigCache, 0)
 	.set	noreorder
 	LA	v0, 1f
-	LA	v1, XKPHYS_NC
+	LA	v1, KSEG1_BASE
 	or	v0, v1
 	jr	v0				# Switch to uncached.
 	nop
@@ -237,7 +241,7 @@ Conf5K:						# R5xxx type, check for L2 cache
 
 	mtc0	v0, COP_0_CONFIG		# Enable L2 cache
 	or	t2, CTYPE_HAS_XL2		# External L2 present.
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, ta2
 1:
 	cache	InvalidateSecondaryPage, 0(t0)
@@ -267,7 +271,7 @@ Conf52K:					# R5200 type, check for L2 cache
 
 	mtc0	v0, COP_0_CONFIG		# Enable L2 cache
 	or	t2, CTYPE_HAS_XL2		# External L2 present.
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, ta2
 1:
 	cache	InvalidateSecondaryPage, 0(t0)
@@ -308,7 +312,7 @@ Conf7K:					# RM7000, check for L2 and L3 cache
 	mtc0	v0, COP_0_CONFIG		# Enable L3 cache
 	or	t2, CTYPE_HAS_XL3
 #endif
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, ta3
 1:
 	cache	InvalidatePage_T, 0(t0)
@@ -327,7 +331,7 @@ Conf7KL2:
 	ori	v0, CF_7_SE
 
 	mtc0	v0, COP_0_CONFIG		# Enable and init L2 cache
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, ta3
 1:
 	PTR_ADDU t0, 32
@@ -335,7 +339,7 @@ Conf7KL2:
 	cache	IndexStoreTag_S, -4(t0)
 	sync
 
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, ta3
 1:
 	PTR_ADDU t0, 32
@@ -343,7 +347,7 @@ Conf7KL2:
 	lw	zero, -4(t0)
 	sync
 
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, ta3
 1:
 	PTR_ADDU t0, 32
@@ -423,7 +427,7 @@ LEAF(Mips5k_SyncCache, 0)
 	mtc0	v0, COP_0_STATUS_REG		# Disable interrupts
 #endif
 
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, t1			# Compute end address
 	PTR_SUBU t1, 128
 
@@ -441,7 +445,7 @@ LEAF(Mips5k_SyncCache, 0)
  * the selected cache and differs from Hit in that sense.
  */
 
-	LA	t0, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t0, CCA_NONCOHERENT)
 	PTR_ADDU t1, t0, t2			# End address
 	PTR_SUBU t1, t1, 128
 1:
@@ -460,7 +464,7 @@ LEAF(Mips5k_SyncCache, 0)
 	nop
 
 3:
-	LA	t3, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
 	lw	ta0, CpuSecondaryCacheSize
 10:
 	cache	IndexWBInvalidate_S, 0(t3)
@@ -476,7 +480,7 @@ LEAF(Mips5k_SyncCache, 0)
 	nop
 
 	mtc0    zero, COP_0_TAG_LO
-	LA	t3, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
 	lw	ta0, CpuSecondaryCacheSize
 21:
 	cache	InvalidateSecondaryPage, 0(t3)
@@ -492,7 +496,7 @@ LEAF(Mips5k_SyncCache, 0)
 	nop
 
 	mtc0    zero, COP_0_TAG_LO
-	LA	t3, XKPHYS_NONCOHERENT
+	LOAD_XKPHYS(t3, CCA_NONCOHERENT)
 	lw	ta0, CpuTertiaryCacheSize
 31:
 	cache	InvalidatePage_T, 0(t3)
@@ -583,11 +587,12 @@ LEAF(Mips5k_InvalidateICache, 0)
 	lw	v0, CpuNWayCache		# Cache properties
 	lw	t0, CpuPrimaryInstSetSize	# Set size
 	and	a0, 0x00ffffff			# Reduce addr to cache index
+	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
 	PTR_ADDU a1, 31				# Round up size
 	PTR_ADDU a1, a0				# Add extra from address
 	and	a0, -32				# Align start address
 	PTR_SUBU a1, a1, a0
-	PTR_ADDU a0, XKPHYS_NONCOHERENT		# a0 now new XKPHYS address
+	PTR_ADDU a0, a2				# a0 now new XKPHYS address
 	srl	a1, a1, 5			# Number of unrolled loops
 	addiu	v0, -2				# <0 1way, 0 = two, >0 four
 1:
@@ -644,14 +649,15 @@ LEAF(Mips5k_SyncDCachePage, 0)
 	li	v0, SR_DIAG_DE
 	mtc0	v0, COP_0_STATUS_REG		# Disable interrupts
 #endif
-	lw	a2, CpuPrimaryDataSetSize
+	LOAD_XKPHYS(a2, CCA_NONCOHERENT)
 	lw	v0, CpuNWayCache
 	dsll	a0, 34
 	dsrl	a0, 34
-	PTR_ADDU a0, XKPHYS_NONCOHERENT		# a0 now new XKPHYS address
+	PTR_ADDU a0, a2				# a0 now new XKPHYS address
 	and	a0, ~PAGE_MASK			# Page align start address
 	PTR_ADDU a1, a0, PAGE_SIZE-128
 	addiu	v0, -2				# <0 1way, 0 = two, >0 four
+	lw	a2, CpuPrimaryDataSetSize
 
 1:
 	bltz	v0, 3f