Fix some 64 bit address problems.

Some function names made more unique.
Other changes for the upcoming Origin 200 support.

14 files changed, 195 insertions, 97 deletions

diff --git a/sys/arch/mips64/include/arcbios.h b/sys/arch/mips64/include/arcbios.h
index 5efb4947d02..42bc74fc849 100644
--- a/sys/arch/mips64/include/arcbios.h
+++ b/sys/arch/mips64/include/arcbios.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: arcbios.h,v 1.5 2004/09/09 22:21:41 pefo Exp $	*/
+/*	$OpenBSD: arcbios.h,v 1.6 2004/10/20 12:49:15 pefo Exp $	*/
 /*-
  * Copyright (c) 1996 M. Warner Losh.  All rights reserved.
  *
@@ -320,37 +320,61 @@ typedef struct arc_calls
 #define ARC_PARAM_BLK_MAGIC	0x53435241
 #define ARC_PARAM_BLK_MAGIC_BUG	0x41524353	/* This is wrong... but req */
 
-typedef struct arc_param_blk
+typedef struct arc_param_blk_32
 {
 	u_int32_t	magic;		/* Magic Number */
 	u_int32_t	length;		/* Length of parameter block */
 	u_int16_t	version;	/* ?? */
 	u_int16_t	revision;	/* ?? */
-/**/	caddr_t		restart_block;	/* ?? */
-/**/	caddr_t		debug_block;	/* Debugging info -- unused */
-/**/	caddr_t		general_exp_vect; /* ?? */
-/**/	caddr_t		tlb_miss_exp_vect; /* ?? */
+	u_int32_t	restart_block;	/* ?? */
+	u_int32_t	debug_block;	/* Debugging info -- unused */
+	u_int32_t	general_exp_vect; /* ?? */
+	u_int32_t	tlb_miss_exp_vect; /* ?? */
 	u_int32_t	firmware_length; /* Size of Firmware jumptable in bytes */
-	arc_calls_t	*firmware_vect;	/* Firmware jumptable */
+	u_int32_t	*firmware_vect;	/* Firmware jumptable */
 	u_int32_t	vendor_length;	/* Size of Vendor specific jumptable */
-/**/	caddr_t		vendor_vect;	/* Vendor specific jumptable */
+	u_int32_t	vendor_vect;	/* Vendor specific jumptable */
 	u_int32_t	adapter_count;	/* ?? */
 	u_int32_t	adapter0_type;	/* ?? */
 	u_int32_t	adapter0_length; /* ?? */
-/**/	caddr_t		adapter0_vect;	/* ?? */
-} arc_param_blk_t;
+	u_int32_t	adapter0_vect;	/* ?? */
+} arc_param_blk_32_t;
+
+typedef struct arc_param_blk_64
+{
+	u_int64_t	magic;		/* Magic Number */
+	u_int64_t	length;		/* Length of parameter block */
+	u_int16_t	version;	/* ?? */
+	u_int16_t	revision;	/* ?? */
+	u_int64_t	restart_block;	/* ?? */
+	u_int64_t	debug_block;	/* Debugging info -- unused */
+	u_int64_t	general_exp_vect; /* ?? */
+	u_int64_t	tlb_miss_exp_vect; /* ?? */
+	u_int64_t	firmware_length; /* Size of Firmware jumptable in bytes */
+	u_int64_t	*firmware_vect;	/* Firmware jumptable */
+	u_int64_t	vendor_length;	/* Size of Vendor specific jumptable */
+	u_int64_t	vendor_vect;	/* Vendor specific jumptable */
+	u_int64_t	adapter_count;	/* ?? */
+	u_int64_t	adapter0_type;	/* ?? */
+	u_int64_t	adapter0_length; /* ?? */
+	u_int64_t	adapter0_vect;	/* ?? */
+} arc_param_blk_64_t;
 
 #ifdef _LP64
-#define ArcBiosBase ((arc_param_blk_t *) 0xffffffff80001000)
+#define ArcBiosBase32	((arc_param_blk_32_t *) 0xffffffff80001000)
+#define ArcBiosBase64	((arc_param_blk_64_t *) 0xffffffff80001000)
 #else
-#define ArcBiosBase ((arc_param_blk_t *) 0x80001000)
+#define ArcBiosBase32	((arc_param_blk_32_t *) 0x80001000)
+#define ArcBiosBase64	((arc_param_blk_64_t *) 0x80001000)
 #endif
 #define ArcBios (ArcBiosBase->firmware_vect)
 
+extern int bios_is_32bit;
 
-int  bios_getchar __P((void));
+int  bios_getchar(void);
 void bios_putchar(char);
 void bios_putstring(char *);
+void bios_printf(const char *, ...);
 void bios_ident(void);
 void bios_display_info(int *, int *, int *, int *);
 
diff --git a/sys/arch/mips64/include/asm.h b/sys/arch/mips64/include/asm.h
index 189b1931be2..e87474dfc1b 100644
--- a/sys/arch/mips64/include/asm.h
+++ b/sys/arch/mips64/include/asm.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: asm.h,v 1.6 2004/09/27 20:39:27 pefo Exp $ */
+/*	$OpenBSD: asm.h,v 1.7 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 2001-2002 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -185,7 +185,7 @@
  */
 #if defined(XGPROF) || defined(XPROF)
 #define	MCOUNT			\
-	subu	sp, sp, 32;	\
+	PTR_SUBU sp, sp, 32;	\
 	SAVE_GP(16);		\
 	sw	ra, 28(sp);	\
 	sw	gp, 24(sp);	\
@@ -193,9 +193,9 @@
 	.set	noreorder;	\
 	move	AT, ra;		\
 	jal	_mcount;	\
-	subu	sp, sp, 8;	\
+	PTR_SUBU sp, sp, 8;	\
 	lw	ra, 28(sp);	\
-	addu	sp, sp, 32;	\
+	PTR_ADDU sp, sp, 32;	\
 	.set reorder;		\
 	.set	at;
 #else
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 15b1352e2e3..942b3e722c5 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.8 2004/09/27 19:20:49 pefo Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.9 2004/10/20 12:49:15 pefo Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -422,7 +422,7 @@ extern u_int	CpuStatusRegister;
 extern u_int	CpuExternalCacheOn;	/* R5K, RM7K */
 extern u_int	CpuOnboardCacheOn;	/* RM7K */
 
-struct tlb;
+struct tlb_entry;
 struct user;
 
 void	tlb_set_wired(int);
@@ -469,9 +469,9 @@ void	Mips10k_HitInvalidateDCache(vaddr_t, int);
 
 void	tlb_flush(int);
 void	tlb_flush_addr(vaddr_t);
-void	tlb_write_indexed(int, struct tlb *);
+void	tlb_write_indexed(int, struct tlb_entry *);
 int	tlb_update(vaddr_t, unsigned);
-void	tlb_read(int, struct tlb *);
+void	tlb_read(int, struct tlb_entry *);
 
 void	wbflush(void);
 void	savectx(struct user *, int);
@@ -500,6 +500,7 @@ u_int32_t enableintr(void);
 u_int32_t disableintr(void);
 u_int32_t updateimask(intrmask_t);
 void setsr(u_int32_t);
+u_int32_t getsr(void);
 
 #endif /* _KERNEL */
 #endif /* !_MIPS_CPU_H_ */
diff --git a/sys/arch/mips64/include/cpustate.h b/sys/arch/mips64/include/cpustate.h
index db1e07f2233..3172938a733 100644
--- a/sys/arch/mips64/include/cpustate.h
+++ b/sys/arch/mips64/include/cpustate.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpustate.h,v 1.5 2004/09/10 10:38:51 miod Exp $ */
+/*	$OpenBSD: cpustate.h,v 1.6 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 2002-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -69,8 +69,8 @@
 	mfhi	v1				;\
 	mfc0	a0, COP_0_CAUSE_REG		;\
 	mfc0	a1, COP_0_STATUS_REG		;\
-	mfc0	a2, COP_0_BAD_VADDR		;\
-	mfc0	a3, COP_0_EXC_PC		;\
+	dmfc0	a2, COP_0_BAD_VADDR		;\
+	dmfc0	a3, COP_0_EXC_PC		;\
 	SAVE_REG(v0, MULLO, frame, bo)		;\
 	SAVE_REG(v1, MULHI, frame, bo)		;\
 	SAVE_REG(a0, CAUSE, frame, bo)		;\
@@ -78,7 +78,7 @@
 	SAVE_REG(a2, BADVADDR, frame, bo)	;\
 	SAVE_REG(a3, PC, frame, bo)		;\
 	SAVE_REG(sp, SP, frame, bo)		;\
-	addu	a0, frame, bo			;\
+	PTR_ADDU a0, frame, bo			;\
 	lw	a2, cpl				;\
 	SAVE_REG(a2, CPL, frame, bo)
 
diff --git a/sys/arch/mips64/include/pte.h b/sys/arch/mips64/include/pte.h
index 9491b91c676..8c6af0504e0 100644
--- a/sys/arch/mips64/include/pte.h
+++ b/sys/arch/mips64/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.1 2004/09/20 20:03:18 miod Exp $	*/
+/*	$OpenBSD: pte.h,v 1.2 2004/10/20 12:49:15 pefo Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -51,11 +51,11 @@
  * Structure defining an tlb entry data set.
  */
 
-struct tlb {
-	int	tlb_mask;
-	int	tlb_hi;
-	int	tlb_lo0;
-	int	tlb_lo1;
+struct tlb_entry {
+	u_int64_t	tlb_mask;
+	u_int64_t	tlb_hi;
+	u_int64_t	tlb_lo0;
+	u_int64_t	tlb_lo1;
 };
 
 typedef union pt_entry {
@@ -78,11 +78,18 @@ typedef union pt_entry {
 #define	PG_M		0x00000004
 #define	PG_ATTR		0x0000003f
 #define	PG_UNCACHED	0x00000010
-#define	PG_CACHED	0x00000018
+#define	PG_CACHED_NC	0x00000018	/* Cached, non coherent */
+#define	PG_CACHED_CE	0x00000020	/* Cached, coherent exclusive */
+#define	PG_CACHED_CEW	0x00000028	/* Cached, coherent exclusive write */
 #define	PG_CACHEMODE	0x00000038
+#ifdef TGT_COHERENT
+#define	PG_CACHED	PG_CACHED_CE
+#else
+#define	PG_CACHED	PG_CACHED_NC
+#endif
 #define	PG_ROPAGE	(PG_V | PG_RO | PG_CACHED) /* Write protected */
-#define	PG_RWPAGE	(PG_V | PG_M | PG_CACHED)  /* Not wr-prot not clean */
-#define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not wr-prot but clean */
+#define	PG_RWPAGE	(PG_V | PG_M | PG_CACHED)  /* Not w-prot not clean */
+#define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not w-prot but clean */
 #define	PG_IOPAGE	(PG_G | PG_V | PG_M | PG_UNCACHED)
 #define	PG_FRAME	0x3fffffc0
 #define PG_SHIFT	6
diff --git a/sys/arch/mips64/mips64/arcbios.c b/sys/arch/mips64/mips64/arcbios.c
index 50116dd22a4..1acc8aa7856 100644
--- a/sys/arch/mips64/mips64/arcbios.c
+++ b/sys/arch/mips64/mips64/arcbios.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: arcbios.c,v 1.6 2004/09/09 22:11:38 pefo Exp $	*/
+/*	$OpenBSD: arcbios.c,v 1.7 2004/10/20 12:49:15 pefo Exp $	*/
 /*-
  * Copyright (c) 1996 M. Warner Losh.  All rights reserved.
  * Copyright (c) 1996-2004 Opsycon AB.  All rights reserved.
@@ -37,7 +37,11 @@
 #include <mips64/arcbios.h>
 #include <mips64/archtype.h>
 
-arc_param_blk_t *bios_base = ArcBiosBase;
+#if defined(TGT_ORIGIN200) || defined(TGT_ORIGIN2000)
+#include <machine/mnode.h>
+#endif
+
+int bios_is_32bit = 1;
 
 extern int	physmem;		/* Total physical memory size */
 extern int	rsvdmem;		/* Total reserved memory size */
@@ -65,6 +69,7 @@ static struct systypes {
     { NULL,		"SGI-IP22",			SGI_INDY },
     { NULL,		"SGI-IP25",			SGI_POWER10 },
     { NULL,		"SGI-IP26",			SGI_POWERI },
+    { NULL,		"SGI-IP27",			SGI_O200 },
     { NULL,		"SGI-IP32",			SGI_O2 },
 };
 
@@ -81,8 +86,16 @@ __asm__("\n"			\
 "	.set	noreorder\n"	\
 "	.globl	" #Name "\n"	\
 #Name":\n"			\
-"	lw	$2, 0xffffffff80001020\n"\
-"	lw	$2," #Offset "($2)\n"\
+"	lw	$2, bios_is_32bit\n"\
+"	beqz	$2, 1f\n"	\
+"	nop\n"			\
+"       lw      $2, 0xffffffff80001020\n"\
+"       lw      $2," #Offset "($2)\n"\
+"	jr	$2\n"		\
+"	nop\n"			\
+"1:\n"				\
+"       ld      $2, 0xffffffff80001040\n"\
+"	ld	$2, 2*" #Offset "($2)\n"\
 "	jr	$2\n"		\
 "	nop\n"			\
 "	.end	" #Name "\n"	);
@@ -170,6 +183,17 @@ char *s;
 	}
 }
 
+void
+bios_printf(const char *fmt, ...)
+{
+	va_list ap;
+	char buf[1024];
+
+	va_start(ap, fmt);
+	vsnprintf(buf, sizeof(buf), fmt, ap);
+	bios_putstring(buf);
+}
+
 /*
  * Get memory descriptor for the memory configuration and
  * create a layout database used by pmap init to set up
@@ -240,12 +264,10 @@ bios_configure_memory()
 
 #ifdef DEBUG_MEM_LAYOUT
 	for ( i = 0; i < MAXMEMSEGS; i++) {
-		char str[100];
 		if (mem_layout[i].mem_first_page) {
-			snprintf(str, sizeof(str), "MEM %d, 0x%x to  0x%x\n",i,
+			bios_printf("MEM %d, 0x%x to  0x%x\n",i,
 				mem_layout[i].mem_first_page * 4096,
 				mem_layout[i].mem_last_page * 4096);
-			bios_putstring(str);
 	    }
 	}
 #endif
@@ -261,12 +283,25 @@ bios_get_system_type()
 	arc_sid_t	*sid;
 	int		i;
 
-	if ((bios_base->magic != ARC_PARAM_BLK_MAGIC) &&
-	    (bios_base->magic != ARC_PARAM_BLK_MAGIC_BUG)) {
-		return(-1);	/* This is not an ARC system */
+	/*
+	 *  Figure out if this is an ARC Bios machine and if its 32 or 64 bits.
+	 */
+	if ((ArcBiosBase32->magic == ARC_PARAM_BLK_MAGIC) ||
+	    (ArcBiosBase32->magic == ARC_PARAM_BLK_MAGIC_BUG)) {
+		bios_is_32bit = 1;
+		bios_printf("ARCS32 Firmware Version %d.%d\n",
+		    ArcBiosBase32->version, ArcBiosBase32->revision);
+	} else if ((ArcBiosBase64->magic == ARC_PARAM_BLK_MAGIC) ||
+	    (ArcBiosBase64->magic == ARC_PARAM_BLK_MAGIC_BUG)) {
+		bios_is_32bit = 0;
+		bios_printf("ARCS64 Firmware Version %d.%d\n",
+		    ArcBiosBase64->version, ArcBiosBase64->revision);
+	} else {
+		return -1;	/* XXX BAD BAD BAD!!! */
 	}
 
 	sid = (arc_sid_t *)Bios_GetSystemId();
+
 	cf = (arc_config_t *)Bios_GetChild(NULL);
 	if (cf) {
 		for (i = 0; i < KNOWNSYSTEMS; i++) {
@@ -277,18 +312,21 @@ bios_get_system_type()
 				continue;
 			return (sys_types[i].sys_type);	/* Found it. */
 		}
+#if defined(TGT_ORIGIN200) || defined(TGT_ORIGIN2000)
+	} else if (IP27_KLD_KLCONFIG(0)->magic == IP27_KLDIR_MAGIC) {
+		/* If we find a kldir assume IP27 */
+		return SGI_O200;
+#endif
 	}
 
-	bios_putstring("UNIDENTIFIED SYSTEM `");
-	if (cf)
-		bios_putstring((char *)(long)cf->id);
-	else
-		bios_putstring("????????");
-	bios_putstring("' VENDOR `");
 	sid->vendor[8] = 0;
-	bios_putstring(sid->vendor);
-	bios_putstring("'. Please contact OpenBSD (www.openbsd.org).\n");
-	bios_putstring("Reset system to restart!\n");
+	sid->prodid[8] = 0;
+	bios_printf("UNRECOGNIZED SYSTEM '%s' VENDOR '%s' PRODUCT '%s'\n",
+		cf ? (char *)(long)cf->id : "??", sid->vendor, sid->prodid);
+	bios_printf("See the www.openbsd.org for further information.\n");
+	bios_printf("Halting system!\n");
+	Bios_Halt();
+	bios_printf("Halting failed, use manual reset!\n");
 	while(1);
 }
 
@@ -299,9 +337,10 @@ void
 bios_ident()
 {
 	sys_config.system_type = bios_get_system_type();
-	if (sys_config.system_type < 0) {
+	if (sys_config.system_type < 0 || sys_config.system_type == SGI_O200) {
 		return;
 	}
+	/* If not an IP27 platform, get memory configuration from bios */
 	bios_configure_memory();
 #ifdef __arc__
 	displayinfo = *(arc_dsp_stat_t *)Bios_GetDisplayStatus(1);
diff --git a/sys/arch/mips64/mips64/clock.c b/sys/arch/mips64/mips64/clock.c
index 43584de1bbc..b15f58d27f1 100644
--- a/sys/arch/mips64/mips64/clock.c
+++ b/sys/arch/mips64/mips64/clock.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: clock.c,v 1.8 2004/09/24 14:22:49 deraadt Exp $ */
+/*	$OpenBSD: clock.c,v 1.9 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -103,6 +103,7 @@ clockattach(struct device *parent, struct device *self, void *aux)
 	case GALILEO_EV64240:
 	case SGI_INDY:
 	case SGI_O2:
+	case SGI_O200:
 		printf(" ticker on int5 using count register.");
 		set_intr(INTPRI_CLOCK, CR_INT_5, clock_int5);
 		ticktime = sys_config.cpu[0].clock / 2000;
@@ -110,7 +111,6 @@ clockattach(struct device *parent, struct device *self, void *aux)
 
 	default:
 		panic("clockattach: it didn't get here.  really.");
-		clock_int5(0,(struct trap_frame *)NULL);
 	}
 
 	printf("\n");
@@ -176,6 +176,13 @@ clock_int5( intrmask_t mask, struct trap_frame *tf)
 	}
 
 	cp0_set_compare(cpu_counter_last);
+	/* Make sure that next clock tick has not passed */
+	clkdiff = cp0_get_count() - cpu_counter_last;
+	if (clkdiff > 0) {
+		cpu_counter_last += cpu_counter_interval;
+		pendingticks++;
+		cp0_set_compare(cpu_counter_last);
+	}
 
 	if ((tf->cpl & SPL_CLOCKMASK) == 0) {
 		while (pendingticks) {
diff --git a/sys/arch/mips64/mips64/cp0access.S b/sys/arch/mips64/mips64/cp0access.S
index c3ef5472dd9..5123f6a2137 100644
--- a/sys/arch/mips64/mips64/cp0access.S
+++ b/sys/arch/mips64/mips64/cp0access.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cp0access.S,v 1.4 2004/09/10 08:58:27 pefo Exp $ */
+/*	$OpenBSD: cp0access.S,v 1.5 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -166,6 +166,12 @@ LEAF(setsr, 0)
 	move	v0, a0
 END(setsr)
 
+LEAF(getsr, 0)
+	mfc0	v0, COP_0_STATUS_REG
+	jr	ra
+	nop
+END(getsr)
+
 LEAF(cp0_get_prid, 0)
 	mfc0	v0, COP_0_PRID
 	j	ra
diff --git a/sys/arch/mips64/mips64/db_machdep.c b/sys/arch/mips64/mips64/db_machdep.c
index 83bf04ec2b6..dd6ec07ac3c 100644
--- a/sys/arch/mips64/mips64/db_machdep.c
+++ b/sys/arch/mips64/mips64/db_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: db_machdep.c,v 1.6 2004/09/15 16:05:18 pefo Exp $ */
+/*	$OpenBSD: db_machdep.c,v 1.7 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 1998-2003 Opsycon AB (www.opsycon.se)
@@ -562,9 +562,9 @@ void
 db_dump_tlb_cmd(db_expr_t addr, int have_addr, db_expr_t count, char *m)
 {
 	int tlbno, last, check, pid;
-	struct tlb tlb, tlbp;
+	struct tlb_entry tlb, tlbp;
 char *attr[] = {
-	"CWTNA", "CWTA ", "UCBL ", "CWB  ", "RES  ", "RES  ", "UCNB ", "BPASS"
+	"WTNA", "WTA ", "UCBL", "CWB ", "RES ", "RES ", "UCNB", "BPAS"
 };
 
 	pid = -1;
@@ -609,23 +609,23 @@ if ((tlbp.tlb_hi == tlb.tlb_hi && (tlb.tlb_lo0 & PG_V || tlb.tlb_lo1 & PG_V)) ||
 			continue;
 
 		if (tlb.tlb_lo0 & PG_V || tlb.tlb_lo1 & PG_V) {
-			printf("%2d v=0x%08x", tlbno, tlb.tlb_hi & ~0xff);
+			printf("%2d v=%16llx", tlbno, tlb.tlb_hi & (long)~0xff);
 			printf("/%02x ", tlb.tlb_hi & 0xff);
 
 			if (tlb.tlb_lo0 & PG_V) {
-				printf("0x%08x ", pfn_to_pad(tlb.tlb_lo0));
+				printf("%16llx ", pfn_to_pad(tlb.tlb_lo0));
 				printf("%c", tlb.tlb_lo0 & PG_M ? 'M' : ' ');
 				printf("%c", tlb.tlb_lo0 & PG_G ? 'G' : ' ');
-				printf(" %s ", attr[(tlb.tlb_lo0 >> 3) & 7]);
+				printf("%s ", attr[(tlb.tlb_lo0 >> 3) & 7]);
 			} else {
 				printf("invalid             ");
 			}
 
 			if (tlb.tlb_lo1 & PG_V) {
-				printf("0x%08x ", pfn_to_pad(tlb.tlb_lo1));
+				printf("%16llx ", pfn_to_pad(tlb.tlb_lo1));
 				printf("%c", tlb.tlb_lo1 & PG_M ? 'M' : ' ');
 				printf("%c", tlb.tlb_lo1 & PG_G ? 'G' : ' ');
-				printf(" %s ", attr[(tlb.tlb_lo1 >> 3) & 7]);
+				printf("%s ", attr[(tlb.tlb_lo1 >> 3) & 7]);
 			} else {
 				printf("invalid             ");
 			}
diff --git a/sys/arch/mips64/mips64/lcore_access.S b/sys/arch/mips64/mips64/lcore_access.S
index b1e45a3a211..3e74b2b1117 100644
--- a/sys/arch/mips64/mips64/lcore_access.S
+++ b/sys/arch/mips64/mips64/lcore_access.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: lcore_access.S,v 1.7 2004/09/27 19:16:06 pefo Exp $ */
+/*	$OpenBSD: lcore_access.S,v 1.8 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -212,10 +212,10 @@ END(fillw)
 LEAF(mem_zero_page, 0)
 	LI	v0, NBPG
 1:
-	dsubu	v0, 8
+	PTR_SUBU v0, 8
 	sd	zero, 0(a0)
 	bne	zero, v0, 1b
-	daddu	a0, 8
+	PTR_ADDU a0, 8
 	jr	ra
 	nop
 END(mem_zero_page)
diff --git a/sys/arch/mips64/mips64/lcore_float.S b/sys/arch/mips64/mips64/lcore_float.S
index 482e7085857..e6975130293 100644
--- a/sys/arch/mips64/mips64/lcore_float.S
+++ b/sys/arch/mips64/mips64/lcore_float.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: lcore_float.S,v 1.7 2004/09/27 19:16:06 pefo Exp $ */
+/*	$OpenBSD: lcore_float.S,v 1.8 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -468,7 +468,7 @@ NON_LEAF(MipsFPTrap, FRAMESZ(CF_SZ), ra)
  */
 1:
 	lw	a0, 0(a2)			# a0 = coproc instruction
-	addu	v0, a2, 4			# v0 = next pc
+	PTR_ADDU v0, a2, 4			# v0 = next pc
 2:
 	PTR_L	a3, curprocpaddr		# first arg is ptr to CPU regs
 	PTR_S	v0, U_PCB_REGS+(PC * REGSZ)(a3)	# save new pc
diff --git a/sys/arch/mips64/mips64/pmap.c b/sys/arch/mips64/mips64/pmap.c
index cc66f74e91b..28d0f5a62d3 100644
--- a/sys/arch/mips64/mips64/pmap.c
+++ b/sys/arch/mips64/mips64/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.16 2004/09/30 07:25:54 pefo Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.17 2004/10/20 12:49:15 pefo Exp $	*/
 
 /*
  * Copyright (c) 2001-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -111,7 +111,7 @@ struct {
 		printf printdata;
 
 #define stat_count(what)	(what)++
-int pmapdebug = 0x0;
+int pmapdebug = PDB_ENTER|PDB_FOLLOW;
 
 #else
 
diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S
index 75858063644..73fb61c0a50 100644
--- a/sys/arch/mips64/mips64/tlbhandler.S
+++ b/sys/arch/mips64/mips64/tlbhandler.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tlbhandler.S,v 1.9 2004/09/27 20:39:27 pefo Exp $ */
+/*	$OpenBSD: tlbhandler.S,v 1.10 2004/10/20 12:49:15 pefo Exp $ */
 
 /*
  * Copyright (c) 1995-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -183,7 +183,8 @@ tlb_miss_nopt:
 	.globl	tlb_miss_tramp
 tlb_miss_tramp:
 	.set	noat
-	j	tlb_miss
+	LA	k0, tlb_miss
+	jr	k0
 	nop
 	.set	at
 	.globl	e_tlb_miss_tramp
@@ -192,7 +193,8 @@ e_tlb_miss_tramp:
 	.globl	xtlb_miss_tramp
 xtlb_miss_tramp:
 	.set	noat
-	j	xtlb_miss
+	LA	k0, xtlb_miss
+	jr	k0
 	nop
 	.set	at
 	.globl	e_xtlb_miss_tramp
@@ -376,16 +378,18 @@ END(k_tlb_miss)
  */
 LEAF(tlb_write_indexed, 0)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
+	ori	v0, v1, SR_INT_ENAB
+	xori	v0, v0, SR_INT_ENAB
+	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
 	ITLBNOPFIX
-	lw	a2, 8(a1)
-	lw	a3, 12(a1)
+	ld	a2, 16(a1)
+	ld	a3, 24(a1)
 	dmfc0	ta0, COP_0_TLB_HI		# Save the current PID.
 
 	dmtc0	a2, COP_0_TLB_LO0		# Set up entry low0.
 	dmtc0	a3, COP_0_TLB_LO1		# Set up entry low1.
-	lw	a2, 0(a1)
-	lw	a3, 4(a1)
+	ld	a2, 0(a1)
+	ld	a3, 8(a1)
 	mtc0	a0, COP_0_TLB_INDEX	# Set the index.
 	dmtc0	a2, COP_0_TLB_PG_MASK	# Set up entry mask.
 	dmtc0	a3, COP_0_TLB_HI		# Set up entry high.
@@ -415,7 +419,9 @@ END(tlb_write_indexed)
  */
 LEAF(tlb_flush, 0)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
+	ori	v0, v1, SR_INT_ENAB
+	xori	v0, v0, SR_INT_ENAB
+	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
 	ITLBNOPFIX
 	mfc0	ta1, COP_0_TLB_WIRED
 	LA	v0, KSEG0_BASE		# invalid address
@@ -452,7 +458,9 @@ END(tlb_flush)
  */
 LEAF(tlb_flush_addr, 0)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
+	ori	v0, v1, SR_INT_ENAB
+	xori	v0, v0, SR_INT_ENAB
+	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
 	ITLBNOPFIX
 	li	v0, (PG_HVPN | PG_ASID)
 	and	a0, a0, v0		# Make shure valid hi value.
@@ -496,7 +504,9 @@ END(tlb_flush_addr)
  */
 LEAF(tlb_update, 0)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
+	ori	v0, v1, SR_INT_ENAB
+	xori	v0, v0, SR_INT_ENAB
+	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
 	ITLBNOPFIX
 	and	ta1, a0, 0x1000		# ta1 = Even/Odd flag
 	li	v0, (PG_HVPN | PG_ASID)
@@ -586,7 +596,9 @@ END(tlb_update)
  */
 LEAF(tlb_read, 0)
 	mfc0	v1, COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, COP_0_STATUS_REG	# Disable interrupts
+	ori	v0, v1, SR_INT_ENAB
+	xori	v0, v0, SR_INT_ENAB
+	mtc0	v0, COP_0_STATUS_REG	# Disable interrupts
 	ITLBNOPFIX
 	dmfc0	v0, COP_0_TLB_HI	# Get current PID
 
@@ -599,7 +611,7 @@ LEAF(tlb_read, 0)
 	nop
 	nop
 	nop
-	mfc0	ta0, COP_0_TLB_PG_MASK	# fetch the hi entry
+	dmfc0	ta0, COP_0_TLB_PG_MASK	# fetch the hi entry
 	dmfc0	ta1, COP_0_TLB_HI	# fetch the hi entry
 	dmfc0	ta2, COP_0_TLB_LO0	# See what we got
 	dmfc0	ta3, COP_0_TLB_LO1	# See what we got
@@ -609,11 +621,11 @@ LEAF(tlb_read, 0)
 	nop				# wait for PID active
 	mtc0	v1, COP_0_STATUS_REG	# Restore the status register
 	ITLBNOPFIX
-	sw	ta0, 0(a1)
-	sw	ta1, 4(a1)
-	sw	ta2, 8(a1)
+	sd	ta0, 0(a1)
+	sd	ta1, 8(a1)
+	sd	ta2, 16(a1)
 	j	ra
-	sw	ta3, 12(a1)
+	sd	ta3, 24(a1)
 END(tlb_read)
 
 /*---------------------------------------------------------------- tlb_get_pid
diff --git a/sys/arch/mips64/mips64/trap.c b/sys/arch/mips64/mips64/trap.c
index f752c296b5d..9fd8a96f493 100644
--- a/sys/arch/mips64/mips64/trap.c
+++ b/sys/arch/mips64/mips64/trap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.c,v 1.13 2004/10/08 07:45:15 grange Exp $	*/
+/*	$OpenBSD: trap.c,v 1.14 2004/10/20 12:49:15 pefo Exp $	*/
 /* tracked to 1.23 */
 
 /*
@@ -849,27 +849,29 @@ void
 trapDump(msg)
 	char *msg;
 {
+	struct trapdebug *ptrp;
 	int i;
 	int s;
 
 	s = splhigh();
+	ptrp = trp;
 	printf("trapDump(%s)\n", msg);
 	for (i = 0; i < TRAPSIZE; i++) {
-		if (trp == trapdebug) {
-			trp = &trapdebug[TRAPSIZE - 1];
+		if (ptrp == trapdebug) {
+			ptrp = &trapdebug[TRAPSIZE - 1];
 		}
 		else {
-			trp--;
+			ptrp--;
 		}
 
-		if (trp->cause == 0)
+		if (ptrp->cause == 0)
 			break;
 
 		printf("%s: PC %p CR 0x%x SR 0x%x\n",
-		    trap_type[(trp->cause & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT],
-		    trp->pc, trp->cause, trp->status);
+		    trap_type[(ptrp->cause & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT],
+		    ptrp->pc, ptrp->cause, ptrp->status);
 
-		printf("  RA %p SP %p ADR %p\n", trp->ra, trp->sp, trp->vadr);
+		printf(" RA %p SP %p ADR %p\n", ptrp->ra, ptrp->sp, ptrp->vadr);
 	}
 
 #ifdef TLBTRACE