Add processor IDs for several OCTEON II and III SoCs.

3 files changed, 29 insertions, 3 deletions

diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index 28d81151a4d..d76f14dbad8 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.124 2018/02/24 11:42:31 visa Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.125 2018/12/04 16:24:13 visa Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -402,7 +402,11 @@ void	cp0_calibrate(struct cpu_info *);
 #define	MIPS_LOONGSON	0x42	/* STC LoongSon CPU		ISA III */
 #define	MIPS_VR5400	0x54	/* NEC Vr5400 CPU		ISA IV+ */
 #define	MIPS_LOONGSON2	0x63	/* STC LoongSon2/3 CPU		ISA III+ */
+#define	MIPS_CN63XX	0x90	/* Cavium OCTEON II CN6[23]xx	MIPS64R2 */
+#define	MIPS_CN68XX	0x91	/* Cavium OCTEON II CN68xx	MIPS64R2 */
+#define	MIPS_CN66XX	0x92	/* Cavium OCTEON II CN66xx	MIPS64R2 */
 #define	MIPS_CN61XX	0x93	/* Cavium OCTEON II CN6[01]xx	MIPS64R2 */
+#define	MIPS_CN78XX	0x95	/* Cavium OCTEON III CN7[678]xx	MIPS64R2 */
 #define	MIPS_CN71XX	0x96	/* Cavium OCTEON III CN7[01]xx	MIPS64R2 */
 #define	MIPS_CN73XX	0x97	/* Cavium OCTEON III CN7[23]xx	MIPS64R2 */
 
diff --git a/sys/arch/mips64/mips64/cache_octeon.c b/sys/arch/mips64/mips64/cache_octeon.c
index 2e65a3785b3..d93179cd48f 100644
--- a/sys/arch/mips64/mips64/cache_octeon.c
+++ b/sys/arch/mips64/mips64/cache_octeon.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_octeon.c,v 1.12 2017/10/11 14:24:12 visa Exp $	*/
+/*	$OpenBSD: cache_octeon.c,v 1.13 2018/12/04 16:24:13 visa Exp $	*/
 /*
  * Copyright (c) 2010 Takuya ASADA.
  *
@@ -93,6 +93,9 @@ Octeon_ConfigCache(struct cpu_info *ci)
 		break;
 
 	case MIPS_CN61XX:
+	case MIPS_CN63XX:
+	case MIPS_CN66XX:
+	case MIPS_CN68XX:
 		/* OCTEON II */
 
 		ci->ci_l1inst.linesize = 128;
@@ -109,6 +112,7 @@ Octeon_ConfigCache(struct cpu_info *ci)
 
 	case MIPS_CN71XX:
 	case MIPS_CN73XX:
+	case MIPS_CN78XX:
 		/* OCTEON III */
 
 		ci->ci_l1inst.linesize = 128;
diff --git a/sys/arch/mips64/mips64/cpu.c b/sys/arch/mips64/mips64/cpu.c
index d24265b5bc1..bff7de1b5a5 100644
--- a/sys/arch/mips64/mips64/cpu.c
+++ b/sys/arch/mips64/mips64/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.69 2017/09/02 15:56:29 visa Exp $ */
+/*	$OpenBSD: cpu.c,v 1.70 2018/12/04 16:24:13 visa Exp $ */
 
 /*
  * Copyright (c) 1997-2004 Opsycon AB (www.opsycon.se)
@@ -231,12 +231,27 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 			printf("CN61xx CPU");
 		fptype = MIPS_SOFT;
 		break;
+	case MIPS_CN63XX:
+		printf("CN62xx/CN63xx CPU");
+		fptype = MIPS_SOFT;
+		break;
+	case MIPS_CN66XX:
+		printf("CN66xx CPU");
+		fptype = MIPS_SOFT;
+		break;
+	case MIPS_CN68XX:
+		printf("CN68xx CPU");
+		fptype = MIPS_SOFT;
+		break;
 	case MIPS_CN71XX:
 		printf("CN70xx/CN71xx CPU");
 		break;
 	case MIPS_CN73XX:
 		printf("CN72xx/CN73xx CPU");
 		break;
+	case MIPS_CN78XX:
+		printf("CN76xx/CN77xx/CN78xx CPU");
+		break;
 	default:
 		printf("Unknown CPU type (0x%x)", ch->type);
 		break;
@@ -328,6 +343,9 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 	case MIPS_CN73XX:
 		printf("CN72xx/CN73xx FPU");
 		break;
+	case MIPS_CN78XX:
+		printf("CN76xx/CN77xx/CN78xx FPU");
+		break;
 	default:
 		printf("Unknown FPU type (0x%x)", fptype);
 		break;