Get rid of duplicate definitions with <m68k/cpu.h>

1 files changed, 30 insertions, 98 deletions

diff --git a/sys/arch/mvme68k/include/cpu.h b/sys/arch/mvme68k/include/cpu.h
index 6c0c985301a..a2bb05dc8b8 100644
--- a/sys/arch/mvme68k/include/cpu.h
+++ b/sys/arch/mvme68k/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.8 2002/03/14 01:26:37 millert Exp $ */
+/*	$OpenBSD: cpu.h,v 1.9 2002/04/21 23:43:40 miod Exp $ */
 
 /*
  * Copyright (c) 1995 Theo de Raadt
@@ -75,13 +75,34 @@
 #define _MVME68K_CPU_H_
 
 /*
- * Exported definitions unique to mvme68k/68k cpu support.
+ * Exported definitions unique to mvme68k cpu support.
  */
 
+/*
+ * CTL_MACHDEP definitions.
+ */
+#define	CPU_CONSDEV		1	/* dev_t: console terminal device */
+#define	CPU_MAXID		2	/* number of valid machdep ids */
+
+#define CTL_MACHDEP_NAMES { \
+	{ 0, 0 }, \
+	{ "console_device", CTLTYPE_STRUCT }, \
+}
+
+#ifdef	_KERNEL
+
+/*
+ * Get common m68k CPU definiti÷ns.
+ */
 #define M68K_MMU_MOTOROLA
 #include <m68k/cpu.h>
 
 /*
+ * Get interrupt glue.
+ */
+#include <machine/intr.h>
+
+/*
  * definitions of cpu-dependent requirements
  * referenced in generic code
  */
@@ -116,7 +137,8 @@ struct clockframe {
  * Preempt the current process if in interrupt from user mode,
  * or after the current trap/syscall if in system mode.
  */
-#define	need_resched()	{ want_resched++; aston(); }
+extern int want_resched;
+#define	need_resched()	{ want_resched = 1; aston(); }
 
 /*
  * Give a profiling tick to the current process when the user profiling
@@ -131,43 +153,12 @@ struct clockframe {
  */
 #define	signotify(p)	aston()
 
-#define aston() (astpending++)
-
-int	astpending;		/* need to trap before returning to user mode */
-int	want_resched;		/* resched() was called */
+extern int astpending;
+#define aston() (astpending = 1)
 
-/*
- * Get interrupt glue.
- */
-#include <machine/intr.h>
-
-/*
- * CTL_MACHDEP definitions.
- */
-#define	CPU_CONSDEV		1	/* dev_t: console terminal device */
-#define	CPU_MAXID		2	/* number of valid machdep ids */
-
-#define CTL_MACHDEP_NAMES { \
-	{ 0, 0 }, \
-	{ "console_device", CTLTYPE_STRUCT }, \
-}
-
-/* values for mmutype (assigned for quick testing) */
-#define	MMU_68040	-2	/* 68040 on-chip MMU */
-#define	MMU_68030	-1	/* 68030 on-chip subset of 68851 */
-#define	MMU_68851	1	/* Motorola 68851 */
-
-/* values for ectype */
-#define	EC_PHYS		-1	/* external physical address cache */
-#define	EC_NONE		0	/* no external cache */
-#define	EC_VIRT		1	/* external virtual address cache */
-
-#ifdef _KERNEL
-extern	int mmutype, ectype;
 extern	char *intiobase, *intiolimit;
 extern	char *iiomapbase;
 extern	int iiomapsize;
-#endif
 
 /* physical memory sections for mvme147 */
 #define	INTIOBASE_147	(0xfffe0000)
@@ -192,67 +183,6 @@ extern	int iiomapsize;
 #define	IIOP(va)	((int)(va)-(int)intiobase+(int)iiomapbase)
 #define	IIOPOFF(pa)	((int)(pa)-(int)iiomapbase)
 
-/*
- * 68851 and 68030 MMU
- */
-#define	PMMU_LVLMASK	0x0007
-#define	PMMU_INV	0x0400
-#define	PMMU_WP		0x0800
-#define	PMMU_ALV	0x1000
-#define	PMMU_SO		0x2000
-#define	PMMU_LV		0x4000
-#define	PMMU_BE		0x8000
-#define	PMMU_FAULT	(PMMU_WP|PMMU_INV)
-
-/*
- * 68040 MMU
- */
-#define	MMU4_RES	0x001
-#define	MMU4_TTR	0x002
-#define	MMU4_WP		0x004
-#define	MMU4_MOD	0x010
-#define	MMU4_CMMASK	0x060
-#define	MMU4_SUP	0x080
-#define	MMU4_U0		0x100
-#define	MMU4_U1		0x200
-#define	MMU4_GLB	0x400
-#define	MMU4_BE		0x800
-
-/* 680X0 function codes */
-#define	FC_USERD	1	/* user data space */
-#define	FC_USERP	2	/* user program space */
-#define	FC_SUPERD	5	/* supervisor data space */
-#define	FC_SUPERP	6	/* supervisor program space */
-#define	FC_CPU		7	/* CPU space */
-
-/* fields in the 68020 cache control register */
-#define	IC_ENABLE	0x0001	/* enable instruction cache */
-#define	IC_FREEZE	0x0002	/* freeze instruction cache */
-#define	IC_CE		0x0004	/* clear instruction cache entry */
-#define	IC_CLR		0x0008	/* clear entire instruction cache */
-
-/* additional fields in the 68030 cache control register */
-#define	IC_BE		0x0010	/* instruction burst enable */
-#define	DC_ENABLE	0x0100	/* data cache enable */
-#define	DC_FREEZE	0x0200	/* data cache freeze */
-#define	DC_CE		0x0400	/* clear data cache entry */
-#define	DC_CLR		0x0800	/* clear entire data cache */
-#define	DC_BE		0x1000	/* data burst enable */
-#define	DC_WA		0x2000	/* write allocate */
-
-#define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
-#define	CACHE_OFF	(DC_CLR|IC_CLR)
-#define	CACHE_CLR	(CACHE_ON)
-#define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
-#define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
-
-/* 68040 cache control register */
-#define	IC4_ENABLE	0x00008000	/* instruction cache enable bit */
-#define	DC4_ENABLE	0x80000000	/* data cache enable bit */
-
-#define	CACHE4_ON	(IC4_ENABLE|DC4_ENABLE)
-#define	CACHE4_OFF	(0)
-
 extern int	cputyp;
 #define CPU_147			0x147
 #define CPU_162			0x162
@@ -274,4 +204,6 @@ struct haltvec {
 	void	(*hv_fn)(void);
 	int	hv_pri;
 };
-#endif
+
+#endif	/* _KERNEL */
+#endif	/* _MVME68K_CPU_H_ */