be consistant on Hz vs hz

5 files changed, 17 insertions, 17 deletions

diff --git a/sys/arch/mvme68k/dev/sbic.c b/sys/arch/mvme68k/dev/sbic.c
index 5a30ca3e007..6df0819013b 100644
--- a/sys/arch/mvme68k/dev/sbic.c
+++ b/sys/arch/mvme68k/dev/sbic.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sbic.c,v 1.11 2002/04/27 23:21:05 miod Exp $ */
+/*	$OpenBSD: sbic.c,v 1.12 2003/02/11 19:20:26 mickey Exp $ */
 /*	$NetBSD: sbic.c,v 1.2 1996/04/23 16:32:54 chuck Exp $	*/
 
 /*
@@ -2621,7 +2621,7 @@ sbictoscsiperiod(dev, a)
     /*
      * cycle = DIV / (2 * CLK)
      * DIV = FS + 2
-     * best we can do is 200ns at 20Mhz, 2 cycles
+     * best we can do is 200ns at 20MHz, 2 cycles
      */
 
     GET_SBIC_myid(dev->sc_sbicp, fs);
diff --git a/sys/arch/mvme68k/dev/sbicreg.h b/sys/arch/mvme68k/dev/sbicreg.h
index 8b8f359648c..b7e76e632b3 100644
--- a/sys/arch/mvme68k/dev/sbicreg.h
+++ b/sys/arch/mvme68k/dev/sbicreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sbicreg.h,v 1.4 2002/07/10 20:30:14 jsyn Exp $ */
+/*	$OpenBSD: sbicreg.h,v 1.5 2003/02/11 19:20:26 mickey Exp $ */
 
 /*
  * Copyright (c) 1990 The Regents of the University of California.
@@ -105,10 +105,10 @@
  * My ID register, and/or CDB Size
  */
 
-#define SBIC_ID_FS_8_10         0x00    /* Input clock is  8-10 Mhz */
-                                    /* 11 Mhz is invalid */
-#define SBIC_ID_FS_12_15        0x40    /* Input clock is 12-15 Mhz */
-#define SBIC_ID_FS_16_20        0x80    /* Input clock is 16-20 Mhz */
+#define SBIC_ID_FS_8_10         0x00    /* Input clock is  8-10 MHz */
+                                    /* 11 MHz is invalid */
+#define SBIC_ID_FS_12_15        0x40    /* Input clock is 12-15 MHz */
+#define SBIC_ID_FS_16_20        0x80    /* Input clock is 16-20 MHz */
 #define SBIC_ID_EHP             0x10    /* Enable host parity */
 #define SBIC_ID_EAF             0x08    /* Enable Advanced Features */
 #define SBIC_ID_MASK            0x07
@@ -130,7 +130,7 @@
 
 /*
  * Timeout period register
- * [val in msecs, input clk in 0.1 Mhz]
+ * [val in msecs, input clk in 0.1 MHz]
  */
 
 #define SBIC_TIMEOUT(val,clk)   ((((val) * (clk)) / 800) + 1)
diff --git a/sys/arch/mvme68k/dev/ssh.c b/sys/arch/mvme68k/dev/ssh.c
index 1b835d3e5b7..76da2ca9579 100644
--- a/sys/arch/mvme68k/dev/ssh.c
+++ b/sys/arch/mvme68k/dev/ssh.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ssh.c,v 1.3 2002/04/27 23:21:05 miod Exp $ */
+/*	$OpenBSD: ssh.c,v 1.4 2003/02/11 19:20:26 mickey Exp $ */
 
 /*
  * Copyright (c) 1994 Michael L. Hitch
@@ -1418,7 +1418,7 @@ sshintr(sc)
 }
 
 /*
- * This is based on the Progressive Peripherals 33Mhz Zeus driver and will
+ * This is based on the Progressive Peripherals 33MHz Zeus driver and will
  * not be correct for other 53c710 boards.
  *
  */
diff --git a/sys/arch/mvme68k/dev/sshdma.c b/sys/arch/mvme68k/dev/sshdma.c
index cf075cd58f5..32e2d098d2b 100644
--- a/sys/arch/mvme68k/dev/sshdma.c
+++ b/sys/arch/mvme68k/dev/sshdma.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sshdma.c,v 1.5 2002/09/17 21:54:56 miod Exp $ */
+/*	$OpenBSD: sshdma.c,v 1.6 2003/02/11 19:20:26 mickey Exp $ */
 
 /*
  * Copyright (c) 1995 Theo de Raadt
@@ -116,7 +116,7 @@ void *auxp;
 	 */
 	sc->sc_clock_freq = cpuspeed * 2;
 #ifdef MVME177
-	/* MVME177 ssh clock documented as fixed 50Mhz in VME177A/HX */
+	/* MVME177 ssh clock documented as fixed 50MHz in VME177A/HX */
 	if (cputyp == CPU_177)
 		sc->sc_clock_freq = 50;
 #endif
diff --git a/sys/arch/mvme68k/dev/sshreg.h b/sys/arch/mvme68k/dev/sshreg.h
index 9c4527f3ba3..cd64f7d0eb1 100644
--- a/sys/arch/mvme68k/dev/sshreg.h
+++ b/sys/arch/mvme68k/dev/sshreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sshreg.h,v 1.2 2002/04/21 23:44:29 miod Exp $ */
+/*	$OpenBSD: sshreg.h,v 1.3 2003/02/11 19:20:26 mickey Exp $ */
 
 /*
  * Copyright (c) 1995 Theo de Raadt
@@ -324,10 +324,10 @@ typedef volatile ssh_regmap_t *ssh_regmap_p;
 /* DMA control register (dcntl) */
 
 #define	SSH_DCNTL_CF_MASK	0xc0	/* Clock frequency dividers:
-						0 --> 37.51..50.00 Mhz, div=2
-						1 --> 25.01..37.50 Mhz, div=1.5
-						2 --> 16.67..25.00 Mhz, div=1
-						3 --> 50.01..66.67 Mhz, div=3
+						0 --> 37.51..50.00 MHz, div=2
+						1 --> 25.01..37.50 MHz, div=1.5
+						2 --> 16.67..25.00 MHz, div=1
+						3 --> 50.01..66.67 MHz, div=3
 					 */
 #define	SSH_DCNTL_EA		0x20	/* Enable ack */
 #define	SSH_DCNTL_SSM		0x10	/* Single step mode */