Preliminary switch to an mvme88k bus_space world. Not all drivers have been

converted yet, and they rely upon some linear mappings provided by bus_space.

In order to not impact performance, almost all the bus_space accesses go
through macros and inline functions. This currently restricts us to D16 and
D32 access modes, which are selected at compilation time. Since there are no
plans to support D8 vme devices in the future, this is acceptable for now.

This makes the "len" locator for vme devices go away, and allows to simplify
some code which was using the pcctwo device, and will now directly access
hardware which is known to exist, rather than wait until the device is
attached.

While there, try to enforce more interrupt vector number checks, since these
changes pointed out that dart(4) had been working correctly so far by sheer
luck only.

1 files changed, 566 insertions, 709 deletions

diff --git a/sys/arch/mvme88k/dev/cl.c b/sys/arch/mvme88k/dev/cl.c
index f55b48dbfee..889d6c77053 100644
--- a/sys/arch/mvme88k/dev/cl.c
+++ b/sys/arch/mvme88k/dev/cl.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cl.c,v 1.43 2004/04/16 23:32:44 miod Exp $ */
+/*	$OpenBSD: cl.c,v 1.44 2004/04/24 19:51:47 miod Exp $ */
 
 /*
  * Copyright (c) 1995 Dale Rahn. All rights reserved.
@@ -46,6 +46,7 @@
 
 #include <mvme88k/dev/clreg.h>
 #include <mvme88k/dev/pcctworeg.h>
+#include <mvme88k/dev/pcctwovar.h>
 
 #ifdef	DDB
 #include <ddb/db_var.h>
@@ -67,10 +68,10 @@
 #define CL_RXINTR	0x02
 
 struct cl_cons {
-	void	*cl_paddr;
-	struct clreg *volatile cl_vaddr;
-	struct pcctworeg *volatile pcctwoaddr;
-	u_char	channel;
+	bus_space_tag_t		cl_iot;
+	bus_space_handle_t	cl_ioh;
+	volatile u_int8_t	*cl_rxiack;
+	u_int8_t		channel;
 } cl_cons;
 
 struct cl_info {
@@ -84,7 +85,9 @@ struct cl_info {
 	u_char	cl_txmode;
 	u_char	cl_clen;
 	u_char	cl_parity;
+#if 0
 	u_char  transmitting;
+#endif
 	u_long  txcnt;
 	u_long  rxcnt;
 
@@ -103,21 +106,19 @@ char cl_dmabuf1[CLCD_PORTS_PER_CHIP * CL_BUFSIZE * 4];
 #endif
 
 struct clsoftc {
-	struct device	sc_dev;
-	struct evcnt sc_txintrcnt;
-	struct evcnt sc_rxintrcnt;
-	struct evcnt sc_mxintrcnt;
-	time_t	sc_rotime;	/* time of last ring overrun */
-	time_t	sc_fotime;	/* time of last fifo overrun */
-	u_char *pbase;
-	struct clreg *cl_reg;
+	struct device		sc_dev;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+	struct evcnt		sc_txintrcnt;
+	struct evcnt		sc_rxintrcnt;
+	struct evcnt		sc_mxintrcnt;
+	time_t			sc_fotime;	/* time of last fifo overrun */
 	struct cl_info		sc_cl[CLCD_PORTS_PER_CHIP];
 	struct intrhand		sc_ih_e;
 	struct intrhand		sc_ih_m;
 	struct intrhand		sc_ih_t;
 	struct intrhand		sc_ih_r;
-	struct pcctworeg		*sc_pcctwo;
-	int			sc_flags;
+	struct pcctwosoftc	*sc_pcctwo;
 };
 
 const struct {
@@ -144,12 +145,14 @@ const struct {
 	{     0, 0x00, 0, 0},
 };
 
+#define	CL_SAFE_CLOCK	4	/* 9600 entry */
+
 /* prototypes */
 cons_decl(cl);
 int cl_instat(struct clsoftc *sc);
-u_char cl_clkdiv(int speed);
-u_char cl_clknum(int speed);
-u_char cl_clkrxtimeout(int speed);
+u_int8_t cl_clkdiv(int speed);
+u_int8_t cl_clknum(int speed);
+u_int8_t cl_clkrxtimeout(int speed);
 void clstart(struct tty *tp);
 void cl_unblock(struct tty *tp);
 int clccparam(struct clsoftc *sc, struct termios *par, int channel);
@@ -164,15 +167,14 @@ void cl_frame(struct clsoftc *sc, int channel);
 void cl_break( struct clsoftc *sc, int channel);
 int clmctl(dev_t dev, int bits, int how);
 #ifdef DEBUG
-void cl_dumpport(int channel);
+void cl_dumpport(struct clsoftc *, int);
 #endif
 
 int	clprobe(struct device *parent, void *self, void *aux);
 void	clattach(struct device *parent, struct device *self, void *aux);
 
-void cl_initchannel(struct clsoftc *sc, int channel);
-void clputc(struct clsoftc *sc, int unit, u_char c);
-u_char clgetc(struct clsoftc *sc, int *channel);
+void	cl_initchannel(struct clsoftc *sc, int channel);
+void	clputc(struct clsoftc *sc, int unit, u_char c);
 
 struct cfattach cl_ca = {
 	sizeof(struct clsoftc), clprobe, clattach
@@ -200,7 +202,7 @@ cltty(dev)
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
 	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
-		return (NULL);
+		return NULL;
 	}
 	channel = CL_CHANNEL(dev);
 	return sc->sc_cl[channel].tty;
@@ -212,25 +214,27 @@ clprobe(parent, self, aux)
 	void *self;
 	void *aux;
 {
-	struct clreg *cl_reg;
 	struct confargs *ca = aux;
+	bus_space_handle_t ioh;
+	int rc;
 
 	if (brdtyp == BRD_188)
-		return (0);
+		return 0;
 
 	/*
 	 * We do not accept empty locators here...
 	 */
-	if ((vaddr_t)ca->ca_paddr == CD2400_BASE_ADDR ||
-	    ((vaddr_t)ca->ca_paddr == CD2400_SECONDARY_ADDR &&
-	     brdtyp == BRD_8120)) {
-		ca->ca_ipl = IPL_TTY;
-		ca->ca_vaddr = ca->ca_paddr;
+	if (ca->ca_paddr == CD2400_BASE_ADDR ||
+	    (ca->ca_paddr == CD2400_SECONDARY_ADDR && brdtyp == BRD_8120)) {
+		if (bus_space_map(ca->ca_iot, ca->ca_paddr, CD2400_SIZE,
+		    0, &ioh) != 0)
+			return 0;
+		rc = badvaddr((vaddr_t)bus_space_vaddr(ca->ca_iot, ioh), 1);
+		bus_space_unmap(ca->ca_iot, ca->ca_paddr, CD2400_SIZE);
+		return rc == 0;
+	}
 
-		cl_reg = (struct clreg *)ca->ca_vaddr;
-		return (!badvaddr((vaddr_t)&cl_reg->cl_gfrcr, 1));
-	} else
-		return (0);
+	return 0;
 }
 
 void
@@ -241,31 +245,41 @@ clattach(parent, self, aux)
 {
 	struct clsoftc *sc = (struct clsoftc *)self;
 	struct confargs *ca = aux;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
 	int i;
 
-	sc->cl_reg = (struct clreg *)ca->ca_vaddr;
-	sc->sc_pcctwo = ca->ca_master;
+	if (ca->ca_ipl < 0)
+		ca->ca_ipl = IPL_TTY;
+
+	iot = sc->sc_iot = ca->ca_iot;
+	if (bus_space_map(iot, ca->ca_paddr, CD2400_SIZE, 0, &ioh) != 0) {
+		printf(": can't map registers!\n");
+		return;
+	}
+	sc->sc_ioh = ioh;
+	sc->sc_pcctwo = (struct pcctwosoftc *)parent;
 
-	if ((paddr_t)ca->ca_paddr == CD2400_BASE_ADDR) {
+	if (ca->ca_paddr == CD2400_BASE_ADDR) {
 		/*
 		 * Although we are still running using the BUG routines,
 		 * this device will be elected as the console after
 		 * autoconf. Mark it as such.
 		 */
 		sc->sc_cl[0].cl_consio = 1;
-		printf(": console ");
+		printf(": console");
 	} else {
 		/* reset chip only if we are not console device */
 		/* wait for GFRCR */
 	}
-        /* allow chip to settle before continuing */
-        delay(800);
+	/* allow chip to settle before continuing */
+	delay(800);
 
 	/* set up global registers */
-	sc->cl_reg->cl_tpr = CL_TIMEOUT;
-	sc->cl_reg->cl_rpilr = 0x03;
-	sc->cl_reg->cl_tpilr = 0x02;
-	sc->cl_reg->cl_mpilr = 0x01;
+	bus_space_write_1(iot, ioh, CL_TPR, CL_TIMEOUT);
+	bus_space_write_1(iot, ioh, CL_RPILR, 0x03);
+	bus_space_write_1(iot, ioh, CL_TPILR, 0x02);
+	bus_space_write_1(iot, ioh, CL_MPILR, 0x01);
 
 #ifdef DO_MALLOC
 	sc->sc_cl[0].rx[0] = (void *)(dvma_malloc(16 * CL_BUFSIZE));
@@ -317,6 +331,11 @@ clattach(parent, self, aux)
 #endif
 		cl_initchannel(sc, i);
 	}
+
+	/* clear errors */
+	bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh,
+	    PCCTWO_SCCERR, 0x01);
+
 	/* enable interrupts */
 	sc->sc_ih_e.ih_fn = cl_rxintr;
 	sc->sc_ih_e.ih_arg = sc;
@@ -338,21 +357,22 @@ clattach(parent, self, aux)
 	sc->sc_ih_e.ih_wantframe = 0;
 	sc->sc_ih_r.ih_ipl = ca->ca_ipl;
 
-	intr_establish(PCC2_VECT + SRXEIRQ, &sc->sc_ih_e);
-	intr_establish(PCC2_VECT + SMOIRQ, &sc->sc_ih_m);
-	intr_establish(PCC2_VECT + STxIRQ, &sc->sc_ih_t);
-	intr_establish(PCC2_VECT + SRxIRQ, &sc->sc_ih_r);
-	sc->sc_pcctwo = ca->ca_master;
-	sc->sc_pcctwo->pcc2_sccerr = 0x01; /* clear errors */
+	pcctwointr_establish(PCC2V_SCC_RXE, &sc->sc_ih_e);
+	pcctwointr_establish(PCC2V_SCC_M, &sc->sc_ih_m);
+	pcctwointr_establish(PCC2V_SCC_TX, &sc->sc_ih_t);
+	pcctwointr_establish(PCC2V_SCC_RX, &sc->sc_ih_r);
 
-	/* enable all interrupts at ca_ipl */
-	sc->sc_pcctwo->pcc2_sccirq = 0x10 | (ca->ca_ipl & 0x7);
-	sc->sc_pcctwo->pcc2_scctx  = 0x10 | (ca->ca_ipl & 0x7);
-	sc->sc_pcctwo->pcc2_sccrx  = 0x10 | (ca->ca_ipl & 0x7);
+	bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh,
+	    PCCTWO_SCCICR, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL));
+	bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh,
+	    PCCTWO_SCCTX, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL));
+	bus_space_write_1(sc->sc_pcctwo->sc_iot, sc->sc_pcctwo->sc_ioh,
+	    PCCTWO_SCCRX, PCC2_IRQ_IEN | (ca->ca_ipl & PCC2_IRQ_IPL));
 
 	evcnt_attach(&sc->sc_dev, "intr", &sc->sc_txintrcnt);
 	evcnt_attach(&sc->sc_dev, "intr", &sc->sc_rxintrcnt);
 	evcnt_attach(&sc->sc_dev, "intr", &sc->sc_mxintrcnt);
+
 	printf("\n");
 }
 
@@ -362,43 +382,49 @@ cl_initchannel(sc, channel)
 	int channel;
 {
 	int s;
-	struct clreg *cl_reg = sc->cl_reg;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
+
 	/* set up option registers */
 	sc->sc_cl[channel].tty = NULL;
 	s = splhigh();
-	cl_reg->cl_car	= (u_char) channel;
-	cl_reg->cl_livr	= PCC2_VECT + 0xc;/* set vector base at 5C */
-	cl_reg->cl_ier	= 0x00;
-	/* if the port is not the console, should be init for all ports??*/
-	if (sc->sc_cl[channel].cl_consio != 1) {
-		cl_reg->cl_cmr	= 0x02;
-		cl_reg->cl_cor1	= 0x17;
-		cl_reg->cl_cor2	= 0x00;
-		cl_reg->cl_cor3	= 0x02;
-		cl_reg->cl_cor4	= 0xec;
-		cl_reg->cl_cor5	= 0xec;
-		cl_reg->cl_cor6	= 0x00;
-		cl_reg->cl_cor7	= 0x00;
-		cl_reg->cl_schr1	= 0x00;
-		cl_reg->cl_schr2	= 0x00;
-		cl_reg->cl_schr3	= 0x00;
-		cl_reg->cl_schr4	= 0x00;
-		cl_reg->cl_scrl	= 0x00;
-		cl_reg->cl_scrh	= 0x00;
-		cl_reg->cl_lnxt	= 0x00;
-		cl_reg->cl_rbpr	= 0x40; /* 9600 */
-		cl_reg->cl_rcor	= 0x01;
-		cl_reg->cl_tbpr	= 0x40; /* 9600 */
-		cl_reg->cl_tcor	= 0x01 << 5;
+
+	bus_space_write_1(iot, ioh, CL_CAR, channel);
+	bus_space_write_1(iot, ioh, CL_LIVR, PCC2_VECT + PCC2V_SCC_RXE);
+	bus_space_write_1(iot, ioh, CL_IER, 0);
+
+	if (sc->sc_cl[channel].cl_consio == 0) {
+		bus_space_write_1(iot, ioh, CL_CMR, 0x02);
+		bus_space_write_1(iot, ioh, CL_COR1, 0x17);
+		bus_space_write_1(iot, ioh, CL_COR2, 0x00);
+		bus_space_write_1(iot, ioh, CL_COR3, 0x02);
+		bus_space_write_1(iot, ioh, CL_COR4, 0xec);
+		bus_space_write_1(iot, ioh, CL_COR5, 0xec);
+		bus_space_write_1(iot, ioh, CL_COR6, 0x00);
+		bus_space_write_1(iot, ioh, CL_COR7, 0x00);
+		bus_space_write_1(iot, ioh, CL_SCHR1, 0x00);
+		bus_space_write_1(iot, ioh, CL_SCHR2, 0x00);
+		bus_space_write_1(iot, ioh, CL_SCHR3, 0x00);
+		bus_space_write_1(iot, ioh, CL_SCHR4, 0x00);
+		bus_space_write_1(iot, ioh, CL_SCRL, 0x00);
+		bus_space_write_1(iot, ioh, CL_SCRH, 0x00);
+		bus_space_write_1(iot, ioh, CL_LNXT, 0x00);
+		bus_space_write_1(iot, ioh, CL_RBPR, 0x40);	/* 9600 */
+		bus_space_write_1(iot, ioh, CL_RCOR, 0x01);
+		bus_space_write_1(iot, ioh, CL_TBPR, 0x40);	/* 9600 */
+		bus_space_write_1(iot, ioh, CL_TCOR, 0x01 << 5);
 		/* console port should be 0x88 already */
-		cl_reg->cl_msvr_rts	= 0x00;
-		cl_reg->cl_msvr_dtr	= 0x00;
-		cl_reg->cl_rtprl	= CL_RX_TIMEOUT;
-		cl_reg->cl_rtprh	= 0x00;
-	}
-	sc->cl_reg->cl_ccr = 0x20;
-	while (sc->cl_reg->cl_ccr != 0) {
+		bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00);
+		bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00);
+		bus_space_write_1(iot, ioh, CL_RTPRL, CL_RX_TIMEOUT);
+		bus_space_write_1(iot, ioh, CL_RTPRH, 0x00);
 	}
+	bus_space_write_1(iot, ioh, CL_CCR, 0x20);
+	while (bus_space_read_1(iot, ioh, CL_CCR) != 0)
+		;
 
 	splx(s);
 }
@@ -412,71 +438,63 @@ clmctl(dev, bits, how)
 	int bits;
 	int how;
 {
-	int s;
 	struct clsoftc *sc;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	int s;
+
 	/* should only be called with valid device */
-	sc = (struct clsoftc *) cl_cd.cd_devs[CL_UNIT(dev)];
-	/*
-	printf("mctl: dev %x, bits %x, how %x,\n",dev, bits, how);
-	*/
+	sc = (struct clsoftc *)cl_cd.cd_devs[CL_UNIT(dev)];
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
+
 	/* settings are currently ignored */
 	s = splcl();
 	switch (how) {
 	case DMSET:
-		if( bits & TIOCM_RTS) {
-			sc->cl_reg->cl_msvr_rts = 0x01;
-		} else {
-			sc->cl_reg->cl_msvr_rts = 0x00;
-		}
-		if( bits & TIOCM_DTR) {
-			sc->cl_reg->cl_msvr_dtr = 0x02;
-		} else {
-			sc->cl_reg->cl_msvr_dtr = 0x00;
-		}
+		if (bits & TIOCM_RTS)
+			bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x01);
+		else
+			bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00);
+		if (bits & TIOCM_DTR)
+			bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x02);
+		else
+			bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00);
 		break;
 
 	case DMBIC:
-		if( bits & TIOCM_RTS) {
-			sc->cl_reg->cl_msvr_rts = 0x00;
-		}
-		if( bits & TIOCM_DTR) {
-			sc->cl_reg->cl_msvr_dtr = 0x00;
-		}
+		if (bits & TIOCM_RTS)
+			bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00);
+		if (bits & TIOCM_DTR)
+			bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00);
 		break;
 
 	case DMBIS:
-		if( bits & TIOCM_RTS) {
-			sc->cl_reg->cl_msvr_rts = 0x01;
-		}
-		if( bits & TIOCM_DTR) {
-			sc->cl_reg->cl_msvr_dtr = 0x02;
-		}
+		if (bits & TIOCM_RTS)
+			bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x01);
+		if (bits & TIOCM_DTR)
+			bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x02);
 		break;
 
 	case DMGET:
 		bits = 0;
 
 		{
-			u_char msvr;
-			msvr = sc->cl_reg->cl_msvr_rts;
-			if( msvr & 0x80) {
+			u_int8_t msvr;
+
+			msvr = bus_space_read_1(iot, ioh, CL_MSVR_RTS);
+			if (msvr & 0x80)
 				bits |= TIOCM_DSR;
-			}
-			if( msvr & 0x40) {
+			if (msvr & 0x40)
 				bits |= TIOCM_CD;
-			}
-			if( msvr & 0x20) {
+			if (msvr & 0x20)
 				bits |= TIOCM_CTS;
-			}
-			if( msvr & 0x10) {
+			if (msvr & 0x10)
 				bits |= TIOCM_DTR;
-			}
-			if( msvr & 0x02) {
+			if (msvr & 0x02)
 				bits |= TIOCM_DTR;
-			}
-			if( msvr & 0x01) {
+			if (msvr & 0x01)
 				bits |= TIOCM_RTS;
-			}
 		}
 		break;
 	}
@@ -492,10 +510,7 @@ clmctl(dev, bits, how)
 	bits |= TIOCM_DSR;
 #endif
 
-	/*
-	printf("retbits %x\n", bits);
-	*/
-	return(bits);
+	return bits;
 }
 
 int
@@ -512,11 +527,13 @@ clopen(dev, flag, mode, p)
 
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
-		return (ENODEV);
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
+		return ENODEV;
 	}
+
 	channel = CL_CHANNEL(dev);
 	cl = &sc->sc_cl[channel];
+
 	s = splcl();
 	if (cl->tty) {
 		tp = cl->tty;
@@ -539,7 +556,7 @@ clopen(dev, flag, mode, p)
 			tp->t_lflag = TTYDEF_LFLAG;
 			tp->t_ispeed = tp->t_ospeed = cldefaultrate;
 
-			if(sc->sc_cl[channel].cl_consio == 1) {
+			if (sc->sc_cl[channel].cl_consio != 0) {
 				/* console is 8N1 */
 				tp->t_cflag = (CREAD | CS8 | HUPCL);
 			} else {
@@ -569,76 +586,30 @@ clopen(dev, flag, mode, p)
 #endif
 		tp->t_state |= TS_CARR_ON;
 		{
-			u_char save = sc->cl_reg->cl_car;
-			sc->cl_reg->cl_car = channel;
-			sc->cl_reg->cl_ier	= 0x88;
-#ifdef CL_DMA_WORKS
-			{
-			sc->cl_reg->cl_cmr	=
-				/* CL_TXDMAINT | */ CL_RXDMAINT;
-			sc->cl_reg->cl_ier	= 0xa8;
-			sc->cl_reg->cl_licr	= 0x00;
-			}
-			sc->cl_reg->cl_arbadrl	=
-				((u_long)sc->sc_cl[channel].rxp[0]) & 0xffff;
-			sc->cl_reg->cl_arbadru	=
-				((u_long)sc->sc_cl[channel].rxp[0]) >> 16;
-			sc->cl_reg->cl_brbadrl	=
-				((u_long)sc->sc_cl[channel].rxp[1]) & 0xffff;
-			sc->cl_reg->cl_brbadru	=
-				((u_long)sc->sc_cl[channel].rxp[1]) >> 16;
-			sc->cl_reg->cl_atbadrl	=
-				((u_long)sc->sc_cl[channel].txp[0]) & 0xffff;
-			sc->cl_reg->cl_atbadru	=
-				((u_long)sc->sc_cl[channel].txp[0]) >> 16;
-			sc->cl_reg->cl_btbadrl	=
-				((u_long)sc->sc_cl[channel].txp[1]) & 0xffff;
-			sc->cl_reg->cl_btbadru	=
-				((u_long)sc->sc_cl[channel].txp[1]) >> 16;
-			sc->cl_reg->cl_arbcnt	= CL_BUFSIZE;
-			sc->cl_reg->cl_brbcnt	= CL_BUFSIZE;
-			sc->cl_reg->cl_arbsts	= 0x01;
-			sc->cl_reg->cl_brbsts	= 0x01;
-if (channel == 2) { /* test one channel now */
-			/* shift for tx DMA */
-			/* no shift for rx DMA */
-#if 0
-			/* tx only */
-			sc->cl_reg->cl_licr	= (CL_DMAMODE << 4);
-			sc->cl_reg->cl_cmr	= 0x42;
-#endif
-		/* rx only */
-			sc->cl_reg->cl_licr	= 0x00;
-			sc->cl_reg->cl_cmr	= 0x82;
-}
-			sc->cl_reg->cl_ccr = 0x20;
-			while (sc->cl_reg->cl_ccr != 0) {
-			}
-#endif /* CL_DMA_WORKS */
-			sc->cl_reg->cl_car = save;
+			u_int8_t save;
+
+			save = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CL_CAR);
+			bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR,
+			    channel);
+			bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_IER, 0x88);
+			bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR,
+			    save);
 		}
 	} else if (tp->t_state & TS_XCLUDE && p->p_ucred->cr_uid != 0) {
 		splx(s);
-		return(EBUSY);
+		return EBUSY;
 	}
-#ifdef XXX
-	/*
-	 * if NONBLOCK requested, ignore carrier
-	 */
-	if (flag & O_NONBLOCK)
-	goto done;
-#endif
-
 	splx(s);
+
 	/*
 	 * Reset the tty pointer, as there could have been a dialout
 	 * use of the tty with a dialin open waiting.
 	 */
 	tp->t_dev = dev;
 #ifdef DEBUG
-	cl_dumpport(channel);
+	cl_dumpport(sc, channel);
 #endif
-	return((*linesw[tp->t_line].l_open)(dev, tp));
+	return (*linesw[tp->t_line].l_open)(dev, tp);
 }
 
 int
@@ -654,8 +625,8 @@ clparam(tp, t)
 	dev = tp->t_dev;
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
-		return (ENODEV);
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
+		return ENODEV;
 	}
 	channel = CL_CHANNEL(dev);
 	tp->t_ispeed = t->c_ispeed;
@@ -683,7 +654,7 @@ cloutput(tp)
 	dev = tp->t_dev;
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
 		return;
 	}
 	channel = CL_CHANNEL(dev);
@@ -720,26 +691,31 @@ clclose(dev, flag, mode, p)
 	struct tty *tp;
 	struct cl_info *cl;
 	struct clsoftc *sc;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
 	int s;
+
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
-		return (ENODEV);
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
+		return ENODEV;
 	}
 	channel = CL_CHANNEL(dev);
 	cl = &sc->sc_cl[channel];
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
 	tp = cl->tty;
 	(*linesw[tp->t_line].l_close)(tp, flag);
 
 	s = splcl();
-
-	sc->cl_reg->cl_car = channel;
-	if(cl->cl_consio == 0 && (tp->t_cflag & HUPCL) != 0) {
-		sc->cl_reg->cl_msvr_rts = 0x00;
-		sc->cl_reg->cl_msvr_dtr = 0x00;
-		sc->cl_reg->cl_ccr = 0x05;
+	bus_space_write_1(iot, ioh, CL_CAR, channel);
+	if (cl->cl_consio == 0 && (tp->t_cflag & HUPCL) != 0) {
+		bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00);
+		bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00);
+		bus_space_write_1(iot, ioh, CL_CCR, 0x05);
 	}
 
+
 	splx(s);
 	ttyclose(tp);
 
@@ -747,7 +723,7 @@ clclose(dev, flag, mode, p)
 	cl->tty = NULL;
 #endif
 #ifdef DEBUG
-	cl_dumpport(channel);
+	cl_dumpport(sc, channel);
 #endif
 
 	return 0;
@@ -765,15 +741,15 @@ clread(dev, uio, flag)
 	struct clsoftc *sc;
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
-		return (ENODEV);
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
+		return ENODEV;
 	}
 	channel = CL_CHANNEL(dev);
 	cl = &sc->sc_cl[channel];
 	tp = cl->tty;
-	if (!tp)
+	if (tp == NULL)
 		return ENXIO;
-	return((*linesw[tp->t_line].l_read)(tp, uio, flag));
+	return (*linesw[tp->t_line].l_read)(tp, uio, flag);
 }
 
 int
@@ -788,15 +764,15 @@ clwrite(dev, uio, flag)
 	struct clsoftc *sc;
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
-		return (ENODEV);
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
+		return ENODEV;
 	}
 	channel = CL_CHANNEL(dev);
 	cl = &sc->sc_cl[channel];
 	tp = cl->tty;
-	if (!tp)
+	if (tp == NULL)
 		return ENXIO;
-	return((*linesw[tp->t_line].l_write)(tp, uio, flag));
+	return (*linesw[tp->t_line].l_write)(tp, uio, flag);
 }
 
 int
@@ -814,22 +790,22 @@ clioctl(dev, cmd, data, flag, p)
 	struct clsoftc *sc;
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
-		return (ENODEV);
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
+		return ENODEV;
 	}
 	channel = CL_CHANNEL(dev);
 	cl = &sc->sc_cl[channel];
 	tp = cl->tty;
-	if (!tp)
+	if (tp == NULL)
 		return ENXIO;
 
 	error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
 	if (error >= 0)
-		return(error);
+		return error;
 
 	error = ttioctl(tp, cmd, data, flag, p);
 	if (error >= 0)
-		return(error);
+		return error;
 
 	switch (cmd) {
 	case TIOCSBRK:
@@ -869,14 +845,14 @@ clioctl(dev, cmd, data, flag, p)
 	case TIOCSFLAGS:
 		error = suser(p, 0);
 		if (error != 0)
-			return(EPERM);
+			return EPERM;
 
 		cl->cl_swflags = *(int *)data;
 		cl->cl_swflags &= /* only allow valid flags */
 			(TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | TIOCFLAG_CRTSCTS);
 		break;
 	default:
-		return(ENOTTY);
+		return ENOTTY;
 	}
 
 	return 0;
@@ -898,13 +874,6 @@ clstop(tp, flag)
 	return 0;
 }
 
-/*
- * clcn* stuff happens before configure() runs kicking off
- * autoconfig. Use a virtual mapping set up in locore till
- * the device is actually configured. Need mappings for
- * pcc2 space and Cirrus chip area.
- */
-
 void
 clcnprobe(cp)
 	struct consdev *cp;
@@ -917,6 +886,10 @@ clcnprobe(cp)
 	if (brdtyp == BRD_188 || badaddr(CD2400_BASE_ADDR, 1) != 0)
 		return;
 
+	/* do not attach as console if cl has been disabled */
+	if (cl_cd.cd_ndevs == 0 || cl_cd.cd_devs[0] == NULL)
+		return;
+
 	/* locate the major number */
 	for (maj = 0; maj < nchrdev; maj++)
 		if (cdevsw[maj].d_open == clopen)
@@ -932,113 +905,70 @@ void
 clcninit(cp)
 	struct consdev *cp;
 {
-	struct clreg *volatile cl_reg;
-
-	cl_cons.cl_paddr = (void *)CD2400_BASE_ADDR;
-	cl_cons.cl_vaddr   = (struct clreg *)IIOV(cl_cons.cl_paddr);
-	cl_cons.pcctwoaddr = (void *)IIOV(0xfff42000);
-	cl_reg = cl_cons.cl_vaddr;
-	/* reset the chip? */
-#ifdef CLCD_DO_RESET
-#endif
-	/* set up globals */
-#ifdef NOT_ALREADY_SETUP
-	cl_reg->cl_tftc  = 0x10;
-	cl_reg->cl_tpr   = CL_TIMEOUT; /* is this correct?? */
-	cl_reg->cl_rpilr = 0x03;
-	cl_reg->cl_tpilr = 0x02;
-	cl_reg->cl_mpilr = 0x01;
-
-	/* set up the tty00 to be 9600 8N1 */
-	cl_reg->cl_car   = 0x00;
-	cl_reg->cl_cor1  = 0x17;	/* No parity, ignore parity, 8 bit char */
-	cl_reg->cl_cor2  = 0x00;
-	cl_reg->cl_cor3  = 0x02;	/* 1 stop bit */
-	cl_reg->cl_cor4  = 0x00;
-	cl_reg->cl_cor5  = 0x00;
-	cl_reg->cl_cor6  = 0x00;
-	cl_reg->cl_cor7  = 0x00;
-	cl_reg->cl_schr1 = 0x00;
-	cl_reg->cl_schr2 = 0x00;
-	cl_reg->cl_schr3 = 0x00;
-	cl_reg->cl_schr4 = 0x00;
-	cl_reg->cl_scrl  = 0x00;
-	cl_reg->cl_scrh  = 0x00;
-	cl_reg->cl_lnxt  = 0x00;
-	cl_reg->cl_cpsr  = 0x00;
-#endif
+	struct clsoftc *sc;
+
+	sc = (struct clsoftc *)cl_cd.cd_devs[0];
+	cl_cons.cl_iot = sc->sc_iot;
+	cl_cons.cl_ioh = sc->sc_ioh;
+	cl_cons.cl_rxiack = (void *)(sc->sc_pcctwo->sc_base + PCCTWO_SCCRXIACK);
 }
 
 int
 cl_instat(sc)
 	struct clsoftc *sc;
 {
-	struct clreg *volatile cl_reg;
-	if ( NULL == sc) {
-		cl_reg = cl_cons.cl_vaddr;
-	} else {
-		cl_reg = sc->cl_reg;
-	}
-	return (cl_reg->cl_rir & 0x40);
+	u_int8_t rir;
+
+	if (sc == NULL)
+		rir = bus_space_read_1(cl_cons.cl_iot, cl_cons.cl_ioh, CL_RIR);
+	else
+		rir = bus_space_read_1(sc->sc_iot, sc->sc_ioh, CL_RIR);
+
+	return (rir & 0x40);
 }
 
 int
 clcngetc(dev)
 	dev_t dev;
 {
-	u_char val, reoir, licr, isrl, data = 0, fifo_cnt;
-#if 0
-	u_char status;
-#endif
+	u_int8_t val, reoir, licr, data;
 	int got_char = 0;
-	u_char ier_old = 0xff;
-	struct clreg *volatile cl_reg = cl_cons.cl_vaddr;
-	struct pcctworeg *volatile pcc2_base = cl_cons.pcctwoaddr;
-	cl_reg->cl_car = 0;
-	if (!(cl_reg->cl_ier & 0x08)) {
-		ier_old = cl_reg->cl_ier;
-		cl_reg->cl_ier	= 0x08;
-	}
+	u_int8_t ier_old;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+
+	iot = cl_cons.cl_iot;
+	ioh = cl_cons.cl_ioh;
+
+	bus_space_write_1(iot, ioh, CL_CAR, 0);
+	ier_old = bus_space_read_1(iot, ioh, CL_IER);
+	if ((ier_old & 0x08) == 0) {
+		bus_space_write_1(iot, ioh, CL_IER, 0x08);
+	} else
+		ier_old = 0xff;
 
 	while (got_char == 0) {
-		val = cl_reg->cl_rir;
+		val = bus_space_read_1(iot, ioh, CL_RIR);
 		/* if no receive interrupt pending wait */
-		if (!(val & 0x80)) {
+		if ((val & 0x80) == 0)
 			continue;
-		}
+
 		/* XXX do we need to suck the entire FIFO contents? */
-		reoir = pcc2_base->pcc2_sccrxiack; /* receive PIACK */
-		licr = cl_reg->cl_licr;
+		reoir = *cl_cons.cl_rxiack; /* receive PIACK */
+		licr = bus_space_read_1(iot, ioh, CL_LICR);
+		/* is the interrupt for us? (port 0) */
 		if (((licr >> 2) & 0x3) == 0) {
-			/* is the interrupt for us (port 0) */
-			/* the character is for us yea. */
-			isrl = cl_reg->cl_risrl;
-#if 0
-			if (isrl & 0x01) {
-				status = BREAK;
-			}
-			if (isrl & 0x02) {
-				status = FRAME;
-			}
-			if (isrl & 0x04) {
-				status = PARITY;
-			}
-			if (isrl & 0x08) {
-				status = OVERFLOW;
-			}
-			/* we do not have special characters ;-) */
-#endif
-			fifo_cnt = cl_reg->cl_rfoc;
-			data = cl_reg->cl_rdr;
-			if (ier_old != 0xff) {
-				cl_reg->cl_ier  = ier_old;
-			}
+			(void)bus_space_read_1(iot, ioh, CL_RISRL);
+			(void)bus_space_read_1(iot, ioh, CL_RFOC);
+			data = bus_space_read_1(iot, ioh, CL_RDR);
+			if (ier_old != 0xff)
+				bus_space_write_1(iot, ioh, CL_IER, ier_old);
 			got_char = 1;
-			cl_reg->cl_teoir = 0x00;
 		} else {
-			data = cl_reg->cl_rdr;
-			cl_reg->cl_teoir = 0x00;
+			/* read and discard the character */
+			data = bus_space_read_1(iot, ioh, CL_RDR);
 		}
+		bus_space_write_1(iot, ioh, CL_TEOIR, 0x00);
 	}
 
 	return data;
@@ -1057,12 +987,11 @@ clcnpollc(dev, on)
 	dev_t dev;
 	int on;
 {
-	if (1 == on) {
+	if (on != 0) {
 		/* enable polling */
 	} else {
 		/* disable polling */
 	}
-	return;
 }
 
 void
@@ -1071,112 +1000,43 @@ clputc(sc, unit, c)
 	int unit;
 	u_char c;
 {
+	u_int8_t schar;
+	u_int8_t oldchannel;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
 	int s;
-	u_char schar;
-	u_char oldchannel;
-	struct clreg *volatile cl_reg;
-	if (0 == sc) {
+
+	if (sc == NULL) {
 		/* output on console */
-		cl_reg = cl_cons.cl_vaddr;
+		iot = cl_cons.cl_iot;
+		ioh = cl_cons.cl_ioh;
 	} else {
-		cl_reg = sc->cl_reg;
+		iot = sc->sc_iot;
+		ioh = sc->sc_ioh;
 	}
-#ifdef NEW_CLCD_STRUCT
-	/* should we disable, flush and all that goo? */
-	cl->car = unit;
-	schar = cl->schr3;
-	cl->schr3 = c;
-	cl->stcr = 0x08 | 0x03; /* send special char, char 3 */
-	while (0 != cl->stcr) {
-		/* wait until cl notices the command
-		 * otherwise it may not notice the character
-		 * if we send characters too fast.
-		 */
-	}
-	cl->schr3 = schar;
-#else
+
+	s = splhigh();
+	oldchannel = bus_space_read_1(iot, ioh, CL_CAR);
+	bus_space_write_1(iot, ioh, CL_CAR, unit);
 	if (unit == 0) {
-		s = splhigh();
-		oldchannel = cl_reg->cl_car;
-		cl_reg->cl_car = unit;
-		schar = cl_reg->cl_schr3;
-		cl_reg->cl_schr3 = c;
-		cl_reg->cl_stcr = 0x08 | 0x03; /* send special char, char 3 */
-		while (0 != cl_reg->cl_stcr) {
+		schar = bus_space_read_1(iot, ioh, CL_SCHR3);
+		/* send special char, number 3 */
+		bus_space_write_1(iot, ioh, CL_SCHR3, c);
+		bus_space_write_1(iot, ioh, CL_STCR, 0x08 | 3);
+		while (bus_space_read_1(iot, ioh, CL_STCR) != 0) {
 			/* wait until cl notices the command
 			 * otherwise it may not notice the character
 			 * if we send characters too fast.
 			 */
 		}
 		DELAY(5);
-		cl_reg->cl_schr3 = schar;
-		cl_reg->cl_car = oldchannel;
-		splx(s);
-	} else {
-		s = splhigh();
-		oldchannel = cl_reg->cl_car;
-		cl_reg->cl_car = unit;
-		if (cl_reg->cl_tftc > 0) {
-			cl_reg->cl_tdr = c;
-		}
-		cl_reg->cl_car = oldchannel;
-		splx(s);
-	}
-#endif
-	return;
-}
-
-u_char
-clgetc(sc, channel)
-	struct clsoftc *sc;
-	int *channel;
-{
-	struct clreg *volatile cl_reg;
-	struct pcctworeg *volatile pcc2_base;
-	u_char val, reoir, licr, isrl, fifo_cnt, data;
-	if (0 == sc) {
-		cl_reg = cl_cons.cl_vaddr;
-		pcc2_base = cl_cons.pcctwoaddr;
-	} else {
-		cl_reg = sc->cl_reg;
-		pcc2_base = sc->sc_pcctwo;
-	}
-	val = cl_reg->cl_rir;
-	/* if no receive interrupt pending wait */
-	if (!(val & 0x80)) {
-		return 0;
-	}
-	/* XXX do we need to suck the entire FIFO contents? */
-	reoir = pcc2_base->pcc2_sccrxiack; /* receive PIACK */
-	licr = cl_reg->cl_licr;
-	*channel = (licr >> 2) & 0x3;
-	/* is the interrupt for us (port 0) */
-	/* the character is for us yea. */
-	isrl = cl_reg->cl_risrl;
-#if 0
-	if (isrl & 0x01) {
-		status = BREAK;
-	}
-	if (isrl & 0x02) {
-		status = FRAME;
-	}
-	if (isrl & 0x04) {
-		status = PARITY;
-	}
-	if (isrl & 0x08) {
-		status = OVERFLOW;
-	}
-	/* we do not have special characters ;-) */
-#endif
-	fifo_cnt = cl_reg->cl_rfoc;
-	if (fifo_cnt > 0) {
-		data = cl_reg->cl_rdr;
-		cl_reg->cl_teoir = 0x00;
+		bus_space_write_1(iot, ioh, CL_SCHR3, schar);
 	} else {
-		data = 0;
-		cl_reg->cl_teoir = 0x08;
+		if (bus_space_read_1(iot, ioh, CL_TFTC) != 0)
+			bus_space_write_1(iot, ioh, CL_TDR, c);
 	}
-	return data;
+	bus_space_write_1(iot, ioh, CL_CAR, oldchannel);
+	splx(s);
 }
 
 int
@@ -1185,36 +1045,41 @@ clccparam(sc, par, channel)
 	struct termios *par;
 	int channel;
 {
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
 	u_int divisor, clk, clen;
 	int s, imask, ints;
 
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
+
 	s = splcl();
-	sc->cl_reg->cl_car = channel;
+	bus_space_write_1(iot, ioh, CL_CAR, channel);
 	if (par->c_ospeed == 0) {
 		/* dont kill the console */
-		if(sc->sc_cl[channel].cl_consio == 0) {
+		if (sc->sc_cl[channel].cl_consio == 0) {
 			/* disconnect, drop RTS DTR stop receiver */
-			sc->cl_reg->cl_msvr_rts = 0x00;
-			sc->cl_reg->cl_msvr_dtr = 0x00;
-			sc->cl_reg->cl_ccr = 0x05;
+			bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x00);
+			bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x00);
+			bus_space_write_1(iot, ioh, CL_CCR, 0x05);
 		}
 		splx(s);
-		return (0xff);
+		return 0xff;
 	}
 
-	sc->cl_reg->cl_msvr_rts = 0x03;
-	sc->cl_reg->cl_msvr_dtr = 0x03;
+	bus_space_write_1(iot, ioh, CL_MSVR_RTS, 0x03);
+	bus_space_write_1(iot, ioh, CL_MSVR_DTR, 0x03);
 
 	divisor = cl_clkdiv(par->c_ospeed);
 	clk	= cl_clknum(par->c_ospeed);
-	sc->cl_reg->cl_tbpr = divisor;
-	sc->cl_reg->cl_tcor = clk << 5;
+	bus_space_write_1(iot, ioh, CL_TBPR, divisor);
+	bus_space_write_1(iot, ioh, CL_TCOR, clk << 5);
 	divisor = cl_clkdiv(par->c_ispeed);
 	clk	= cl_clknum(par->c_ispeed);
-	sc->cl_reg->cl_rbpr = divisor;
-	sc->cl_reg->cl_rcor = clk;
-	sc->cl_reg->cl_rtprl = cl_clkrxtimeout(par->c_ispeed);
-	sc->cl_reg->cl_rtprh = 0x00;
+	bus_space_write_1(iot, ioh, CL_RBPR, divisor);
+	bus_space_write_1(iot, ioh, CL_RCOR, clk);
+	bus_space_write_1(iot, ioh, CL_RTPRL, cl_clkrxtimeout(par->c_ispeed));
+	bus_space_write_1(iot, ioh, CL_RTPRH, 0x00);
 
 	switch (par->c_cflag & CSIZE) {
 	case CS5:
@@ -1233,10 +1098,11 @@ clccparam(sc, par, channel)
 		clen = 7;
 		imask = 0xFF;
 	}
-	sc->cl_reg->cl_cor3 = par->c_cflag & PARENB ? 4 : 2;
+
+	bus_space_write_1(iot, ioh, CL_COR3, par->c_cflag & PARENB ? 4 : 2);
 
 	{
-		u_char cor1;
+		u_int8_t cor1;
 		if (par->c_cflag & PARENB) {
 			if (par->c_cflag & PARODD) {
 				cor1 = 0xE0 | clen ; /* odd */
@@ -1246,23 +1112,23 @@ clccparam(sc, par, channel)
 		} else {
 			cor1 = 0x10 | clen; /* ignore parity */
 		}
-		if (sc->cl_reg->cl_cor1 != cor1) {
-			sc->cl_reg->cl_cor1 = cor1;
-			sc->cl_reg->cl_ccr = 0x20;
-			while (sc->cl_reg->cl_ccr != 0) {
-			}
+
+		if (bus_space_read_1(iot, ioh, CL_COR1) != cor1) {
+			bus_space_write_1(iot, ioh, CL_COR1, cor1);
+			bus_space_write_1(iot, ioh, CL_CCR, 0x20);
+			while (bus_space_read_1(iot, ioh, CL_CCR) != 0)
+				;
 		}
 	}
 
-	if (sc->sc_cl[channel].cl_consio == 0
-		&& (par->c_cflag & CREAD) == 0 )
-	{
-		sc->cl_reg->cl_ccr = 0x08;
-	} else {
-		sc->cl_reg->cl_ccr = 0x0a;
-	}
-	while (sc->cl_reg->cl_ccr != 0) {
-	}
+	if (sc->sc_cl[channel].cl_consio == 0 && (par->c_cflag & CREAD) == 0)
+		bus_space_write_1(iot, ioh, CL_CCR, 0x08);
+	else
+		bus_space_write_1(iot, ioh, CL_CCR, 0x0a);
+
+	while (bus_space_read_1(iot, ioh, CL_CCR) != 0)
+		;
+
 	ints = 0;
 #define SCC_DSR 0x80
 #define SCC_DCD 0x40
@@ -1281,68 +1147,74 @@ clccparam(sc, par, channel)
 		ints |= SCC_DSR;
 	}
 #endif
-	sc->cl_reg->cl_cor4 = ints | CL_FIFO_CNT;
-	sc->cl_reg->cl_cor5 = ints | CL_FIFO_CNT;
+	bus_space_write_1(iot, ioh, CL_COR4, ints | CL_FIFO_CNT);
+	bus_space_write_1(iot, ioh, CL_COR5, ints | CL_FIFO_CNT);
 
 	splx(s);
+
 	return imask;
 }
 
 static int clknum = 0;
 
-u_char
+u_int8_t
 cl_clkdiv(speed)
 	int speed;
 {
-	int i = 0;
-	if (cl_clocks[clknum].speed == speed) {
+	int i;
+
+	if (cl_clocks[clknum].speed == speed)
 		return cl_clocks[clknum].divisor;
-	}
+
 	for  (i = 0; cl_clocks[i].speed != 0; i++) {
 		if (cl_clocks[i].speed == speed) {
 			clknum = i;
 			return cl_clocks[clknum].divisor;
 		}
 	}
+
 	/* return some sane value if unknown speed */
-	return cl_clocks[4].divisor;
+	return cl_clocks[CL_SAFE_CLOCK].divisor;
 }
 
-u_char
+u_int8_t
 cl_clknum(speed)
 	int speed;
 {
-	int found = 0;
-	int i = 0;
-	if (cl_clocks[clknum].speed == speed) {
+	int i;
+
+	if (cl_clocks[clknum].speed == speed)
 		return cl_clocks[clknum].clock;
-	}
-	for  (i = 0; found != 0 && cl_clocks[i].speed != 0; i++) {
+
+	for (i = 0; cl_clocks[i].speed != 0; i++) {
 		if (cl_clocks[clknum].speed == speed) {
 			clknum = i;
 			return cl_clocks[clknum].clock;
 		}
 	}
+
 	/* return some sane value if unknown speed */
-	return cl_clocks[4].clock;
+	return cl_clocks[CL_SAFE_CLOCK].clock;
 }
 
-u_char
+u_int8_t
 cl_clkrxtimeout(speed)
 	int speed;
 {
-	int i = 0;
-	if (cl_clocks[clknum].speed == speed) {
+	int i;
+
+	if (cl_clocks[clknum].speed == speed)
 		return cl_clocks[clknum].rx_timeout;
-	}
+
 	for  (i = 0; cl_clocks[i].speed != 0; i++) {
 		if (cl_clocks[i].speed == speed) {
 			clknum = i;
 			return cl_clocks[clknum].rx_timeout;
 		}
 	}
+
 	/* return some sane value if unknown speed */
-	return cl_clocks[4].rx_timeout;
+	return cl_clocks[CL_SAFE_CLOCK].rx_timeout;
 }
 
 void
@@ -1363,7 +1235,7 @@ clstart(tp)
 	int channel, unit, s;
 #if 0
 	int cnt;
-	u_char cbuf;
+	u_int8_t cbuf;
 #endif
 
 	dev = tp->t_dev;
@@ -1377,7 +1249,7 @@ clstart(tp)
 #endif
 	unit = CL_UNIT(dev);
 	if (unit >= cl_cd.cd_ndevs ||
-		(sc = (struct clsoftc *) cl_cd.cd_devs[unit]) == NULL) {
+	    (sc = (struct clsoftc *)cl_cd.cd_devs[unit]) == NULL) {
 		return;
 	}
 
@@ -1394,8 +1266,8 @@ clstart(tp)
 	cnt = q_to_b(&tp->t_outq, &cbuf, 1);
 	if ( cnt != 0 ) {
 		sc->sc_cl[channel].transmitting = 1;
-		sc->cl_reg->cl_car = channel;
-		sc->cl_reg->cl_tdr = cbuf;
+		bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR, channel);
+		bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_TDR, cbuf);
 	} else {
 		sc->sc_cl[channel].transmitting = 0;
 	}
@@ -1403,12 +1275,12 @@ clstart(tp)
 	if ((tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP | TS_FLUSH)) == 0)
 	{
 		tp->t_state |= TS_BUSY;
-		sc->cl_reg->cl_car = channel;
-		sc->cl_reg->cl_ier = sc->cl_reg->cl_ier | 0x3;
+		bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_CAR, channel);
+		bus_space_write_1(sc->sc_iot, sc->sc_ioh, CL_IER,
+		    bus_space_read_1(sc->sc_iot, sc->sc_ioh, CL_IER) | 0x03);
 	}
 #endif
 	splx(s);
-	return;
 }
 
 int
@@ -1416,11 +1288,16 @@ cl_mintr(arg)
 	void *arg;
 {
 	struct clsoftc *sc = arg;
-
-	u_char mir, misr, msvr;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t mir, misr, msvr;
 	int channel;
 
-	if(((mir = sc->cl_reg->cl_mir) & 0x40) == 0x0) {
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
+
+	mir = bus_space_read_1(iot, ioh, CL_MIR);
+	if ((mir & 0x40) == 0) {
 		/* only if intr is not shared? */
 		log(LOG_WARNING, "cl_mintr extra intr\n");
 		return 0;
@@ -1428,8 +1305,8 @@ cl_mintr(arg)
 	sc->sc_mxintrcnt.ev_count++;
 
 	channel = mir & 0x03;
-	misr = sc->cl_reg->cl_misr;
-	msvr = sc->cl_reg->cl_msvr_rts;
+	misr = bus_space_read_1(iot, ioh, CL_MISR);
+	msvr = bus_space_read_1(iot, ioh, CL_MSVR_RTS);
 	if (misr & 0x01) {
 		/* timers are not currently used?? */
 		log(LOG_WARNING, "cl_mintr: channel %x timer 1 unexpected\n",channel);
@@ -1440,13 +1317,13 @@ cl_mintr(arg)
 	}
 	if (misr & 0x20) {
 		log(LOG_WARNING, "cl_mintr: channel %x cts %x\n",channel,
-		((msvr & 0x20) != 0x0)
+		    ((msvr & 0x20) != 0x0)
 		);
 	}
 	if (misr & 0x40) {
 		struct tty *tp = sc->sc_cl[channel].tty;
 		log(LOG_WARNING, "cl_mintr: channel %x cd %x\n",channel,
-		((msvr & 0x40) != 0x0)
+		    ((msvr & 0x40) != 0x0)
 		);
 		ttymodem(tp, ((msvr & 0x40) != 0x0) );
 	}
@@ -1455,7 +1332,7 @@ cl_mintr(arg)
 		((msvr & 0x80) != 0x0)
 		);
 	}
-	sc->cl_reg->cl_meoir = 0x00;
+	bus_space_write_1(iot, ioh, CL_MEOIR, 0);
 	return 1;
 }
 
@@ -1463,17 +1340,21 @@ int
 cl_txintr(arg)
 	void *arg;
 {
+	static int empty;
 	struct clsoftc *sc = arg;
-
-	static int empty = 0;
-	u_char tir, cmr, teoir;
-	u_char max;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t tir, cmr, teoir;
+	u_int8_t max;
 	int channel;
 	struct tty *tp;
 	int cnt;
 	u_char buffer[CL_FIFO_MAX +1];
-	u_char *tptr;
-	if (((tir = sc->cl_reg->cl_tir) & 0x40) == 0x0) {
+
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
+	tir = bus_space_read_1(iot, ioh, CL_TIR);
+	if ((tir & 0x40) == 0) {
 		/* only if intr is not shared ??? */
 		log(LOG_WARNING, "cl_txintr extra intr\n");
 		return 0;
@@ -1481,80 +1362,83 @@ cl_txintr(arg)
 	sc->sc_txintrcnt.ev_count++;
 
 	channel = tir & 0x03;
-	cmr     = sc->cl_reg->cl_cmr;
-
 	sc->sc_cl[channel].txcnt ++;
 
+	cmr = bus_space_read_1(iot, ioh, CL_CMR);
+
 	tp = sc->sc_cl[channel].tty;
 	if (tp == NULL || (tp->t_state & TS_ISOPEN) == 0) {
-		sc->cl_reg->cl_ier = sc->cl_reg->cl_ier & ~0x3;
-		sc->cl_reg->cl_teoir = 0x08;
+		bus_space_write_1(iot, ioh, CL_IER,
+		    bus_space_read_1(iot, ioh, CL_IER) & ~0x03);
+		bus_space_write_1(iot, ioh, CL_TEOIR, 0x08);
 		return 1;
 	}
+
 	switch (cmr & CL_TXMASK) {
 	case CL_TXDMAINT:
-		{
-			u_char dmabsts;
-			int nbuf, busy, resid;
-			void *pbuffer;
-			dmabsts = sc->cl_reg->cl_dmabsts;
-			log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x\n",
-			    channel, dmabsts);
-			nbuf = ((dmabsts & 0x8) >> 3) & 0x1;
-			busy = ((dmabsts & 0x4) >> 2) & 0x1;
-
-			do {
-				pbuffer = sc->sc_cl[channel].tx[nbuf];
-				resid = tp->t_outq.c_cc;
-				cnt = min (CL_BUFSIZE,resid);
-				log(LOG_WARNING, "cl_txintr: resid %x cnt %x pbuf %p\n",
-				    resid, cnt, pbuffer);
-				if (cnt != 0) {
-					cnt = q_to_b(&tp->t_outq, pbuffer, cnt);
-					resid -= cnt;
-					if (nbuf == 0) {
-						sc->cl_reg->cl_atbadru =
-						((u_long) sc->sc_cl[channel].txp[nbuf]) >> 16;
-						sc->cl_reg->cl_atbadrl =
-						((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff;
-						sc->cl_reg->cl_atbcnt = cnt;
-						sc->cl_reg->cl_atbsts = 0x43;
-					} else {
-						sc->cl_reg->cl_btbadru =
-						((u_long) sc->sc_cl[channel].txp[nbuf]) >> 16;
-						sc->cl_reg->cl_btbadrl =
-						((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff;
-						sc->cl_reg->cl_btbcnt = cnt;
-						sc->cl_reg->cl_btbsts = 0x43;
-					}
-					teoir = 0x08;
+	{
+		u_int8_t dmabsts;
+		int nbuf, busy, resid;
+		void *pbuffer;
+
+		dmabsts = bus_space_read_1(iot, ioh, CL_DMABSTS);
+		nbuf = ((dmabsts & 0x8) >> 3) & 0x1;
+		busy = ((dmabsts & 0x4) >> 2) & 0x1;
+
+		do {
+			pbuffer = sc->sc_cl[channel].tx[nbuf];
+			resid = tp->t_outq.c_cc;
+			cnt = min (CL_BUFSIZE,resid);
+			log(LOG_WARNING, "cl_txintr: resid %x cnt %x pbuf %p\n",
+			    resid, cnt, pbuffer);
+			if (cnt != 0) {
+				cnt = q_to_b(&tp->t_outq, pbuffer, cnt);
+				resid -= cnt;
+				if (nbuf == 0) {
+					bus_space_write_2(iot, ioh, CL_ATBADRU,
+					    ((u_long)sc->sc_cl[channel].txp[nbuf]) >> 16);
+					bus_space_write_2(iot, ioh, CL_ATBADRL,
+					    ((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff);
+					bus_space_write_2(iot, ioh, CL_ATBCNT,
+					    cnt);
+					bus_space_write_1(iot, ioh, CL_ATBSTS,
+					    0x43);
 				} else {
-					teoir = 0x08;
-					if (tp->t_state & TS_BUSY) {
-						tp->t_state &= ~(TS_BUSY | TS_FLUSH);
-						if (tp->t_state & TS_ASLEEP) {
-							tp->t_state &= ~TS_ASLEEP;
-							wakeup((caddr_t) &tp->t_outq);
-						}
-						selwakeup(&tp->t_wsel);
+					bus_space_write_2(iot, ioh, CL_BTBADRU,
+					    ((u_long)sc->sc_cl[channel].txp[nbuf]) >> 16);
+					bus_space_write_2(iot, ioh, CL_BTBADRL,
+					    ((u_long) sc->sc_cl[channel].txp[nbuf]) & 0xffff);
+					bus_space_write_2(iot, ioh, CL_BTBCNT,
+					    cnt);
+					bus_space_write_1(iot, ioh, CL_BTBSTS,
+					    0x43);
+				}
+				teoir = 0x08;
+			} else {
+				teoir = 0x08;
+				if (tp->t_state & TS_BUSY) {
+					tp->t_state &= ~(TS_BUSY | TS_FLUSH);
+					if (tp->t_state & TS_ASLEEP) {
+						tp->t_state &= ~TS_ASLEEP;
+						wakeup((caddr_t) &tp->t_outq);
 					}
-					sc->cl_reg->cl_ier = sc->cl_reg->cl_ier & ~0x3;
+					selwakeup(&tp->t_wsel);
 				}
-				nbuf = ~nbuf & 0x1;
-				busy--;
-			} while (resid != 0 && busy != -1);/* if not busy do other buffer */
-			log(LOG_WARNING, "cl_txintr: done\n");
-		}
+				bus_space_write_1(iot, ioh, CL_IER,
+				    bus_space_read_1(iot, ioh, CL_IER) & ~0x03);
+			}
+			nbuf = ~nbuf & 0x1;
+			busy--;
+		} while (resid != 0 && busy != -1);/* if not busy do other buffer */
+	}
 		break;
 	case CL_TXINTR:
-		max = sc->cl_reg->cl_tftc;
-		cnt = min ((int)max,tp->t_outq.c_cc);
+		max = bus_space_read_1(iot, ioh, CL_TFTC);
+		cnt = min((int)max,tp->t_outq.c_cc);
 		if (cnt != 0) {
 			cnt = q_to_b(&tp->t_outq, buffer, cnt);
 			empty = 0;
-			for (tptr = buffer; tptr < &buffer[cnt]; tptr++) {
-				sc->cl_reg->cl_tdr = *tptr;
-			}
+			bus_space_write_multi_1(iot, ioh, CL_TDR, buffer, cnt);
 			teoir = 0x00;
 		} else {
 			if (empty > 5 && ((empty % 20000 )== 0)) {
@@ -1571,7 +1455,8 @@ cl_txintr(arg)
 				}
 				selwakeup(&tp->t_wsel);
 			}
-			sc->cl_reg->cl_ier = sc->cl_reg->cl_ier & ~0x3;
+			bus_space_write_1(iot, ioh, CL_IER,
+			    bus_space_read_1(iot, ioh, CL_IER) & ~0x03);
 		}
 		break;
 	default:
@@ -1579,7 +1464,7 @@ cl_txintr(arg)
 		/* we probably will go to hell quickly now */
 		teoir = 0x08;
 	}
-	sc->cl_reg->cl_teoir = teoir;
+	bus_space_write_1(iot, ioh, CL_TEOIR, teoir);
 	return 1;
 }
 
@@ -1588,34 +1473,38 @@ cl_rxintr(arg)
 	void *arg;
 {
 	struct clsoftc *sc = arg;
-
-	u_char rir, channel, cmr, risrl;
-	u_char fifocnt;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t rir, channel, cmr, risrl;
+	u_int8_t fifocnt;
 	struct tty *tp;
 	int i;
-	u_char reoir;
+	u_int8_t reoir;
 	u_char buffer[CL_FIFO_MAX +1];
 
-	rir = sc->cl_reg->cl_rir;
-	if((rir & 0x40) == 0x0) {
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
+
+	rir = bus_space_read_1(iot, ioh, CL_RIR);
+	if ((rir & 0x40) == 0x0) {
 		/* only if intr is not shared ??? */
 		log(LOG_WARNING, "cl_rxintr extra intr\n");
 		return 0;
 	}
 	sc->sc_rxintrcnt.ev_count++;
 	channel = rir & 0x3;
-	cmr = sc->cl_reg->cl_cmr;
+	cmr = bus_space_read_1(iot, ioh, CL_CMR);
 	reoir = 0x08;
 
 	sc->sc_cl[channel].rxcnt ++;
-	risrl = sc->cl_reg->cl_risrl;
+	risrl = bus_space_read_1(iot, ioh, CL_RISRL);
 	if (risrl & 0x80) {
 		/* timeout, no characters */
 		reoir = 0x08;
 	} else
 	/* We don't need no sinkin special characters */
 	if (risrl & 0x08) {
-		cl_overflow (sc, channel, (long *)&sc->sc_fotime, "fifo");
+		cl_overflow(sc, channel, (long *)&sc->sc_fotime, "fifo");
 		reoir = 0x08;
 	} else
 	if (risrl & 0x04) {
@@ -1633,94 +1522,79 @@ cl_rxintr(arg)
 
 	switch (cmr & CL_RXMASK) {
 	case CL_RXDMAINT:
-		{
-			int nbuf;
-			u_short cnt;
-			int bufcomplete;
-			u_char status, dmabsts;
-			u_char risrh = sc->cl_reg->cl_risrh;
-			dmabsts = sc->cl_reg->cl_dmabsts;
-#ifdef DMA_DEBUG
-log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x risrl %x risrh %x\n",
-	channel, dmabsts, risrl, risrh);
-#endif
-			nbuf = (risrh & 0x08) ? 1 : 0;
-			bufcomplete = (risrh & 0x20) ? 1 : 0;
-			if (nbuf == 0) {
-				cnt  = sc->cl_reg->cl_arbcnt;
-				status =  sc->cl_reg->cl_arbsts;
-			} else {
-				cnt  = sc->cl_reg->cl_brbcnt;
-				status =  sc->cl_reg->cl_brbsts;
-			}
-#ifdef DMA_DEBUG
-			log(LOG_WARNING, "cl_rxintr: 1channel %x buf %x cnt %x status %x\n",
-			    channel, nbuf, cnt, status);
-#endif
+	{
+		int nbuf;
+		u_int16_t cnt;
+		int bufcomplete;
+		u_int8_t status, dmabsts;
+		u_int8_t risrh;
+
+		risrh = bus_space_read_1(iot, ioh, CL_RISRH);
+		dmabsts = bus_space_read_1(iot, ioh, CL_DMABSTS);
+		nbuf = (risrh & 0x08) ? 1 : 0;
+		bufcomplete = (risrh & 0x20) ? 1 : 0;
+		if (nbuf == 0) {
+			cnt = bus_space_read_2(iot, ioh, CL_ARBCNT);
+			status = bus_space_read_1(iot, ioh, CL_ARBSTS);
+		} else {
+			cnt = bus_space_read_2(iot, ioh, CL_BRBCNT);
+			status = bus_space_read_1(iot, ioh, CL_BRBSTS);
+		}
 #if USE_BUFFER
-			cl_appendbufn(sc, channel, sc->rx[nbuf], cnt);
+		cl_appendbufn(sc, channel, sc->rx[nbuf], cnt);
 #else
+		{
+			int i;
+			u_char *pbuf;
+
+			tp = sc->sc_cl[channel].tty;
+			pbuf = sc->sc_cl[channel].rx[nbuf];
+			/* this should be done at off level */
 			{
-				int i;
-				u_char *pbuf;
-				tp = sc->sc_cl[channel].tty;
-				pbuf = sc->sc_cl[channel].rx[nbuf];
-				/* this should be done at off level */
-				{
-					u_short rcbadru, rcbadrl;
-					u_char arbsts, brbsts;
-					u_char *pbufs, *pbufe;
-					rcbadru = sc->cl_reg->cl_rcbadru;
-					rcbadrl = sc->cl_reg->cl_rcbadrl;
-					arbsts =  sc->cl_reg->cl_arbsts;
-					brbsts =  sc->cl_reg->cl_brbsts;
-					pbufs = sc->sc_cl[channel].rxp[nbuf];
-					pbufe = (u_char *)(((u_long)rcbadru << 16) | (u_long)rcbadrl);
-					cnt = pbufe - pbufs;
-#ifdef DMA_DEBUG
-					log(LOG_WARNING, "cl_rxintr: rcbadru %x rcbadrl %x arbsts %x brbsts %x cnt %x\n",
-					    rcbadru, rcbadrl, arbsts, brbsts, cnt);
-#endif
-#ifdef DMA_DEBUG1
-					log(LOG_WARNING, "cl_rxintr: buf %x cnt %x\n",
-					    nbuf, cnt);
-#endif
-				}
-				reoir = 0x0 | (bufcomplete) ? 0 : 0xd0;
-				sc->cl_reg->cl_reoir = reoir;
-#ifdef DMA_DEBUG
-				log(LOG_WARNING, "cl_rxintr: reoir %x\n", reoir);
-#endif
-				delay(10); /* give the chip a moment */
-#ifdef DMA_DEBUG
-				log(LOG_WARNING, "cl_rxintr: 2channel %x buf %x cnt %x status %x\n",
-				    channel, nbuf, cnt, status);
-#endif
-				for (i = 0; i < cnt; i++) {
-					u_char c;
-					c = pbuf[i];
-					(*linesw[tp->t_line].l_rint)(c,tp);
-				}
+				u_int16_t rcbadru, rcbadrl;
+				u_int8_t arbsts, brbsts;
+				u_char *pbufs, *pbufe;
+
+				rcbadru = bus_space_read_2(iot, ioh,
+				    CL_RCBADRU);
+				rcbadrl = bus_space_read_2(iot, ioh,
+				    CL_RCBADRL);
+				arbsts = bus_space_read_1(iot, ioh, CL_ARBSTS);
+				brbsts = bus_space_read_1(iot, ioh, CL_BRBSTS);
+				pbufs = sc->sc_cl[channel].rxp[nbuf];
+				pbufe = (u_char *)(((u_long)rcbadru << 16) | (u_long)rcbadrl);
+				cnt = pbufe - pbufs;
+			}
+			reoir = 0x0 | (bufcomplete) ? 0 : 0xd0;
+			bus_space_write_1(iot, ioh, CL_REOIR, reoir);
+
+			DELAY(10); /* give the chip a moment */
+
+			for (i = 0; i < cnt; i++) {
+				u_char c;
+				c = pbuf[i];
+				(*linesw[tp->t_line].l_rint)(c,tp);
+			}
 			/* this should be done at off level */
-				if (nbuf == 0) {
-					sc->cl_reg->cl_arbcnt = CL_BUFSIZE;
-					sc->cl_reg->cl_arbsts = 0x01;
-				} else {
-					sc->cl_reg->cl_brbcnt = CL_BUFSIZE;
-					sc->cl_reg->cl_brbsts = 0x01;
-				}
+			if (nbuf == 0) {
+				bus_space_write_2(iot, ioh, CL_ARBCNT,
+				    CL_BUFSIZE);
+				bus_space_write_2(iot, ioh, CL_ARBSTS, 0x01);
+			} else {
+				bus_space_write_2(iot, ioh, CL_BRBCNT,
+				    CL_BUFSIZE);
+				bus_space_write_2(iot, ioh, CL_BRBSTS, 0x01);
 			}
-#endif
 		}
-		sc->cl_reg->cl_reoir = reoir;
+#endif
+	}
+		bus_space_write_1(iot, ioh, CL_REOIR, reoir);
 		break;
 	case CL_RXINTR:
-		fifocnt = sc->cl_reg->cl_rfoc;
+		fifocnt = bus_space_read_1(iot, ioh, CL_RFOC);
 		tp = sc->sc_cl[channel].tty;
-		for (i = 0; i < fifocnt; i++) {
-			buffer[i] = sc->cl_reg->cl_rdr;
-		}
-		if (NULL == tp) {
+		bus_space_read_multi_1(iot, ioh, CL_RDR, buffer, fifocnt);
+		if (tp == NULL) {
 			/* if the channel is not configured,
 			 * dont send characters upstream.
 			 * also fix problem with NULL dereference
@@ -1729,7 +1603,7 @@ log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x risrl %x risrh %x\n",
 			break;
 		}
 
-		sc->cl_reg->cl_reoir = reoir;
+		bus_space_write_1(iot, ioh, CL_REOIR, reoir);
 		for (i = 0; i < fifocnt; i++) {
 			u_char c;
 			c = buffer[i];
@@ -1746,7 +1620,7 @@ log(LOG_WARNING, "cl_txintr: DMAMODE channel %x dmabsts %x risrl %x risrh %x\n",
 	default:
 		log(LOG_WARNING, "cl_rxintr unknown mode %x\n", cmr);
 		/* we probably will go to hell quickly now */
-		sc->cl_reg->cl_reoir = 0x08;
+		bus_space_write_1(iot, ioh, CL_REOIR, 0x08);
 	}
 	return 1;
 }
@@ -1796,92 +1670,77 @@ cl_break(sc, channel)
 
 #ifdef DEBUG
 void
-cl_dumpport(channel)
-	int channel;
+cl_dumpport(struct clsoftc *sc, int channel)
 {
-	u_char	livr, cmr, cor1, cor2, cor3, cor4, cor5, cor6, cor7,
-		schr1, schr2, schr3, schr4, scrl, scrh, lnxt,
-		rbpr, rcor, tbpr, tcor, rpilr, rir, tpr, ier, ccr,
-		dmabsts, arbsts, brbsts, atbsts, btbsts,
-		csr, rts, dtr, rtprl, rtprh;
-	void *volatile parbadru, *volatile parbadrl,
-	     *volatile parbsts, *volatile parbcnt;
-	u_short rcbadru, rcbadrl, arbadru, arbadrl, arbcnt,
-		brbadru, brbadrl, brbcnt;
-	u_short tcbadru, tcbadrl, atbadru, atbadrl, atbcnt,
-		btbadru, btbadrl, btbcnt;
-	struct clsoftc *sc;
-
-	struct clreg *volatile cl_reg;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	u_int8_t livr, cmr, cor1, cor2, cor3, cor4, cor5, cor6, cor7,
+	    schr1, schr2, schr3, schr4, scrl, scrh, lnxt,
+	    rbpr, rcor, tbpr, tcor, rpilr, rir, tpr, ier, ccr,
+	    dmabsts, arbsts, brbsts, atbsts, btbsts,
+	    csr, rts, dtr, rtprl, rtprh;
+	u_int16_t rcbadru, rcbadrl, arbadru, arbadrl, arbcnt,
+	    brbadru, brbadrl, brbcnt;
+	u_int16_t tcbadru, tcbadrl, atbadru, atbadrl, atbcnt,
+	    btbadru, btbadrl, btbcnt;
 	int s;
 
-	cl_reg = cl_cons.cl_vaddr;
-
-	sc = (struct clsoftc *) cl_cd.cd_devs[0];
+	iot = sc->sc_iot;
+	ioh = sc->sc_ioh;
 
 	s = splcl();
-	cl_reg->cl_car	= (u_char) channel;
-	livr = cl_reg->cl_livr;
-	cmr = cl_reg->cl_cmr;
-	cor1 = cl_reg->cl_cor1;
-	cor2 = cl_reg->cl_cor2;
-	cor3 = cl_reg->cl_cor3;
-	cor4 = cl_reg->cl_cor4;
-	cor5 = cl_reg->cl_cor5;
-	cor6 = cl_reg->cl_cor6;
-	cor7 = cl_reg->cl_cor7;
-	schr1 = cl_reg->cl_schr1;
-	schr2 = cl_reg->cl_schr2;
-	schr3 = cl_reg->cl_schr3;
-	schr4 = cl_reg->cl_schr4;
-	scrl = cl_reg->cl_scrl;
-	scrh = cl_reg->cl_scrh;
-	lnxt = cl_reg->cl_lnxt;
-	rbpr = cl_reg->cl_rbpr;
-	rcor = cl_reg->cl_rcor;
-	tbpr = cl_reg->cl_tbpr;
-	rpilr = cl_reg->cl_rpilr;
-	rir = cl_reg->cl_rir;
-	ier = cl_reg->cl_ier;
-	ccr = cl_reg->cl_ccr;
-	tcor = cl_reg->cl_tcor;
-	csr = cl_reg->cl_csr;
-	tpr = cl_reg->cl_tpr;
-	rts = cl_reg->cl_msvr_rts;
-	dtr = cl_reg->cl_msvr_dtr;
-	rtprl = cl_reg->cl_rtprl;
-	rtprh = cl_reg->cl_rtprh;
-	dmabsts = cl_reg->cl_dmabsts;
-	tcbadru = cl_reg->cl_tcbadru;
-	tcbadrl = cl_reg->cl_tcbadrl;
-	rcbadru = cl_reg->cl_rcbadru;
-	rcbadrl = cl_reg->cl_rcbadrl;
-
-	parbadru = &(cl_reg->cl_arbadru);
-	parbadrl = &(cl_reg->cl_arbadrl);
-	parbcnt  = &(cl_reg->cl_arbcnt);
-	parbsts  = &(cl_reg->cl_arbsts);
-
-	arbadru = cl_reg->cl_arbadru;
-	arbadrl = cl_reg->cl_arbadrl;
-	arbcnt  = cl_reg->cl_arbcnt;
-	arbsts  = cl_reg->cl_arbsts;
-
-	brbadru = cl_reg->cl_brbadru;
-	brbadrl = cl_reg->cl_brbadrl;
-	brbcnt  = cl_reg->cl_brbcnt;
-	brbsts  = cl_reg->cl_brbsts;
-
-	atbadru = cl_reg->cl_atbadru;
-	atbadrl = cl_reg->cl_atbadrl;
-	atbcnt  = cl_reg->cl_atbcnt;
-	atbsts  = cl_reg->cl_atbsts;
-
-	btbadru = cl_reg->cl_btbadru;
-	btbadrl = cl_reg->cl_btbadrl;
-	btbcnt  = cl_reg->cl_btbcnt;
-	btbsts  = cl_reg->cl_btbsts;
-
+	bus_space_write_1(iot, ioh, CL_CAR, channel);
+	livr = bus_space_read_1(iot, ioh, CL_LIVR);
+	cmr = bus_space_read_1(iot, ioh, CL_CMR);
+	cor1 = bus_space_read_1(iot, ioh, CL_COR1);
+	cor2 = bus_space_read_1(iot, ioh, CL_COR2);
+	cor3 = bus_space_read_1(iot, ioh, CL_COR3);
+	cor4 = bus_space_read_1(iot, ioh, CL_COR4);
+	cor5 = bus_space_read_1(iot, ioh, CL_COR5);
+	cor6 = bus_space_read_1(iot, ioh, CL_COR6);
+	cor7 = bus_space_read_1(iot, ioh, CL_COR7);
+	schr1 = bus_space_read_1(iot, ioh, CL_SCHR1);
+	schr2 = bus_space_read_1(iot, ioh, CL_SCHR2);
+	schr3 = bus_space_read_1(iot, ioh, CL_SCHR3);
+	schr4 = bus_space_read_1(iot, ioh, CL_SCHR4);
+	scrl = bus_space_read_1(iot, ioh, CL_SCRL);
+	scrh = bus_space_read_1(iot, ioh, CL_SCRH);
+	lnxt = bus_space_read_1(iot, ioh, CL_LNXT);
+	rbpr = bus_space_read_1(iot, ioh, CL_RBPR);
+	rcor = bus_space_read_1(iot, ioh, CL_RCOR);
+	tbpr = bus_space_read_1(iot, ioh, CL_TBPR);
+	rpilr = bus_space_read_1(iot, ioh, CL_RPILR);
+	rir = bus_space_read_1(iot, ioh, CL_RIR);
+	ier = bus_space_read_1(iot, ioh, CL_IER);
+	ccr = bus_space_read_1(iot, ioh, CL_CCR);
+	tcor = bus_space_read_1(iot, ioh, CL_TCOR);
+	csr = bus_space_read_1(iot, ioh, CL_CSR);
+	tpr = bus_space_read_1(iot, ioh, CL_TPR);
+	rts = bus_space_read_1(iot, ioh, CL_MSVR_RTS);
+	dtr = bus_space_read_1(iot, ioh, CL_MSVR_DTR);
+	rtprl = bus_space_read_1(iot, ioh, CL_RTPRL);
+	rtprh = bus_space_read_1(iot, ioh, CL_RTPRH);
+	dmabsts = bus_space_read_1(iot, ioh, CL_DMABSTS);
+	tcbadru = bus_space_read_2(iot, ioh, CL_TCBADRU);
+	tcbadrl = bus_space_read_2(iot, ioh, CL_TCBADRL);
+	rcbadru = bus_space_read_2(iot, ioh, CL_RCBADRU);
+	rcbadrl = bus_space_read_2(iot, ioh, CL_RCBADRL);
+	arbadru = bus_space_read_2(iot, ioh, CL_ARBADRU);
+	arbadrl = bus_space_read_2(iot, ioh, CL_ARBADRL);
+	arbcnt  = bus_space_read_2(iot, ioh, CL_ARBCNT);
+	arbsts  = bus_space_read_1(iot, ioh, CL_ARBSTS);
+	brbadru = bus_space_read_2(iot, ioh, CL_BRBADRU);
+	brbadrl = bus_space_read_2(iot, ioh, CL_BRBADRL);
+	brbcnt  = bus_space_read_2(iot, ioh, CL_BRBCNT);
+	brbsts  = bus_space_read_1(iot, ioh, CL_BRBSTS);
+	atbadru = bus_space_read_2(iot, ioh, CL_ATBADRU);
+	atbadrl = bus_space_read_2(iot, ioh, CL_ATBADRL);
+	atbcnt  = bus_space_read_2(iot, ioh, CL_ATBCNT);
+	atbsts  = bus_space_read_1(iot, ioh, CL_ATBSTS);
+	btbadru = bus_space_read_2(iot, ioh, CL_BTBADRU);
+	btbadrl = bus_space_read_2(iot, ioh, CL_BTBADRL);
+	btbcnt  = bus_space_read_2(iot, ioh, CL_BTBCNT);
+	btbsts  = bus_space_read_1(iot, ioh, CL_BTBSTS);
 	splx(s);
 
 	printf("{ port %x livr %x cmr %x\n",
@@ -1904,8 +1763,6 @@ cl_dumpport(channel)
 		sc->sc_cl[channel].rxcnt, sc->sc_cl[channel].txcnt);
 	printf("dmabsts %x, tcbadru %x, tcbadrl %x, rcbadru %x, rcbadrl %x,\n",
 		dmabsts,    tcbadru,    tcbadrl,    rcbadru,    rcbadrl );
-	printf("parbadru %x, parbadrl %x, parbcnt %x, parbsts %x\n",
-		parbadru,    parbadrl,    parbcnt,    parbsts);
 	printf("arbadru %x, arbadrl %x, arbcnt %x, arbsts %x\n",
 		arbadru,    arbadrl,    arbcnt,    arbsts);
 	printf("brbadru %x, brbadrl %x, brbcnt %x, brbsts %x\n",