diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2006-04-26 21:06:09 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2006-04-26 21:06:09 +0000 |
| commit | bf998542c38e5272e4f15b1d26c81803d5c62017 (patch) | |
| tree | 8b2106296b25811ecc50fd8a325f7d33efa7545e /sys/arch/mvme88k/dev/if_lereg.h | |
| parent | cfa0db19831c29b2faddf07a6dcae0ab1f1708d6 (diff) | |
The dual-ported memory of the MVME376 boards is D32 addressable, say the
documentation, so we can use the MI {zero,copy{to,from}}buf_contig
callbacks, which rely upon bcopy() and bzero(), instead of their d16_bcopy()
and d16_bzero() equivalents. No functional change, except an unnoticeable
speedup.
Diffstat (limited to 'sys/arch/mvme88k/dev/if_lereg.h')
| -rw-r--r-- | sys/arch/mvme88k/dev/if_lereg.h | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/sys/arch/mvme88k/dev/if_lereg.h b/sys/arch/mvme88k/dev/if_lereg.h index 40ffe14dbdd..6e76b8d3f0a 100644 --- a/sys/arch/mvme88k/dev/if_lereg.h +++ b/sys/arch/mvme88k/dev/if_lereg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_lereg.h,v 1.3 2004/05/17 08:36:22 miod Exp $ */ +/* $OpenBSD: if_lereg.h,v 1.4 2006/04/26 21:06:08 miod Exp $ */ /*- * Copyright (c) 1982, 1992, 1993 @@ -45,11 +45,11 @@ struct vlereg1 { volatile u_int16_t ler1_ear; /* ethernet address register */ }; -#define NVRAM_EN 0x0008 /* NVRAM enable bit */ -#define INTR_EN 0x0010 /* Interrupt enable bit */ -#define PARITYB 0x0020 /* Parity clear bit */ -#define HW_RS 0x0040 /* Hardware reset bit */ -#define SYSFAILB 0x0080 /* SYSFAIL bit */ +#define NVRAM_EN 0x0008 /* NVRAM enable bit (active low) */ +#define INTR_EN 0x0010 /* interrupt enable bit (active low) */ +#define PARITYB 0x0020 /* parity error clear bit */ +#define HW_RS 0x0040 /* hardware reset bit (active low) */ +#define SYSFAILB 0x0080 /* SYSFAIL bit */ #define NVRAM_RWEL 0xe0 /* Reset write enable latch */ #define NVRAM_STO 0x60 /* Store ram to eeprom */ @@ -76,13 +76,9 @@ struct vlereg1 { #define DISABLE_INTR WRITE_CSR_OR(INTR_EN) #define RESET_HW \ do { \ - WRITE_CSR_AND(0xff00); \ WRITE_CSR_AND(HW_RS); \ CDELAY; \ } while (0) #define SET_VEC(x) \ - do { \ - reg1->ler1_vec = 0; \ - reg1->ler1_vec |= (x); \ - } while (0) + reg1->ler1_vec |= (x) #define SYSFAIL_CL WRITE_CSR_AND(SYSFAILB) |