diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2004-08-24 22:01:30 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2004-08-24 22:01:30 +0000 |
| commit | 124a6ef5003c8d2756817de2c8e82bdf6a4244fc (patch) | |
| tree | 2557b69bfe3598f84541d6593cf84711a3f8b59d /sys/arch/mvme88k/dev | |
| parent | f48deeeae461e0e99e6c9957fc61b5bc6d01ce15 (diff) | |
The#@$#%^&}1 z8536 timers runs at PCLK/2, hence 2MHz. Compensate, since
the code assumes 1MHz timers.
Diffstat (limited to 'sys/arch/mvme88k/dev')
| -rw-r--r-- | sys/arch/mvme88k/dev/clock.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/sys/arch/mvme88k/dev/clock.c b/sys/arch/mvme88k/dev/clock.c index deca0706c91..b964137b67c 100644 --- a/sys/arch/mvme88k/dev/clock.c +++ b/sys/arch/mvme88k/dev/clock.c @@ -1,4 +1,4 @@ -/* $OpenBSD: clock.c,v 1.37 2004/08/24 07:42:04 miod Exp $ */ +/* $OpenBSD: clock.c,v 1.38 2004/08/24 22:01:29 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * Copyright (c) 1995 Theo de Raadt @@ -81,7 +81,6 @@ #include <machine/autoconf.h> #include <machine/bugio.h> #include <machine/cpu.h> -#include <machine/cmmu.h> /* DMA_CACHE_SYNC, etc... */ #include "pcctwo.h" #if NPCCTWO > 0 @@ -139,10 +138,12 @@ u_int8_t prof_reset; u_int8_t stat_reset; #endif +#if NSYSCON > 0 struct simplelock cio_lock; #define CIO_LOCK simple_lock(&cio_lock) #define CIO_UNLOCK simple_unlock(&cio_lock) +#endif /* * Statistics clock interval and variance, in usec. Variance must be a @@ -247,7 +248,6 @@ sbc_initclock(void) PCC2_TCTL_CEN | PCC2_TCTL_COC | PCC2_TCTL_COVF; *(volatile u_int8_t *)(OBIO_START + PCC2_BASE + PCCTWO_T1ICR) = prof_reset; - } /* @@ -446,6 +446,7 @@ m188_statintr(void *eframe) newint = statmin + r; /* Load time constant CTC #1 */ + newint <<= 1; /* CT1 runs at PCLK/2, hence 2MHz */ write_cio(CIO_CT1MSB, (newint & 0xff00) >> 8); write_cio(CIO_CT1LSB, newint & 0xff); @@ -481,15 +482,13 @@ m188_initstatclock(void) statmin = statint - (statvar >> 1); } -#define CIO_CNTRL 0xfff8300c - /* Write CIO register */ void write_cio(int reg, u_int val) { int s; volatile int i; - int *volatile cio_ctrl = (int *volatile)CIO_CNTRL; + int *volatile cio_ctrl = (int *volatile)CIO_CTRL; s = splclock(); CIO_LOCK; @@ -511,7 +510,7 @@ read_cio(int reg) { int c, s; volatile int i; - int *volatile cio_ctrl = (int *volatile)CIO_CNTRL; + int *volatile cio_ctrl = (int *volatile)CIO_CTRL; s = splclock(); CIO_LOCK; @@ -563,6 +562,7 @@ m188_cio_init(unsigned period) write_cio(CIO_PDCB, 0xff); /* set port B to input */ /* Load time constant CTC #1 */ + period <<= 1; /* CT1 runs at PCLK/2, hence 2MHz */ write_cio(CIO_CT1MSB, (period & 0xff00) >> 8); write_cio(CIO_CT1LSB, period & 0xff); |