Preliminary switch to an mvme88k bus_space world. Not all drivers have been

converted yet, and they rely upon some linear mappings provided by bus_space.

In order to not impact performance, almost all the bus_space accesses go
through macros and inline functions. This currently restricts us to D16 and
D32 access modes, which are selected at compilation time. Since there are no
plans to support D8 vme devices in the future, this is acceptable for now.

This makes the "len" locator for vme devices go away, and allows to simplify
some code which was using the pcctwo device, and will now directly access
hardware which is known to exist, rather than wait until the device is
attached.

While there, try to enforce more interrupt vector number checks, since these
changes pointed out that dart(4) had been working correctly so far by sheer
luck only.

1 files changed, 47 insertions, 47 deletions

diff --git a/sys/arch/mvme88k/include/m88410.h b/sys/arch/mvme88k/include/m88410.h
index ca22e47727b..2c10126d87e 100644
--- a/sys/arch/mvme88k/include/m88410.h
+++ b/sys/arch/mvme88k/include/m88410.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88410.h,v 1.9 2004/04/14 20:16:51 miod Exp $ */
+/*	$OpenBSD: m88410.h,v 1.10 2004/04/24 19:51:48 miod Exp $ */
 /*
  * Copyright (c) 2001 Steve Murphree, Jr.
  * All rights reserved.
@@ -30,44 +30,43 @@
  *
  */
 
-#ifndef	__MACHINE_M88410_H__
-#define	__MACHINE_M88410_H__
+#ifndef	__M88410_H__
+#define	__M88410_H__
+
+#ifdef _KERNEL
 
 /*
- *	mc88410 External Cache Controller definitions
+ *	MC88410 External Cache Controller definitions
  *	This is only available on MVME197DP/SP models.
  */
 
-#ifndef	_LOCORE
-
 #include <machine/asm_macro.h>
 #include <machine/psl.h>
-#ifdef _KERNEL
 #include <mvme88k/dev/busswreg.h>
-#endif
 
-#define XCC_NOP		"0x0"
-#define XCC_FLUSH_PAGE	"0x1"
-#define XCC_FLUSH_ALL	"0x2"
-#define XCC_INVAL_ALL	"0x3"
-#define XCC_ADDR	0xFF800000
+#define XCC_NOP		"0x00"
+#define XCC_FLUSH_PAGE	"0x01"
+#define XCC_FLUSH_ALL	"0x02"
+#define XCC_INVAL_ALL	"0x03"
+#define XCC_ADDR	0xff800000
 
 static __inline__ void
 mc88410_flush_page(paddr_t physaddr)
 {
 	paddr_t xccaddr = XCC_ADDR | (physaddr >> PGSHIFT);
         m88k_psr_type psr;
-	struct bussw_reg *bs = (struct bussw_reg *)BS_BASE;
-        u_short	bs_gcsr = bs->bs_gcsr;
-	u_short	bs_romcr = bs->bs_romcr;
+	u_int16_t bs_gcsr, bs_romcr;
 
+	bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR);
+	bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR);
 	psr = get_psr();
 	/* mask misaligned exceptions */
 	set_psr(psr | PSR_MXM);
 	/* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
-	bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1) ;
-	/* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */
-	bs->bs_gcsr |= BS_GCSR_XCC;
+	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) =
+	    bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1);
+	/* set XCC bit in GCSR (0xff8xxxxx now decodes to mc88410) */
+	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr | BS_GCSR_XCC;
 
 	/* load the value of upper32 into r2 */
 	__asm__ __volatile__("or   r2,r0," XCC_FLUSH_PAGE);
@@ -80,88 +79,91 @@ mc88410_flush_page(paddr_t physaddr)
 	__asm__ __volatile__("st.d r2,r4,0");
 
 	/* spin until the operation starts */
-	while ((bs->bs_xccr & BS_XCC_FBSY) == 0)
+	while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) == 0)
 		;
 
 	/* restore PSR and friends */
         set_psr(psr);
 	flush_pipeline();
-        bs->bs_gcsr = bs_gcsr;
-	bs->bs_romcr = bs_romcr;
+	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr;
+	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr;
 }
 
 static __inline__ void
 mc88410_flush(void)
 {
         m88k_psr_type psr;
-	struct bussw_reg *bs = (struct bussw_reg *)BS_BASE;
-        u_short	bs_gcsr = bs->bs_gcsr;
-	u_short	bs_romcr = bs->bs_romcr;
+	u_int16_t bs_gcsr, bs_romcr;
 
+	bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR);
+	bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR);
 	psr = get_psr();
 	/* mask misaligned exceptions */
 	set_psr(psr | PSR_MXM);
 	/* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
-	bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1) ;
+	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) =
+	    bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1);
 	/* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */
-	bs->bs_gcsr |= BS_GCSR_XCC;
+	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr | BS_GCSR_XCC;
 
 	/* load the value of upper32 into r2 */
 	__asm__ __volatile__("or   r2,r0," XCC_FLUSH_ALL);
 	/* load the value of lower32 into r3 (always 0) */
 	__asm__ __volatile__("or   r3,r0,r0");
 	/* load the value of xccaddr into r4 */
-	__asm__ __volatile__("or.u r5,r0,hi16(0xFF800000)");
-	__asm__ __volatile__("or   r4,r5,r0");	/* r4 is now 0xFF800000 */
+	__asm__ __volatile__("or.u r5,r0,hi16(0xff800000)");
+	__asm__ __volatile__("or   r4,r5,r0");
 	/* make the double write. bang! */
 	__asm__ __volatile__("st.d r2,r4,0");
 
 	/* spin until the operation starts */
-	while ((bs->bs_xccr & BS_XCC_FBSY) == 0)
+	while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) == 0)
 		;
 
 	/* restore PSR and friends */
         set_psr(psr);
 	flush_pipeline();
-        bs->bs_gcsr = bs_gcsr;
-	bs->bs_romcr = bs_romcr;
+	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr;
+	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr;
 }
 
 static __inline__ void
 mc88410_inval(void)
 {
         m88k_psr_type psr;
-	struct bussw_reg *bs = (struct bussw_reg *)BS_BASE;
-        u_short	bs_gcsr = bs->bs_gcsr;
-	u_short	bs_romcr = bs->bs_romcr;
+	u_int16_t bs_gcsr, bs_romcr;
+
+	bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR);
+	bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR);
 
 	psr = get_psr();
 	/* mask misaligned exceptions */
 	set_psr(psr | PSR_MXM);
 	/* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
-	bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1) ;
+	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) =
+	    bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1);
 	/* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */
-	bs->bs_gcsr |= BS_GCSR_XCC;
+	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr | BS_GCSR_XCC;
 
 	/* load the value of upper32 into r2 */
 	__asm__ __volatile__("or   r2,r0," XCC_INVAL_ALL);
 	/* load the value of lower32 into r3 (always 0) */
 	__asm__ __volatile__("or   r3,r0,r0");
 	/* load the value of xccaddr into r4 */
-	__asm__ __volatile__("or.u r5,r0,hi16(0xFF800000)");
-	__asm__ __volatile__("or   r4,r5,r0");	/* r4 is now 0xFF800000 */
+	__asm__ __volatile__("or.u r5,r0,hi16(0xff800000)");
+	__asm__ __volatile__("or   r4,r5,r0");
 	/* make the double write. bang! */
 	__asm__ __volatile__("st.d r2,r4,0");
 
 	/* spin until the operation starts */
-	while ((bs->bs_xccr & BS_XCC_FBSY) == 0)
+	while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) == 0)
 		;
 
 	/* restore PSR and friends */
         set_psr(psr);
 	flush_pipeline();
-        bs->bs_gcsr = bs_gcsr;
-	bs->bs_romcr = bs_romcr;
+	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr;
+	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr;
 }
 
 static __inline__ void
@@ -174,11 +176,9 @@ mc88410_sync(void)
 static __inline__ int
 mc88410_present(void)
 {
-	struct bussw_reg *bs = (struct bussw_reg *)BS_BASE;
-
-	return (bs->bs_gcsr & BS_GCSR_B410);
+	return (*(volatile u_int16_t *)(BS_BASE + BS_GCSR)) & BS_GCSR_B410;
 }
 
-#endif	/* _LOCORE */
+#endif	/* _KERNEL */
 
-#endif	/* __MACHINE_M88410_H__ */
+#endif	/* __M88410_H__ */