diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2007-05-14 17:00:41 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2007-05-14 17:00:41 +0000 |
| commit | 1c060e9bbf429ecd1c20e7d6a7ccad995a9dd8cc (patch) | |
| tree | df2be620149ca7c20b41da842a2c51b9eb13abf5 /sys/arch/mvme88k/include | |
| parent | 324e84af407cac6fe6c7ee0d3fed906b9c4e3128 (diff) | |
Work in progress IPI mechanism, currently only implemented on MVME188, to
send clock ticks to secondary processors.
Diffstat (limited to 'sys/arch/mvme88k/include')
| -rw-r--r-- | sys/arch/mvme88k/include/cpu.h | 3 | ||||
| -rw-r--r-- | sys/arch/mvme88k/include/mvme188.h | 14 |
2 files changed, 13 insertions, 4 deletions
diff --git a/sys/arch/mvme88k/include/cpu.h b/sys/arch/mvme88k/include/cpu.h index 0ae4bdd0425..72dc6bb1a64 100644 --- a/sys/arch/mvme88k/include/cpu.h +++ b/sys/arch/mvme88k/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.36 2007/03/22 18:52:39 miod Exp $ */ +/* $OpenBSD: cpu.h,v 1.37 2007/05/14 17:00:40 miod Exp $ */ /* * Copyright (c) 1996 Nivas Madhur * Copyright (c) 1992, 1993 @@ -52,6 +52,7 @@ extern u_int (*md_getipl)(void); extern u_int (*md_setipl)(u_int); extern u_int (*md_raiseipl)(u_int); extern void (*md_init_clocks)(void); +extern void (*md_send_ipi)(int, cpuid_t); struct intrhand { SLIST_ENTRY(intrhand) ih_link; diff --git a/sys/arch/mvme88k/include/mvme188.h b/sys/arch/mvme88k/include/mvme188.h index 3f06ba62e3e..aa13449cf5f 100644 --- a/sys/arch/mvme88k/include/mvme188.h +++ b/sys/arch/mvme88k/include/mvme188.h @@ -1,4 +1,4 @@ -/* $OpenBSD: mvme188.h,v 1.28 2006/11/18 22:53:11 miod Exp $ */ +/* $OpenBSD: mvme188.h,v 1.29 2007/05/14 17:00:40 miod Exp $ */ /* * Copyright (c) 1999 Steve Murphree, Jr. * All rights reserved. @@ -149,8 +149,9 @@ /* hardware irq bits */ #define HW_FAILURE_MASK (IRQ_ABORT | IRQ_ACF | IRQ_ARBTO | IRQ_SF) /* software irq bits */ -#define SOFT_INTERRUPT_MASK (IRQ_SWI7 | IRQ_SWI6 | IRQ_SWI5 | IRQ_SWI4 | \ - IRQ_SWI3 | IRQ_SWI2 | IRQ_SWI1 | IRQ_SWI0) +#define SOFT_INTERRUPT_MASK (IRQ_SWI7 | IRQ_SWI6 | IRQ_SWI5 | IRQ_SWI4) +/* IPI bits (see below) */ +#define IPI_MASK (IRQ_SWI3 | IRQ_SWI2 | IRQ_SWI1 | IRQ_SWI0) /* VME irq bits */ #define VME_INTERRUPT_MASK (IRQ_VME7 | IRQ_VME6 | IRQ_VME5 | IRQ_VME4 | \ IRQ_VME3 | IRQ_VME2 | IRQ_VME1) @@ -186,6 +187,13 @@ (*(volatile u_int *)MVME188_IST & *int_mask_reg[cpu]) /* + * Software interrupts 0 to 3 are used to deliver IPIs to cpu0-3. + * We rely on the fact that the control bits for these interrupts are + * the same in the interrupt registers and the set/clear SWI registers. + */ +#define IPI_BIT(cpuid) (1 << (cpuid)) + +/* * ISTATE and CLRINT register bits */ |