Major changes to get MVME188 working. More header and code cleanups. The

kernel is tested on MVME188A/2P256 and MVME188A/1P64.

9 files changed, 413 insertions, 401 deletions

diff --git a/sys/arch/mvme88k/include/asm.h b/sys/arch/mvme88k/include/asm.h
index a72fcdaf82f..4540ecdc0b9 100644
--- a/sys/arch/mvme88k/include/asm.h
+++ b/sys/arch/mvme88k/include/asm.h
@@ -200,20 +200,19 @@
  *	in a rather precarious state and so special cautions must
  * 	be taken.
  */
-#define FLAG_CPU_FIELD_WIDTH		   4	/* must be <= 12 */
+#define FLAG_CPU_FIELD_WIDTH		2	/* must be <= 12 */
 #define FLAG_IGNORE_DATA_EXCEPTION	5	/* bit number 5  */
-#define FLAG_INTERRUPT_EXCEPTION	   6	/* bit number 6  */
-#define FLAG_ENABLING_FPU		      7	/* bit number 7  */
-#define FLAG_FROM_KERNEL            8  /* bit number 8  */
-#define FLAG_187 		               8	/* bit number 9  */
-#define FLAG_188 		               9	/* bit number 10 */
-#define FLAG_197 		              10	/* bit number 11 */
+#define FLAG_INTERRUPT_EXCEPTION	6	/* bit number 6  */
+#define FLAG_ENABLING_FPU		7	/* bit number 7  */
+#define FLAG_FROM_KERNEL		8	/* bit number 8  */
+#define FLAG_187			9	/* bit number 9  */
+#define FLAG_188			10	/* bit number 10 */
+#define FLAG_197			11	/* bit number 11 */
 
 /* REGister OFFset into the E.F. (exception frame) */
 #define REG_OFF(reg_num)  ((reg_num) * 4) /* (num * sizeof(register int))  */
 #define GENREG_OFF(num)	(REG_OFF(EF_R0 + (num))) /* GENeral REGister OFFset */
 
-
 #define GENERAL_BREATHING_ROOM	/* arbitrarily */ 200
 #define KERNEL_STACK_BREATHING_ROOM 	\
 	(GENERAL_BREATHING_ROOM + SIZEOF_STRUCT_PCB + SIZEOF_STRUCT_UTHREAD)
diff --git a/sys/arch/mvme88k/include/asm_macro.h b/sys/arch/mvme88k/include/asm_macro.h
index c437fb7a0cf..1ece66a5ab7 100644
--- a/sys/arch/mvme88k/include/asm_macro.h
+++ b/sys/arch/mvme88k/include/asm_macro.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: asm_macro.h,v 1.8 2001/01/15 19:50:38 deraadt Exp $ */
+/*	$OpenBSD: asm_macro.h,v 1.9 2001/02/01 03:38:17 smurph Exp $ */
 /*
  * Mach Operating System
  * Copyright (c) 1993-1991 Carnegie Mellon University
@@ -59,12 +59,12 @@ typedef unsigned long m88k_psr_type;
  */
 static __inline__ m88k_psr_type disable_interrupts_return_psr(void)
 {
-   m88k_psr_type temp, oldpsr;
-   __asm__ __volatile__ ("ldcr %0, cr1" : "=r" (oldpsr));
-   __asm__ __volatile__ ("set  %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp));
-   __asm__ __volatile__ ("stcr %0, cr1" : "=r" (temp));
-   __asm__ __volatile__ ("tcnd ne0, r0, 0");
-   return oldpsr;
+	m88k_psr_type temp, oldpsr;
+	__asm__ __volatile__ ("ldcr %0, cr1" : "=r" (oldpsr));
+	__asm__ __volatile__ ("set  %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp));
+	__asm__ __volatile__ ("stcr %0, cr1" : "=r" (temp));
+	__asm__ __volatile__ ("tcnd ne0, r0, 0");
+	return oldpsr;
 }
 #define disable_interrupt() (void)disable_interrupts_return_psr()
 
@@ -73,7 +73,7 @@ static __inline__ m88k_psr_type disable_interrupts_return_psr(void)
  */
 static __inline__ void set_psr(m88k_psr_type psr)
 {
-   __asm__ __volatile__ ("stcr %0, cr1" :: "r" (psr));
+	__asm__ __volatile__ ("stcr %0, cr1" :: "r" (psr));
 }
 
 /*
@@ -81,11 +81,11 @@ static __inline__ void set_psr(m88k_psr_type psr)
  */
 static __inline__ m88k_psr_type enable_interrupts_return_psr(void)
 {
-   m88k_psr_type temp, oldpsr; /* need a temporary register */
-   __asm__ __volatile__ ("ldcr %0, cr1" : "=r" (oldpsr));
-   __asm__ __volatile__ ("clr  %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp));
-   __asm__ __volatile__ ("stcr %0, cr1" : "=r" (temp));
-   return oldpsr;
+	m88k_psr_type temp, oldpsr; /* need a temporary register */
+	__asm__ __volatile__ ("ldcr %0, cr1" : "=r" (oldpsr));
+	__asm__ __volatile__ ("clr  %1, %0, 1<1>" : "=r" (oldpsr), "=r" (temp));
+	__asm__ __volatile__ ("stcr %0, cr1" : "=r" (temp));
+	return oldpsr;
 }
 #define enable_interrupt() (void)enable_interrupts_return_psr()
 
@@ -97,8 +97,19 @@ static __inline__ m88k_psr_type enable_interrupts_return_psr(void)
  */
 static __inline__ void flush_pipeline()
 {
-    __asm__ __volatile__ ("tcnd ne0, r0, 0");
+	__asm__ __volatile__ ("tcnd ne0, r0, 0");
 }
 #define db_flush_pipeline flush_pipeline
 
+/*
+ * gets the current stack pointer.
+ */
+static inline unsigned long stack_pointer()
+{
+	register unsigned long sp;
+	__asm__ __volatile__ ("or %0,r0,r31" : "=r" (sp));
+	return(sp);
+}
+
+
 #endif __MACHINE_M88K_ASM_MACRO_H__
diff --git a/sys/arch/mvme88k/include/board.h b/sys/arch/mvme88k/include/board.h
index 7890c04b7f5..b69e13778ca 100644
--- a/sys/arch/mvme88k/include/board.h
+++ b/sys/arch/mvme88k/include/board.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: board.h,v 1.7 2001/01/14 20:25:23 smurph Exp $ */
+/*	$OpenBSD: board.h,v 1.8 2001/02/01 03:38:17 smurph Exp $ */
 /*
  * Copyright (c) 1996 Nivas Madhur
  * All rights reserved.
@@ -63,52 +63,52 @@
 #endif
 #define UDEFINED
 
-#define MAX_CPUS	4		/* no. of CPUs */
-#define MAX_CMMUS	8		/* 2 CMMUs per CPU - 1 data and 1 code */
+#define MAX_CPUS	4	/* no. of CPUs */
+#define MAX_CMMUS	8	/* 2 CMMUs per CPU - 1 data and 1 code */
 
-#define SYSV_BASE			U(0x00000000) 	/* system virtual base */
+#define SYSV_BASE	U(0x00000000)	/* system virtual base */
 
-#define MAXU_ADDR			U(0x40000000) 	/* size of user virtual space */
-#define MAXPHYSMEM		U(0x10000000) 	/* max physical memory */
+#define MAXU_ADDR	U(0x40000000)	/* size of user virtual space */
+#define MAXPHYSMEM	U(0x10000000)	/* max physical memory */
 
-#define VMEA16				U(0xFFFF0000)	/* VMEbus A16 */
-#define VMEA16_SIZE		U(0x0000EFFF)	/* VMEbus A16 size */
-#define VMEA32D16    	U(0xFF000000)  /* VMEbus A32/D16 */
+#define VMEA16		U(0xFFFF0000)	/* VMEbus A16 */
+#define VMEA16_SIZE	U(0x0000EFFF)	/* VMEbus A16 size */
+#define VMEA32D16    	U(0xFF000000)	/* VMEbus A32/D16 */
 #define VMEA32D16_SIZE	U(0x007FFFFF)	/* VMEbus A32/D16 size */
 
 
 /* These need to be here because of the way m18x_cmmu.c 
    handles the CMMU's. */
-#define CMMU_SIZE			0x1000
+#define CMMU_SIZE	0x1000
 
 #ifndef CMMU_DEFS
 #define CMMU_DEFS
-#define SBC_CMMU_I		U(0xFFF77000) 	/* Single Board Computer code CMMU */
-#define SBC_CMMU_D		U(0xFFF7F000) 	/* Single Board Computer data CMMU */
+#define SBC_CMMU_I	U(0xFFF77000) 	/* Single Board Computer code CMMU */
+#define SBC_CMMU_D	U(0xFFF7F000) 	/* Single Board Computer data CMMU */
 
-#define VME_CMMU_I0		U(0xFFF7E000) 	/* MVME188 code CMMU 0 */
-#define VME_CMMU_I1		U(0xFFF7D000) 	/* MVME188 code CMMU 1 */
-#define VME_CMMU_I2		U(0xFFF7B000) 	/* MVME188 code CMMU 2 */
-#define VME_CMMU_I3		U(0xFFF77000) 	/* MVME188 code CMMU 3 */
-#define VME_CMMU_D0		U(0xFFF6F000) 	/* MVME188 data CMMU 0 */
-#define VME_CMMU_D1		U(0xFFF5F000) 	/* MVME188 data CMMU 1 */
-#define VME_CMMU_D2		U(0xFFF3F000) 	/* MVME188 data CMMU 2 */
-#define VME_CMMU_D3		U(0xFFF7F000) 	/* MVME188 data CMMU 3 */
+#define VME_CMMU_I0	U(0xFFF7E000) 	/* MVME188 code CMMU 0 */
+#define VME_CMMU_I1	U(0xFFF7D000) 	/* MVME188 code CMMU 1 */
+#define VME_CMMU_I2	U(0xFFF7B000) 	/* MVME188 code CMMU 2 */
+#define VME_CMMU_I3	U(0xFFF77000) 	/* MVME188 code CMMU 3 */
+#define VME_CMMU_D0	U(0xFFF6F000) 	/* MVME188 data CMMU 0 */
+#define VME_CMMU_D1	U(0xFFF5F000) 	/* MVME188 data CMMU 1 */
+#define VME_CMMU_D2	U(0xFFF3F000) 	/* MVME188 data CMMU 2 */
+#define VME_CMMU_D3	U(0xFFF7F000) 	/* MVME188 data CMMU 3 */
 #endif /* CMMU_DEFS */
 
 /* These are the hardware exceptions. */
-#define INT_BIT      0x1		/* interrupt exception		*/
-#define IACC_BIT     0x2		/* instruction access exception	*/
-#define DACC_BIT     0x4		/* data access exception	*/
-#define MACC_BIT     0x8		/* misaligned access exception	*/
-#define UOPC_BIT     0x10		/* unimplemented opcode exception*/
-#define PRIV_BIT     0x20		/* priviledge violation exception*/
-#define BND_BIT      0x40		/* bounds check violation	*/
-#define IDE_BIT      0x80		/* illegal integer divide	*/
-#define IOV_BIT      0x100		/* integer overflow exception	*/
-#define ERR_BIT      0x200		/* error exception		*/
-#define FPUP_BIT     0x400		/* FPU precise exception	*/
-#define FPUI_BIT     0x800		/* FPU imprecise exception	*/
+#define INT_BIT		0x1		/* interrupt exception		*/
+#define IACC_BIT	0x2		/* instruction access exception	*/
+#define DACC_BIT	0x4		/* data access exception	*/
+#define MACC_BIT	0x8		/* misaligned access exception	*/
+#define UOPC_BIT	0x10		/* unimplemented opcode exception*/
+#define PRIV_BIT	0x20		/* priviledge violation exception*/
+#define BND_BIT		0x40		/* bounds check violation	*/
+#define IDE_BIT		0x80		/* illegal integer divide	*/
+#define IOV_BIT		0x100		/* integer overflow exception	*/
+#define ERR_BIT		0x200		/* error exception		*/
+#define FPUP_BIT	0x400		/* FPU precise exception	*/
+#define FPUI_BIT	0x800		/* FPU imprecise exception	*/
 
 #if defined(MVME187) || defined(MVME197)
 #include <machine/mvme1x7.h>
diff --git a/sys/arch/mvme88k/include/m88100.h b/sys/arch/mvme88k/include/m88100.h
index 88739cbc908..57b8111f5fd 100644
--- a/sys/arch/mvme88k/include/m88100.h
+++ b/sys/arch/mvme88k/include/m88100.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88100.h,v 1.5 2001/01/14 20:25:24 smurph Exp $ */
+/*	$OpenBSD: m88100.h,v 1.6 2001/02/01 03:38:17 smurph Exp $ */
 /* 
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
@@ -40,6 +40,7 @@
  */
 
 /* DMT0, DMT1, DMT2 */
+#define DMT_SKIP	0x00010000	/* skip this dmt in data_access_emulation */
 #define DMT_BO		0x00008000	/* Byte-Ordering */
 #define DMT_DAS		0x00004000	/* Data Access Space */
 #define DMT_DOUB1	0x00002000	/* Double Word */
@@ -53,17 +54,22 @@
 #ifndef	ASSEMBLER
 #include "sys/types.h"
 
+/* dmt_skip is never set by the cpu.  It is used to 
+ * mark 'known' transactions so that they don't get 
+ * prosessed by data_access_emulation().  XXX smurph 
+ */
 struct dmt_reg {
-    unsigned int :16,
-	  dmt_bo:1,
-          dmt_das:1,
-	  dmt_doub1:1,
-	  dmt_lockbar:1,
-	  dmt_dreg:5,
-	  dmt_signed:1,
-	  dmt_en:4,
-	  dmt_write:1,
-	  dmt_valid:1;
+	unsigned int :15,
+	dmt_skip:1,   
+	dmt_bo:1,
+	dmt_das:1,
+	dmt_doub1:1,
+	dmt_lockbar:1,
+	dmt_dreg:5,
+	dmt_signed:1,
+	dmt_en:4,
+	dmt_write:1,
+	dmt_valid:1;
 };
 #endif 
 
diff --git a/sys/arch/mvme88k/include/mvme188.h b/sys/arch/mvme88k/include/mvme188.h
index 3bb14c0ff5e..039e396c09a 100644
--- a/sys/arch/mvme88k/include/mvme188.h
+++ b/sys/arch/mvme88k/include/mvme188.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mvme188.h,v 1.2 2001/01/14 20:25:24 smurph Exp $ */
+/*	$OpenBSD: mvme188.h,v 1.3 2001/02/01 03:38:18 smurph Exp $ */
 /*
  * Copyright (c) 1999 Steve Murphree, Jr.
  * All rights reserved.
@@ -63,14 +63,14 @@
 #endif
 
 
-#define MVME188_EPROM		   U(0xFFC00000)
-#define MVME188_EPROM_SIZE	   U(0x00080000)
-#define MVME188_SRAM		      U(0xFFE00000)
-#define MVME188_SRAM_SIZE	   U(0x00020000)
-#define MVME188_UTILITY		   U(0xFF000000)
+#define MVME188_EPROM		U(0xFFC00000)
+#define MVME188_EPROM_SIZE	U(0x00080000)
+#define MVME188_SRAM		U(0xFFE00000)
+#define MVME188_SRAM_SIZE	U(0x00020000)
+#define MVME188_UTILITY		U(0xFF000000)
 #define MVME188_UTILITY_SIZE	U(0x01000000)
-#define UTIL_START            U(0xFFC00000)  /* start of MVME188 utility space */
-#define UTIL_SIZE             U(0x003FFFFF)  /* size of MVME188 utility space */
+#define UTIL_START		U(0xFFC00000)  /* start of MVME188 utility space */
+#define UTIL_SIZE		U(0x003FFFFF)  /* size of MVME188 utility space */
 
 /*
  * MVME188 declarations for hardware level device registers and such.
@@ -78,24 +78,24 @@
 
 /* base address for the interrupt control registers */
 #define INTR_CONTROL_BASE	U(0xfff84000)
-#define VMEA24SPACE 	   U(0xEEC00000) 	/*  VMEA24 master addr space (4 Meg) */
+#define VMEA24SPACE	U(0xEEC00000) 	/*  VMEA24 master addr space (4 Meg) */
 
 /* per-processor interrupt enable registers */
-#define MVME188_IEN0	   U(0xFFF84004)	/* interrupt enable CPU 0 */
-#define MVME188_IEN1	   U(0xFFF84008)	/* interrupt enable CPU 1 */
-#define MVME188_IEN2	   U(0xFFF84010)	/* interrupt enable CPU 2 */
-#define MVME188_IEN3	   U(0xFFF84020)	/* interrupt enable CPU 3 */
+#define MVME188_IEN0	U(0xFFF84004)	/* interrupt enable CPU 0 */
+#define MVME188_IEN1	U(0xFFF84008)	/* interrupt enable CPU 1 */
+#define MVME188_IEN2	U(0xFFF84010)	/* interrupt enable CPU 2 */
+#define MVME188_IEN3	U(0xFFF84020)	/* interrupt enable CPU 3 */
 
 /* same as above */
-#define IEN0_REG        U(0xfff84004)
-#define IEN1_REG        U(0xfff84008)
-#define IEN2_REG        U(0xfff84010)
-#define IEN3_REG        U(0xfff84020)
+#define IEN0_REG	U(0xfff84004)
+#define IEN1_REG	U(0xfff84008)
+#define IEN2_REG	U(0xfff84010)
+#define IEN3_REG	U(0xfff84020)
 
-#define IENALL_REG      U(0xfff8403c)
+#define IENALL_REG	U(0xfff8403c)
 
-#define MVME188_IST	   U(0xFFF84040) 	/* interrupt status register */
-#define IST_REG         U(0xfff84040)	/* same as above */
+#define MVME188_IST	U(0xFFF84040) 	/* interrupt status register */
+#define IST_REG		U(0xfff84040)	/* same as above */
 
 #define MVME188_SETSWI	U(0xFFF84080) 	/* generate soft interrupt */
 #define MVME188_CLRSWI	U(0xFFF84084) 	/* reset soft interrupt */
@@ -103,82 +103,82 @@
 #define MVME188_CLRINT	U(0xFFF8408C) 	/* reset HW interrupt */
 
 /* same as above */
-#define SETSWI_REG   U(0xfff84080)	/* SETSWI register addr */
-#define CLRSWI_REG   U(0xfff84084)	/* CLRSWI register addr */
-#define ISTATE_REG   U(0xfff84088)
-#define CLRINT_REG   U(0xfff8408C)
-
-#define MVME188_GCSR 	U(0xFFF86000)	/* 188 global control and status reg */
-#define MVME188_UCSR 	U(0xFFF87000)	/* 188 utility control and status reg */
-#define MVME188_BASAD 	U(0xFFF87004)	/* 188 base address reg */
-#define MVME188_GLBRES 	U(0xFFF8700C)	/* 188 global reset reg */
-
-#define GCSR_BASE    U(0xfff86000)
-#define GLOBAL0      GCSR_BASE + 0x01
-#define GLOBAL1      GCSR_BASE + 0x03
-#define GLOBAL2      GCSR_BASE + 0x05
-#define GLOBAL3      GCSR_BASE + 0x07
-#define GLB0         U(0xfff86001)
-#define GLB1         U(0xfff86003)
-#define GLB2         U(0xfff86005)
-#define GLB3         U(0xfff86007)
-#define M188_SYSCON  U(0x00000040)
-#define UCSR_REG     U(0xfff87000)
-#define GLBRES_REG   U(0xfff8700C)
-
-#define MVME188_CCSR 	U(0xFFF88000)	/* 188 CPU board control status reg */
-#define MVME188_ERROR 	U(0xFFF88004)	/* 188 Mbus fault reg */
-#define MVME188_PCNFA 	U(0xFFF88008)	/* 188 Pbus A decoder reg */
-#define MVME188_PCNFB 	U(0xFFF8800C)	/* 188 Pbus B decoder reg */
-#define MVME188_EXTAD 	U(0xFFF88010)	/* 188 A24 master A24-A31 addr reg */
-#define MVME188_WHOAMI 	U(0xFFF88018)	/* 188 whoami reg */
-#define MVME188_WMAD 	U(0xFFF88020)	/* 188 write mbus addr decoder reg */
-#define MVME188_RMAD 	U(0xFFF88024)	/* 188 read mbus addr decoder reg */
-#define MVME188_WVAD 	U(0xFFF88028)	/* 188 write vmebus addr decoder reg */
-#define MVME188_RVAD 	U(0xFFF8802C)	/* 188 read vmebus adds decoder reg */
+#define SETSWI_REG	U(0xfff84080)	/* SETSWI register addr */
+#define CLRSWI_REG	U(0xfff84084)	/* CLRSWI register addr */
+#define ISTATE_REG	U(0xfff84088)
+#define CLRINT_REG	U(0xfff8408C)
+
+#define MVME188_GCSR	U(0xFFF86000)	/* 188 global control and status reg */
+#define MVME188_UCSR	U(0xFFF87000)	/* 188 utility control and status reg */
+#define MVME188_BASAD	U(0xFFF87004)	/* 188 base address reg */
+#define MVME188_GLBRES	U(0xFFF8700C)	/* 188 global reset reg */
+
+#define GCSR_BASE	U(0xfff86000)
+#define GLOBAL0		GCSR_BASE + 0x01
+#define GLOBAL1		GCSR_BASE + 0x03
+#define GLOBAL2		GCSR_BASE + 0x05
+#define GLOBAL3		GCSR_BASE + 0x07
+#define GLB0		U(0xfff86001)
+#define GLB1		U(0xfff86003)
+#define GLB2		U(0xfff86005)
+#define GLB3		U(0xfff86007)
+#define M188_SYSCON	U(0x00000040)
+#define UCSR_REG	U(0xfff87000)
+#define GLBRES_REG	U(0xfff8700C)
+
+#define MVME188_CCSR	U(0xFFF88000)	/* 188 CPU board control status reg */
+#define MVME188_ERROR	U(0xFFF88004)	/* 188 Mbus fault reg */
+#define MVME188_PCNFA	U(0xFFF88008)	/* 188 Pbus A decoder reg */
+#define MVME188_PCNFB	U(0xFFF8800C)	/* 188 Pbus B decoder reg */
+#define MVME188_EXTAD	U(0xFFF88010)	/* 188 A24 master A24-A31 addr reg */
+#define MVME188_WHOAMI	U(0xFFF88018)	/* 188 whoami reg */
+#define MVME188_WMAD	U(0xFFF88020)	/* 188 write mbus addr decoder reg */
+#define MVME188_RMAD	U(0xFFF88024)	/* 188 read mbus addr decoder reg */
+#define MVME188_WVAD	U(0xFFF88028)	/* 188 write vmebus addr decoder reg */
+#define MVME188_RVAD	U(0xFFF8802C)	/* 188 read vmebus adds decoder reg */
 
 /* duplicates of above */
-#define CCSR_REG     U(0xfff88000)
-#define ERROR_REG    U(0xfff88004)	/* ERROR register addr */
-#define PCNFA_REG    U(0xfff88008)
-#define PCNFB_REG    U(0xfff8800c)
-#define EXTAD_REG    U(0xfff88010)
-#define EXTAM_REG    U(0xfff88014)
-#define WHOAMI_REG   U(0xfff88018)	/* WHOAMI register addr */
-#define WMAD_REG     U(0xfff88020)
-#define RMAD_REG     U(0xfff88024)
-#define WVAD_REG     U(0xfff88028)
-#define RVAD_REG     U(0xfff8802c)
-
-#define MAD_MDS		   0x07	/* 188 MAD Device Select bits */
-
-#define VMEA24 		   0x5	/* Mbus addess decode select for VMEA24 */
-#define VADV		      0x1	/* vmeaddres decode enable */
-#define VBDSELBIT 	   0 	   /* bit to enable vme slave response low true */
-#define VBDISABLE	      0x1	/* VME BUS Disable */
-#define VSDBIT    	   1 	   /* bit number to enable snooping low true */
-#define VSDISABLE	      0x2	/* VME Snoop Disable */
-#define VASPBIT	 	   21 	/* addr space 0 = A32, 1 = A24 bit */
-#define VASP		      0x00200000 /* A24 VME address space */
-#define VPN		         0x00400000 /* Page Number LSB */
-#define PAGECNT		   0x400	/* number of (4 meg) pages to map */
+#define CCSR_REG	U(0xfff88000)
+#define ERROR_REG	U(0xfff88004)	/* ERROR register addr */
+#define PCNFA_REG	U(0xfff88008)
+#define PCNFB_REG	U(0xfff8800c)
+#define EXTAD_REG	U(0xfff88010)
+#define EXTAM_REG	U(0xfff88014)
+#define WHOAMI_REG	U(0xfff88018)	/* WHOAMI register addr */
+#define WMAD_REG	U(0xfff88020)
+#define RMAD_REG	U(0xfff88024)
+#define WVAD_REG	U(0xfff88028)
+#define RVAD_REG	U(0xfff8802c)
+
+#define MAD_MDS		0x07	/* 188 MAD Device Select bits */
+
+#define VMEA24		0x5	/* Mbus addess decode select for VMEA24 */
+#define VADV		0x1	/* vmeaddres decode enable */
+#define VBDSELBIT	0	/* bit to enable vme slave response low true */
+#define VBDISABLE	0x1	/* VME BUS Disable */
+#define VSDBIT		1	/* bit number to enable snooping low true */
+#define VSDISABLE	0x2	/* VME Snoop Disable */
+#define VASPBIT		21	/* addr space 0 = A32, 1 = A24 bit */
+#define VASP		0x00200000	/* A24 VME address space */
+#define VPN		0x00400000	/* Page Number LSB */
+#define PAGECNT		0x400	/* number of (4 meg) pages to map */
 
 #define UCSR_PWRUPBIT 	0x4000	/* 188 UCSR powerup indicator */
 #define UCSR_DRVSFBIT 	0x2000	/* 188 UCSR Board system fail */
 #define UCSR_BRIRQBIT 	0x1000	/* 188 UCSR drives VME IRQ1 broadcast int */
-#define UCSR_ROBINBIT 	0x800	   /* 188 UCSR sel round robin VME arbiter mode */
-#define UCSR_BRLVBITS 	0x600	   /* 188 UCSR VME bus request level 0-3 */
-#define UCSR_RNEVERBIT  0x100	   /* 188 UCSR VME bus never release once req'd */
-#define UCSR_RONRBIT	   0x80	   /* 188 UCSR VME bus req release on no request */
-#define UCSR_RWDBIT		0x40	   /* 188 UCSR VME bus request release when done */
-#define UCSR_EARBTOBIT  0x20	   /* 188 UCSR enable VME arbiter bus timeout */
+#define UCSR_ROBINBIT 	0x800	/* 188 UCSR sel round robin VME arbiter mode */
+#define UCSR_BRLVBITS 	0x600	/* 188 UCSR VME bus request level 0-3 */
+#define UCSR_RNEVERBIT  0x100	/* 188 UCSR VME bus never release once req'd */
+#define UCSR_RONRBIT	0x80	/* 188 UCSR VME bus req release on no request */
+#define UCSR_RWDBIT	0x40	/* 188 UCSR VME bus request release when done */
+#define UCSR_EARBTOBIT  0x20	/* 188 UCSR enable VME arbiter bus timeout */
 
 /* MVME188 VMEbus data transfer timeout select */
-#define VTOSELBITS 	0x18	/* 188 UCSR VMEbus timeout select bits */
-#define VTO32US 	   0x00	/* VMEbus timeout length - 32 MicroSec */
-#define VTO64US 	   0x01	/* VMEbus timeout length - 64 MicroSec */
-#define VTO128US 	   0x10	/* VMEbus timeout length - 128 MicroSec */
-#define VTODISABLE 	0x18	/* VMEbus timeout length - disabled */
+#define VTOSELBITS	0x18	/* 188 UCSR VMEbus timeout select bits */
+#define VTO32US		0x00	/* VMEbus timeout length - 32 MicroSec */
+#define VTO64US		0x01	/* VMEbus timeout length - 64 MicroSec */
+#define VTO128US	0x10	/* VMEbus timeout length - 128 MicroSec */
+#define VTODISABLE	0x18	/* VMEbus timeout length - disabled */
 
 /*
  * processor dependend code section
@@ -207,18 +207,6 @@
 
 #define INT_LEVEL	        8		/* # of interrupt level + 1 */
 
-/*
- * masks and offsets for IST
- */
-#define HW_FAILURE_MASK		   U(0x60100000)	/* HW failure bits */
-#define HW_FAILURE_ACF		   U(0x40000000)  /* AC failure */
-#define HW_FAILURE_ABRTO	   U(0x20000000)  /* Arbiter timeout */
-#define HW_FAILURE_SYSFAIL	   U(0x00100000) 	/* SYSFAIL asserted */
-
-#define SOFT_INTERRUPT_MASK	U(0x0F00000F)	/* software irq bits */
-#define VME_INTERRUPT_MASK	   U(0x00885450)	/* vme irq bits */
-#define OBIO_INTERRUPT_MASK	U(0xF0320100)  /* on board I/O */
-
 #define IEN_ABRT_LOG		31
 #define IEN_CIOI_LOG		21
 #define IEN_DTI_LOG		28
@@ -230,40 +218,45 @@
 
 /* the following codes are the INT exception enable and status bits. */
 /* Refer to MVME188 RISC Microcomputer User's Manual, 4-10. */
-#define ABRT_BIT     U(0x80000000)
-#define ACF_BIT      U(0x40000000)
-#define ARBTO_BIT    U(0x20000000)
-#define DTI_BIT      U(0x10000000)
-#define SWI7_BIT     U(0x08000000)
-#define SWI6_BIT     U(0x04000000)
-#define SWI5_BIT     U(0x02000000)
-#define SWI4_BIT     U(0x01000000)
-#define IRQ7_BIT     U(0x00800000)
-#define CIOI_BIT     U(0x00200000)
-#define SF_BIT       U(0x00100000)
-#define IRQ6_BIT     U(0x00080000)
-#define DI_BIT       U(0x00020000)
-#define SIGHPI_BIT   U(0x00010000)
-#define IRQ5_BIT     U(0x00004000)
-#define IRQ4_BIT     U(0x00001000)
-#define IRQ3_BIT     U(0x00000400)
-#define LMI_BIT      U(0x00000100)
-#define SIGLPI_BIT   U(0x00000080)
-#define IRQ2_BIT     U(0x00000040)
-#define IRQ1_BIT     U(0x00000010)
-#define SWI3_BIT     U(0x00000008)
-#define SWI2_BIT     U(0x00000004)
-#define SWI1_BIT     U(0x00000002)
-#define SWI0_BIT     U(0x00000001)
-
-#define ABRT_BIT     U(0x80000000)
-#define ACF_BIT      U(0x40000000)
-#define ARBTO_BIT    U(0x20000000)
-#define DTI_BIT      U(0x10000000)
-#define CIOI_BIT     U(0x00200000)
-#define SF_BIT       U(0x00100000)
-#define DI_BIT       U(0x00020000)
-#define LMI_BIT      U(0x00000100)
+#define ABRT_BIT		U(0x80000000)	/* 31 */
+#define ACF_BIT			U(0x40000000)	/* 30 */
+#define ARBTO_BIT		U(0x20000000)	/* 29 */
+#define DTI_BIT			U(0x10000000)	/* 28 */
+#define SWI7_BIT		U(0x08000000)	/* 27 */
+#define SWI6_BIT		U(0x04000000)	/* 26 */
+#define SWI5_BIT		U(0x02000000)	/* 25 */
+#define SWI4_BIT		U(0x01000000)	/* 24 */	   
+#define IRQ7_BIT		U(0x00800000)	/* 23 */
+#define CIOI_BIT		U(0x00200000)	/* 21 */
+#define SF_BIT			U(0x00100000)	/* 20 */
+#define IRQ6_BIT		U(0x00080000)	/* 19 */
+#define DI_BIT			U(0x00020000)	/* 17 */
+#define SIGHPI_BIT		U(0x00010000)	/* 16 */
+#define IRQ5_BIT		U(0x00004000)	/* 14 */
+#define IRQ4_BIT		U(0x00001000)	/* 12 */
+#define IRQ3_BIT		U(0x00000400)	/* 10 */
+#define LMI_BIT			U(0x00000100)	/* 08 */
+#define SIGLPI_BIT		U(0x00000080)	/* 07 */
+#define IRQ2_BIT		U(0x00000040)	/* 06 */
+#define IRQ1_BIT		U(0x00000010)	/* 04 */
+#define SWI3_BIT		U(0x00000008)	/* 03 */
+#define SWI2_BIT		U(0x00000004)	/* 02 */
+#define SWI1_BIT		U(0x00000002)	/* 01 */
+#define SWI0_BIT		U(0x00000001)	/* 00 */
+
+/*
+ * masks and offsets for IST
+ * These are a combination of the above
+ */
+#define HW_FAILURE_MASK		U(0xE0100000)	/* hardware irq bits */
+#define SOFT_INTERRUPT_MASK	U(0x0F00000F)	/* software irq bits */
+#define VME_INTERRUPT_MASK	U(0x00885450)   /* vme irq bits */
+#define OBIO_INTERRUPT_MASK	U(0x10330180)	/* on board I/O */
+
+#define HW_FAILURE_ACF		ACF_BIT		/* AC failure */
+#define HW_FAILURE_ABRTO	ARBTO_BIT	/* Arbiter timeout */
+#define HW_FAILURE_SYSFAIL	SF_BIT		/* SYSFAIL asserted */
+#define HW_FAILURE_ABORT	ABRT_BIT	/* Abort pressed */
 
 #define LVL7 (ABRT_BIT | ACF_BIT | IRQ7_BIT | SF_BIT)
 #define LVL6 (IRQ6_BIT)
@@ -285,96 +278,96 @@
 #define MASK_LVL_7 U(0x00000000) /* all ints disabled */
 
 /* these are the various Z8536 CIO counter/timer registers */
-#define CIO_BASE     U(0xfff83000)
-#define CIO_PORTC    U(0xfff83000)
-#define CIO_PORTB    U(0xfff83004)
-#define CIO_PORTA    U(0xfff83008)
-#define CIO_CTRL     U(0xfff8300c)
-
-#define CIO_MICR        0x00	/* Master interrupt control register */
-#define CIO_MICR_MIE    0x80
-#define CIO_MICR_DLC    0x40
-#define CIO_MICR_NV     0x20
-#define CIO_MICR_PAVIS  0x10
-#define CIO_MICR_PBVIS  0x08
-#define CIO_MICR_CTVIS  0x04
-#define CIO_MICR_RJA    0x02
-#define CIO_MICR_RESET  0x01
-
-#define CIO_MCCR        0x01	/* Master configuration control register */
-#define CIO_MCCR_PBE    0x80
-#define CIO_MCCR_CT1E   0x40
-#define CIO_MCCR_CT2E   0x20
-#define CIO_MCCR_CT3E   0x10
-#define CIO_MCCR_PLC    0x08
-#define CIO_MCCR_PAE    0x04
-
-#define CIO_CTMS1       0x1c	/* Counter/timer mode specification #1 */
-#define CIO_CTMS2       0x1d	/* Counter/timer mode specification #2 */
-#define CIO_CTMS3       0x1e	/* Counter/timer mode specification #3 */
-#define CIO_CTMS_CSC    0x80  /* Continuous Single Cycle */
-#define CIO_CTMS_EOE    0x40  /* External Output Enable  */
-#define CIO_CTMS_ECE    0x20  /* External Count Enable   */
-#define CIO_CTMS_ETE    0x10  /* External Trigger Enable */
-#define CIO_CTMS_EGE    0x08  /* External Gate Enable    */
-#define CIO_CTMS_REB    0x04  /* Retrigger Enable Bit    */
-#define CIO_CTMS_PO     0x00  /* Pulse Output            */
-#define CIO_CTMS_OSO    0x01  /* One Shot Output         */
-#define CIO_CTMS_SWO    0x02  /* Square Wave Output      */
-
-#define CIO_IVR         0x04	/* Interrupt vector register */
-
-#define CIO_CSR1        0x0a	/* Command and status register CTC #1 */
-#define CIO_CSR2        0x0b	/* Command and status register CTC #2 */
-#define CIO_CSR3        0x0c	/* Command and status register CTC #3 */
-
-#define CIO_CT1MSB      0x16	/* CTC #1 Timer constant - MSB */
-#define CIO_CT1LSB      0x17	/* CTC #1 Timer constant - LSB */
-#define CIO_CT2MSB      0x18	/* CTC #2 Timer constant - MSB */
-#define CIO_CT2LSB      0x19	/* CTC #2 Timer constant - LSB */
-#define CIO_CT3MSB      0x1a	/* CTC #3 Timer constant - MSB */
-#define CIO_CT3LSB      0x1b	/* CTC #3 Timer constant - LSB */
-#define CIO_PDCA        0x23	/* Port A data direction control */
-#define CIO_PDCB        0x2b	/* Port B data direction control */
-
-#define CIO_GCB         0x04	/* CTC Gate command bit */
-#define CIO_TCB         0x02	/* CTC Trigger command bit */
-#define CIO_IE          0xc0	/* CTC Interrupt enable (set) */
-#define CIO_CIP         0x20	/* CTC Clear interrupt pending */
-#define CIO_IP          0x20	/* CTC Interrupt pending */
+#define CIO_BASE		U(0xfff83000)
+#define CIO_PORTC		U(0xfff83000)
+#define CIO_PORTB		U(0xfff83004)
+#define CIO_PORTA		U(0xfff83008)
+#define CIO_CTRL		U(0xfff8300c)
+
+#define CIO_MICR		0x00	/* Master interrupt control register */
+#define CIO_MICR_MIE		0x80
+#define CIO_MICR_DLC		0x40
+#define CIO_MICR_NV		0x20
+#define CIO_MICR_PAVIS		0x10
+#define CIO_MICR_PBVIS		0x08
+#define CIO_MICR_CTVIS		0x04
+#define CIO_MICR_RJA		0x02
+#define CIO_MICR_RESET		0x01
+
+#define CIO_MCCR		0x01	/* Master config control register */
+#define CIO_MCCR_PBE		0x80
+#define CIO_MCCR_CT1E		0x40
+#define CIO_MCCR_CT2E		0x20
+#define CIO_MCCR_CT3E		0x10
+#define CIO_MCCR_PLC		0x08
+#define CIO_MCCR_PAE		0x04
+
+#define CIO_CTMS1		0x1c	/* Counter/timer mode specification #1 */
+#define CIO_CTMS2		0x1d	/* Counter/timer mode specification #2 */
+#define CIO_CTMS3		0x1e	/* Counter/timer mode specification #3 */
+#define CIO_CTMS_CSC		0x80	/* Continuous Single Cycle */
+#define CIO_CTMS_EOE		0x40	/* External Output Enable  */
+#define CIO_CTMS_ECE		0x20	/* External Count Enable   */
+#define CIO_CTMS_ETE		0x10	/* External Trigger Enable */
+#define CIO_CTMS_EGE		0x08	/* External Gate Enable    */
+#define CIO_CTMS_REB		0x04	/* Retrigger Enable Bit    */
+#define CIO_CTMS_PO		0x00	/* Pulse Output            */
+#define CIO_CTMS_OSO		0x01	/* One Shot Output         */
+#define CIO_CTMS_SWO		0x02	/* Square Wave Output      */
+
+#define CIO_IVR			0x04	/* Interrupt vector register */
+
+#define CIO_CSR1		0x0a	/* Command and status register CTC #1 */
+#define CIO_CSR2		0x0b	/* Command and status register CTC #2 */
+#define CIO_CSR3		0x0c	/* Command and status register CTC #3 */
+
+#define CIO_CT1MSB		0x16	/* CTC #1 Timer constant - MSB */
+#define CIO_CT1LSB		0x17	/* CTC #1 Timer constant - LSB */
+#define CIO_CT2MSB		0x18	/* CTC #2 Timer constant - MSB */
+#define CIO_CT2LSB		0x19	/* CTC #2 Timer constant - LSB */
+#define CIO_CT3MSB		0x1a	/* CTC #3 Timer constant - MSB */
+#define CIO_CT3LSB		0x1b	/* CTC #3 Timer constant - LSB */
+#define CIO_PDCA		0x23	/* Port A data direction control */
+#define CIO_PDCB		0x2b	/* Port B data direction control */
+
+#define CIO_GCB			0x04	/* CTC Gate command bit */
+#define CIO_TCB			0x02	/* CTC Trigger command bit */
+#define CIO_IE			0xc0	/* CTC Interrupt enable (set) */
+#define CIO_CIP			0x20	/* CTC Clear interrupt pending */
+#define CIO_IP			0x20	/* CTC Interrupt pending */
 
 /* these are the DART read registers */
-#define DART_BASE    U(0xfff82000)
-#define DART_MRA     U(0xfff82000)	/* mode A */
-#define DART_SRA     U(0xfff82004)	/* status A */
-#define DART_RBA     U(0xfff8200c)	/* receive buffer A */
-#define DART_IPCR    U(0xfff82010)	/* input port change */
-#define DART_ISR     U(0xfff82014)	/* interrupt status */
-#define DART_CUR     U(0xfff82018)	/* count upper */
-#define DART_CLR     U(0xfff8201c)	/* count lower */
-#define DART_MR1B    U(0xfff82020)	/* mode B */
-#define DART_SRB     U(0xfff82024)	/* status B */
-#define DART_RBB     U(0xfff8202c)	/* receive buffer B */
-#define DART_IVR     U(0xfff82030)	/* interrupt vector */
-#define DART_INP     U(0xfff82034)	/* input port */
-#define DART_STARTC  U(0xfff82038)	/* start counter cmd */
-#define DART_STOPC   U(0xfff8203c)	/* stop counter cmd */
+#define DART_BASE		U(0xfff82000)
+#define DART_MRA		U(0xfff82000)	/* mode A */
+#define DART_SRA		U(0xfff82004)	/* status A */
+#define DART_RBA		U(0xfff8200c)	/* receive buffer A */
+#define DART_IPCR		U(0xfff82010)	/* input port change */
+#define DART_ISR		U(0xfff82014)	/* interrupt status */
+#define DART_CUR		U(0xfff82018)	/* count upper */
+#define DART_CLR		U(0xfff8201c)	/* count lower */
+#define DART_MR1B		U(0xfff82020)	/* mode B */
+#define DART_SRB		U(0xfff82024)	/* status B */
+#define DART_RBB		U(0xfff8202c)	/* receive buffer B */
+#define DART_IVR		U(0xfff82030)	/* interrupt vector */
+#define DART_INP		U(0xfff82034)	/* input port */
+#define DART_STARTC		U(0xfff82038)	/* start counter cmd */
+#define DART_STOPC		U(0xfff8203c)	/* stop counter cmd */
 
 /* these are the DART write registers */
-#define DART_CSRA    U(0xfff82004)	/* clock select A */
-#define DART_CRA     U(0xfff82008)	/* command A */
-#define DART_TBA     U(0xfff8200c)	/* transmit buffer A */
-#define DART_ACR     U(0xfff82010)	/* auxiliary control */
-#define DART_IMR     U(0xfff82014)	/* interrupt mask reg*/
-#define DART_CTUR    U(0xfff82018)	/* counter/timer MSB */
-#define DART_CTLR    U(0xfff8201c)	/* counter/timer LSB */
-#define DART_MRB     U(0xfff82020)	/* mode B */
-#define DART_CSRB    U(0xfff82024)	/* clock select B */
-#define DART_CRB     U(0xfff82028)	/* command B */
-#define DART_TBB     U(0xfff8202c)	/* transmit buffer B */
-#define DART_OPCR    U(0xfff82034)	/* output port config*/
-#define DART_OPRS    U(0xfff82038)	/* output port set */
-#define DART_OPRR    U(0xfff8203c)	/* output port reset */
+#define DART_CSRA		U(0xfff82004)	/* clock select A */
+#define DART_CRA		U(0xfff82008)	/* command A */
+#define DART_TBA		U(0xfff8200c)	/* transmit buffer A */
+#define DART_ACR		U(0xfff82010)	/* auxiliary control */
+#define DART_IMR		U(0xfff82014)	/* interrupt mask reg*/
+#define DART_CTUR		U(0xfff82018)	/* counter/timer MSB */
+#define DART_CTLR		U(0xfff8201c)	/* counter/timer LSB */
+#define DART_MRB		U(0xfff82020)	/* mode B */
+#define DART_CSRB		U(0xfff82024)	/* clock select B */
+#define DART_CRB		U(0xfff82028)	/* command B */
+#define DART_TBB		U(0xfff8202c)	/* transmit buffer B */
+#define DART_OPCR		U(0xfff82034)	/* output port config*/
+#define DART_OPRS		U(0xfff82038)	/* output port set */
+#define DART_OPRR		U(0xfff8203c)	/* output port reset */
 
 #ifndef ASSEMBLER
 
@@ -392,7 +385,9 @@ extern volatile unsigned int *int_mask_reg[MAX_CPUS];
 void block_obio_interrupt(unsigned mask);
 void unblock_obio_interrupt(unsigned mask);
 #endif 
-#define M188_IACK        U(0xFFF85000)
+
+#define M188_IACK		U(0xFFF85000)
+#define M188_IVEC		0x40	/* vector returned upon MVME188 int */
 
 #endif	__MACHINE_MVME188_H__
 
diff --git a/sys/arch/mvme88k/include/mvme1x7.h b/sys/arch/mvme88k/include/mvme1x7.h
index c296c59bb98..3bf85c1f38c 100644
--- a/sys/arch/mvme88k/include/mvme1x7.h
+++ b/sys/arch/mvme88k/include/mvme1x7.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mvme1x7.h,v 1.2 2001/01/14 20:25:24 smurph Exp $ */
+/*	$OpenBSD: mvme1x7.h,v 1.3 2001/02/01 03:38:18 smurph Exp $ */
 /*
  * Copyright (c) 1996 Nivas Madhur
  * Copyright (c) 1999 Steve Murphree, Jr.
@@ -65,39 +65,39 @@
 #endif
 #endif
 
-#define BUGROM_START		U(0xFF800000)	/* start of BUG PROM */
-#define BUGROM_SIZE		U(0x003FFFFF)	/* size of BUG PROM */
-#define SRAM_START		U(0xFFE00000)	/* start of sram used by bug */
-#define SRAM_SIZE			U(0x0001FFFF)	/* size of sram */
-#define OBIO_START		U(0xFFF00000)	/* start of local IO */
-#define OBIO_SIZE			U(0x000EFFFF)	/* size of obio space */
-#define UTIL_START      U(0xFFC00000)  /* start of MVME188 utility space */
-#define UTIL_SIZE       U(0x003FFFFF)  /* size of MVME188 utility space */
+#define BUGROM_START	U(0xFF800000)	/* start of BUG PROM */
+#define BUGROM_SIZE	U(0x003FFFFF)	/* size of BUG PROM */
+#define SRAM_START	U(0xFFE00000)	/* start of sram used by bug */
+#define SRAM_SIZE	U(0x0001FFFF)	/* size of sram */
+#define OBIO_START	U(0xFFF00000)	/* start of local IO */
+#define OBIO_SIZE	U(0x000EFFFF)	/* size of obio space */
+#define UTIL_START	U(0xFFC00000)  /* start of MVME188 utility space */
+#define UTIL_SIZE	U(0x003FFFFF)  /* size of MVME188 utility space */
 
 #define INT_PRI_LEVEL	U(0xFFF4203E)	/* interrupt priority level */
 #define INT_MASK_LEVEL	U(0xFFF4203F)	/* interrupt mask level */
 
 #define LOCAL_IO_DEVS	U(0xFFF00000)	/* local IO devices */
 
-#define PCC2_ADDR			U(0xFFF42000)	/* PCCchip2 Regs */
-#define UTIL_ADDR			U(0xFFC02000)	/* PCCchip2 Regs */
-#define MEM_CTLR			U(0xFFF43000)	/* MEMC040 mem controller */
-#define SCC_ADDR			U(0xFFF45000) 	/* Cirrus Chip */
-#define LANCE_ADDR		U(0xFFF46000) 	/* 82596CA */
-#define SCSI_ADDR			U(0xFFF47000) 	/* NCR 710 address */
-#define NCR710_SIZE		U(0x00000040) 	/* NCR 710 size */
-#define MK48T08_ADDR		U(0xFFFC0000) 	/* BBRAM, TOD */
+#define PCC2_ADDR	U(0xFFF42000)	/* PCCchip2 Regs */
+#define UTIL_ADDR	U(0xFFC02000)	/* PCCchip2 Regs */
+#define MEM_CTLR	U(0xFFF43000)	/* MEMC040 mem controller */
+#define SCC_ADDR	U(0xFFF45000) 	/* Cirrus Chip */
+#define LANCE_ADDR	U(0xFFF46000) 	/* 82596CA */
+#define SCSI_ADDR	U(0xFFF47000) 	/* NCR 710 address */
+#define NCR710_SIZE	U(0x00000040) 	/* NCR 710 size */
+#define MK48T08_ADDR	U(0xFFFC0000) 	/* BBRAM, TOD */
 
-#define TOD_CAL_CTL		U(0xFFFC1FF8) 	/* calendar control register */
-#define TOD_CAL_SEC		U(0xFFFC1FF9) 	/* seconds */
-#define TOD_CAL_MIN		U(0xFFFC1FFA) 	/* minutes */
-#define TOD_CAL_HOUR		U(0xFFFC1FFB) 	/* hours */
-#define TOD_CAL_DOW		U(0xFFFC1FFC) 	/* Day Of the Week */
-#define TOD_CAL_DAY		U(0xFFFC1FFD) 	/* days */
-#define TOD_CAL_MON		U(0xFFFC1FFE) 	/* months */
-#define TOD_CAL_YEAR		U(0xFFFC1FFF) 	/* years */
+#define TOD_CAL_CTL	U(0xFFFC1FF8) 	/* calendar control register */
+#define TOD_CAL_SEC	U(0xFFFC1FF9) 	/* seconds */
+#define TOD_CAL_MIN	U(0xFFFC1FFA) 	/* minutes */
+#define TOD_CAL_HOUR	U(0xFFFC1FFB) 	/* hours */
+#define TOD_CAL_DOW	U(0xFFFC1FFC) 	/* Day Of the Week */
+#define TOD_CAL_DAY	U(0xFFFC1FFD) 	/* days */
+#define TOD_CAL_MON	U(0xFFFC1FFE) 	/* months */
+#define TOD_CAL_YEAR	U(0xFFFC1FFF) 	/* years */
 
-#define M187_IACK       U(0xFFFE0000)
-#define M197_IACK       U(0xFFF00100)
+#define M187_IACK	U(0xFFFE0000)
+#define M197_IACK	U(0xFFF00100)
 
 #endif __MACHINE_MVME1X7_H__
diff --git a/sys/arch/mvme88k/include/param.h b/sys/arch/mvme88k/include/param.h
index fb169df5b33..3d6013ab19f 100644
--- a/sys/arch/mvme88k/include/param.h
+++ b/sys/arch/mvme88k/include/param.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: param.h,v 1.12 2001/01/14 20:25:24 smurph Exp $ */
+/*	$OpenBSD: param.h,v 1.13 2001/02/01 03:38:18 smurph Exp $ */
 /*
  * Copyright (c) 1999 Steve Murphree, Jr.
  * Copyright (c) 1988 University of Utah.
@@ -40,7 +40,7 @@
  * from: Utah $Hdr: machparam.h 1.11 89/08/14$
  *
  *	@(#)param.h	7.8 (Berkeley) 6/28/91
- *	$Id: param.h,v 1.12 2001/01/14 20:25:24 smurph Exp $
+ *	$Id: param.h,v 1.13 2001/02/01 03:38:18 smurph Exp $
  */
 #ifndef _MACHINE_PARAM_H_
 #define _MACHINE_PARAM_H_
@@ -59,20 +59,20 @@
  * 88k.
  */
 
-#define  ALIGNBYTES           15	/* 64 bit alignment */
-#define  ALIGN(p)             (((u_int)(p) + ALIGNBYTES) & ~ALIGNBYTES)
-#define  ALIGNED_POINTER(p,t) ((((u_long)(p)) & (sizeof(t)-1)) == 0)
+#define  ALIGNBYTES		15		/* 64 bit alignment */
+#define  ALIGN(p)		(((u_int)(p) + ALIGNBYTES) & ~ALIGNBYTES)
+#define  ALIGNED_POINTER(p,t)	((((u_long)(p)) & (sizeof(t)-1)) == 0)
 
-#ifndef  NBPG
-#define  NBPG                 4096     /* bytes/page */
+#ifndef NBPG
+#define NBPG		4096		/* bytes/page */
 #endif /* NBPG */
-#define  PGOFSET              (NBPG-1) /* byte offset into page */
-#define  PGSHIFT              12       /* LOG2(NBPG) */
-#define  NPTEPG               (NBPG/(sizeof(u_int)))
+#define PGOFSET		(NBPG-1)	/* byte offset into page */
+#define PGSHIFT		12		/* LOG2(NBPG) */
+#define NPTEPG		(NBPG/(sizeof(u_int)))
 
-#define  NBSEG                (1<<22)  /* bytes/segment */
-#define  SEGOFSET             (NBSEG-1)/* byte offset into segment */
-#define  SEGSHIFT             22       /* LOG2(NBSEG) */
+#define NBSEG		(1<<22)		/* bytes/segment */
+#define SEGOFSET	(NBSEG-1)	/* byte offset into segment */
+#define SEGSHIFT	22	/* LOG2(NBSEG) */
 
 /*
  * 187 Bug uses the bottom 64k. We allocate ptes to map this into the
@@ -80,32 +80,32 @@
  * past this 64k. How does this change KERNBASE? XXX
  */
 
-#define  KERNBASE             0x0      /* start of kernel virtual */
-#define  BTOPKERNBASE         ((u_long)KERNBASE >> PGSHIFT)
+#define KERNBASE	0x0		/* start of kernel virtual */
+#define BTOPKERNBASE	((u_long)KERNBASE >> PGSHIFT)
 
-#define  DEV_BSIZE            512
-#define  DEV_BSHIFT           9        /* log2(DEV_BSIZE) */
-#define  BLKDEV_IOSIZE        2048     /* Should this be changed? XXX */
-#define  MAXPHYS              (64 * 1024)	/* max raw I/O transfer size */
+#define DEV_BSIZE	512
+#define DEV_BSHIFT	9		/* log2(DEV_BSIZE) */
+#define BLKDEV_IOSIZE	2048		/* Should this be changed? XXX */
+#define MAXPHYS		(64 * 1024)	/* max raw I/O transfer size */
 
-#define  CLSIZE               1
-#define  CLSIZELOG2           0
+#define CLSIZE		1
+#define CLSIZELOG2	0
 
 /* NOTE: SSIZE, SINCR and UPAGES must be multiples of CLSIZE */
-#define  SSIZE                1        /* initial stack size/NBPG */
-#define  SINCR                1        /* increment of stack/NBPG */
-#define  USPACE               ctob(UPAGES)
+#define SSIZE		1		/* initial stack size/NBPG */
+#define SINCR		1		/* increment of stack/NBPG */
+#define USPACE		ctob(UPAGES)
 
-#define  UPAGES               4                    /* pages of u-area */
-#define  UADDR                0xEEE00000	         /* address of u */
-#define  UVPN                 (UADDR>>PGSHIFT)     /* virtual page number of u */
-#define  KERNELSTACK          (UADDR+UPAGES*NBPG)  /* top of kernel stack */
+#define UPAGES		8		/* pages of u-area */
+#define UADDR		0xEEE00000	/* address of u */
+#define UVPN		(UADDR>>PGSHIFT)	/* virtual page number of u */
+#define KERNELSTACK	(UADDR+UPAGES*NBPG)	/* top of kernel stack */
 
-#define  PHYSIO_MAP_START     0xEEF00000
-#define  PHYSIO_MAP_SIZE      0x00100000
-#define  IOMAP_MAP_START      0xEF000000 /* VME etc */
-#define  IOMAP_SIZE           0x018F0000
-#define  NIOPMAP              32
+#define PHYSIO_MAP_START	0xEEF00000
+#define PHYSIO_MAP_SIZE		0x00100000
+#define IOMAP_MAP_START		0xEF000000	/* VME etc */
+#define IOMAP_SIZE		0x018F0000
+#define NIOPMAP			32
 
 /*
  * Constants related to network buffer management.
@@ -114,42 +114,42 @@
  * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple
  * of the hardware page size.
  */
-#define  MSIZE		128		/* size of an mbuf */
-#define  MCLSHIFT	11		/* convert bytes to m_buf clusters */
-#define  MCLBYTES	(1 << MCLSHIFT)	/* size of a m_buf cluster */
-#define  MCLOFSET	(MCLBYTES - 1)	/* offset within a m_buf cluster */
+#define MSIZE		128		/* size of an mbuf */
+#define MCLSHIFT	11		/* convert bytes to m_buf clusters */
+#define MCLBYTES	(1 << MCLSHIFT)	/* size of a m_buf cluster */
+#define MCLOFSET	(MCLBYTES - 1)	/* offset within a m_buf cluster */
 
-#ifndef  NMBCLUSTERS
+#ifndef NMBCLUSTERS
 #ifdef   GATEWAY
-#define  NMBCLUSTERS          1024     /* map size, max cluster allocation */
+#define NMBCLUSTERS	1024		/* map size, max cluster allocation */
 #else
-#define  NMBCLUSTERS          512      /* map size, max cluster allocation */
+#define NMBCLUSTERS	512		/* map size, max cluster allocation */
 #endif
 #endif
 
 /*
  * Size of kernel malloc arena in CLBYTES-sized logical pages
  */ 
-#ifndef  NKMEMCLUSTERS
-#define  NKMEMCLUSTERS        (4096*1024/CLBYTES)
+#ifndef NKMEMCLUSTERS
+#define NKMEMCLUSTERS	(4096*1024/CLBYTES)
 #endif
 
 #define MSGBUFSIZE	4096
 
 /* pages ("clicks") to disk blocks */
-#define  ctod(x)              ((x)<<(PGSHIFT-DEV_BSHIFT))
-#define  dtoc(x)              ((x)>>(PGSHIFT-DEV_BSHIFT))
-#define  dtob(x)              ((x)<<DEV_BSHIFT)
+#define ctod(x)			((x)<<(PGSHIFT-DEV_BSHIFT))
+#define dtoc(x)			((x)>>(PGSHIFT-DEV_BSHIFT))
+#define dtob(x)			((x)<<DEV_BSHIFT)
 
 /* pages to bytes */
-#define  ctob(x)              ((x)<<PGSHIFT)
+#define ctob(x)			((x)<<PGSHIFT)
 
 /* bytes to pages */
-#define  btoc(x)              (((unsigned)(x)+(NBPG-1))>>PGSHIFT)
+#define btoc(x)			(((unsigned)(x)+(NBPG-1))>>PGSHIFT)
 
-#define  btodb(bytes)         /* calculates (bytes / DEV_BSIZE) */ \
+#define btodb(bytes)         /* calculates (bytes / DEV_BSIZE) */ \
 	((unsigned)(bytes) >> DEV_BSHIFT)
-#define  dbtob(db)            /* calculates (db * DEV_BSIZE) */ \
+#define dbtob(db)            /* calculates (db * DEV_BSIZE) */ \
 	((unsigned)(db) << DEV_BSHIFT)
 
 /*
@@ -158,13 +158,13 @@
  * field from the disk label.
  * For now though just use DEV_BSIZE.
  */
-#define  bdbtofsb(bn)         ((bn) / (BLKDEV_IOSIZE/DEV_BSIZE))
+#define bdbtofsb(bn)		((bn) / (BLKDEV_IOSIZE/DEV_BSIZE))
 
 /*
  * Mach derived conversion macros
  */
-#define  mvme88k_btop(x)      ((unsigned)(x) >> PGSHIFT)
-#define  mvme88k_ptob(x)      ((unsigned)(x) << PGSHIFT)
+#define mvme88k_btop(x)		((unsigned)(x) >> PGSHIFT)
+#define mvme88k_ptob(x)		((unsigned)(x) << PGSHIFT)
 
 #include <machine/psl.h>
 
@@ -179,9 +179,10 @@ extern int cpumod;
 /*
  * Values for the cputyp variable.
  */
-#define  CPU_187              0x187
-#define  CPU_188              0x188
-#define  CPU_197              0x197
+#define CPU_187		0x187
+#define CPU_188		0x188
+#define CPU_197		0x197
+#define CPU_8120	0x8120
 #endif /* !_MACHINE_PARAM_H_ */
 
 
diff --git a/sys/arch/mvme88k/include/reg.h b/sys/arch/mvme88k/include/reg.h
index 00c3ae9060f..160fb875b71 100644
--- a/sys/arch/mvme88k/include/reg.h
+++ b/sys/arch/mvme88k/include/reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: reg.h,v 1.6 2001/01/12 07:29:27 smurph Exp $ */
+/*	$OpenBSD: reg.h,v 1.7 2001/02/01 03:38:18 smurph Exp $ */
 /*
  * Copyright (c) 1999 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -78,7 +78,7 @@ struct reg {
     unsigned isr;          /* MVME197 */
     unsigned ilar;         /* MVME197 */
     unsigned ipar;         /* MVME197 */
-    unsigned pad;          /* alignment */
+    unsigned cpu;          /* cpu number */
 };
 
 struct fpreg {
diff --git a/sys/arch/mvme88k/include/trap.h b/sys/arch/mvme88k/include/trap.h
index ea39c46f055..681804c94aa 100644
--- a/sys/arch/mvme88k/include/trap.h
+++ b/sys/arch/mvme88k/include/trap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.h,v 1.6 2001/01/14 20:25:24 smurph Exp $ */
+/*	$OpenBSD: trap.h,v 1.7 2001/02/01 03:38:18 smurph Exp $ */
 /* 
  * Mach Operating System
  * Copyright (c) 1992 Carnegie Mellon University
@@ -34,43 +34,43 @@
  * Trap type values
  */
 
-#define T_RESADFLT	0		/* reserved addressing fault */
-#define T_PRIVINFLT	1		/* privileged instruction fault */
-#define T_RESOPFLT	2		/* reserved operand fault */
+#define T_RESADFLT	0	/* reserved addressing fault */
+#define T_PRIVINFLT	1	/* privileged instruction fault */
+#define T_RESOPFLT	2	/* reserved operand fault */
 
 /* End of known constants */
 
-#define T_INSTFLT    3		/* instruction access exception */
-#define T_DATAFLT    4		/* data access exception */
-#define T_MISALGNFLT 5		/* misaligned access exception */
-#define T_ILLFLT     6		/* unimplemented opcode exception */
-#define T_BNDFLT     7		/* bounds check violation exception */
-#define T_ZERODIV    8		/* illegal divide exception */
-#define T_OVFFLT     9		/* integer overflow exception */
-#define T_ERRORFLT	10		/* error exception */
-#define T_FPEPFLT    11		/* floating point precise exception */
-#define T_FPEIFLT    12		/* floating point imprecise exception */
-#define T_ASTFLT	   13		/* software trap */
+#define T_INSTFLT	3	/* instruction access exception */
+#define T_DATAFLT	4	/* data access exception */
+#define T_MISALGNFLT	5	/* misaligned access exception */
+#define T_ILLFLT	6	/* unimplemented opcode exception */
+#define T_BNDFLT	7	/* bounds check violation exception */
+#define T_ZERODIV	8	/* illegal divide exception */
+#define T_OVFFLT	9	/* integer overflow exception */
+#define T_ERRORFLT	10	/* error exception */
+#define T_FPEPFLT	11	/* floating point precise exception */
+#define T_FPEIFLT	12	/* floating point imprecise exception */
+#define T_ASTFLT	13	/* software trap */
 #if	DDB
-#define	T_KDB_ENTRY	14		/* force entry to kernel debugger */
-#define T_KDB_BREAK	15		/* break point hit */
-#define T_KDB_TRACE	16		/* trace */
+#define	T_KDB_ENTRY	14	/* force entry to kernel debugger */
+#define T_KDB_BREAK	15	/* break point hit */
+#define T_KDB_TRACE	16	/* trace */
 #endif /* DDB */
-#define T_UNKNOWNFLT	17		/* unknown exception */
-#define T_SIGTRAP	   18		/* generate SIGTRAP */
-#define T_SIGSYS	   19		/* generate SIGSYS */
-#define T_STEPBPT	   20		/* special breakpoint for single step */
-#define T_USERBPT	   21		/* user set breakpoint (for debugger) */
-#define T_SYSCALL	   22		/* Syscall */
-#define T_NON_MASK	23		/* MVME197 Non-Maskable Interrupt */
+#define T_UNKNOWNFLT	17	/* unknown exception */
+#define T_SIGTRAP	18	/* generate SIGTRAP */
+#define T_SIGSYS	19	/* generate SIGSYS */
+#define T_STEPBPT	20	/* special breakpoint for single step */
+#define T_USERBPT	21	/* user set breakpoint (for debugger) */
+#define T_SYSCALL	22	/* Syscall */
+#define T_NON_MASK	23	/* MVME197 Non-Maskable Interrupt */
 #if	DDB
-#define	T_KDB_WATCH	24		/* watchpoint hit */
+#define	T_KDB_WATCH	24	/* watchpoint hit */
 #endif /* DDB */
-#define T_197_READ   25    /* MVME197 Data Read Miss (Software Table Searches) */
-#define T_197_WRITE  26    /* MVME197 Data Write Miss (Software Table Searches) */
-#define T_197_INST   27    /* MVME197 Inst ATC Miss (Software Table Searches) */
-#define T_INT        28    /* interrupt exception */
-#define T_USER       29		/* user mode fault */
+#define T_197_READ	25	/* MVME197 Data Read Miss (Software Table Searches) */
+#define T_197_WRITE	26	/* MVME197 Data Write Miss (Software Table Searches) */
+#define T_197_INST	27	/* MVME197 Inst ATC Miss (Software Table Searches) */
+#define T_INT		28	/* interrupt exception */
+#define T_USER		29	/* user mode fault */
 
 #endif __MACHINE_TRAP_H__