No need to mask misaligned address exceptions for global flush or invalidate

operations (those do not take a page number in the low address bits of the
88410 control register).

1 files changed, 14 insertions, 21 deletions

diff --git a/sys/arch/mvme88k/mvme88k/m88410.c b/sys/arch/mvme88k/mvme88k/m88410.c
index a7c767eda6c..7537f81399a 100644
--- a/sys/arch/mvme88k/mvme88k/m88410.c
+++ b/sys/arch/mvme88k/mvme88k/m88410.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88410.c,v 1.1 2005/12/12 20:36:33 miod Exp $	*/
+/*	$OpenBSD: m88410.c,v 1.2 2006/05/07 17:44:28 miod Exp $	*/
 /*
  * Copyright (c) 2001 Steve Murphree, Jr.
  * All rights reserved.
@@ -54,7 +54,10 @@ mc88410_flush_page(paddr_t physaddr)
 	bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR);
 	bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR);
 
-	/* mask misaligned exceptions */
+	/*
+	 * Since the page number is unlikely to be a multiple of 4, we need
+	 * to mask misaligned exceptions.
+	 */
 	set_psr((psr = get_psr()) | PSR_MXM);
 
 	/* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
@@ -70,7 +73,7 @@ mc88410_flush_page(paddr_t physaddr)
 	    "or   r3, r0, r0;"
 	    "st.d r2, %0, 0" : : "r" (xccaddr) : "r2", "r3");
 
-	/* spin until the operation starts */
+	/* spin until the operation is complete */
 	while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) != 0)
 		;
 
@@ -84,15 +87,11 @@ mc88410_flush_page(paddr_t physaddr)
 void
 mc88410_flush(void)
 {
-	u_int psr;
 	u_int16_t bs_gcsr, bs_romcr;
 
 	bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR);
 	bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR);
 
-	/* mask misaligned exceptions */
-	set_psr((psr = get_psr()) | PSR_MXM);
-
 	/* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
 	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) =
 	    bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1);
@@ -106,13 +105,10 @@ mc88410_flush(void)
 	    "or   r3, r0, r0;"
 	    "st.d r2, %0, 0" : : "r" (XCC_ADDR) : "r2", "r3");
 
-	/* spin until the operation starts */
+	/* spin until the operation is complete */
 	while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) != 0)
 		;
 
-	/* restore PSR and friends */
-        set_psr(psr);
-	flush_pipeline();
 	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr;
 	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr;
 }
@@ -120,15 +116,12 @@ mc88410_flush(void)
 void
 mc88410_inval(void)
 {
-	u_int psr;
 	u_int16_t bs_gcsr, bs_romcr;
+	u_int32_t dummy;
 
 	bs_gcsr = *(volatile u_int16_t *)(BS_BASE + BS_GCSR);
 	bs_romcr = *(volatile u_int16_t *)(BS_BASE + BS_ROMCR);
 
-	/* mask misaligned exceptions */
-	set_psr((psr = get_psr()) | PSR_MXM);
-
 	/* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
 	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) =
 	    bs_romcr & ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN1);
@@ -142,13 +135,13 @@ mc88410_inval(void)
 	    "or   r3, r0, r0;"
 	    "st.d r2, %0, 0" : : "r" (XCC_ADDR) : "r2", "r3");
 
-	/* wait for the operation to be completed */
-	while (*(volatile u_int32_t *)(BS_BASE + BS_XCCR) != 0)
-		;
+	/*
+	 * The 88410 will not let the 88110 access it until the
+	 * invalidate all operation is complete. Simply force a read
+	 * access which will spin as long as necessary.
+	 */
+	dummy = *(volatile u_int32_t *)(BS_BASE + BS_XCCR);
 
-	/* restore PSR and friends */
-        set_psr(psr);
-	flush_pipeline();
 	*(volatile u_int16_t *)(BS_BASE + BS_GCSR) = bs_gcsr;
 	*(volatile u_int16_t *)(BS_BASE + BS_ROMCR) = bs_romcr;
 }