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authorSteve Murphree <smurph@cvs.openbsd.org>2001-12-13 08:55:53 +0000
committerSteve Murphree <smurph@cvs.openbsd.org>2001-12-13 08:55:53 +0000
commit473b535f76f86533ee5e407fe116de57f486b4ab (patch)
tree4f23697fe5a745e7407f507f3b3a3e82e9bd7150 /sys/arch/mvme88k
parent73fa188e07813a02c13455459ffa53a64e277416 (diff)
Support for MVME197 completed. Fix SPL defs.
Diffstat (limited to 'sys/arch/mvme88k')
-rw-r--r--sys/arch/mvme88k/conf/GENERIC10
-rw-r--r--sys/arch/mvme88k/conf/M1875
-rw-r--r--sys/arch/mvme88k/conf/M1887
-rw-r--r--sys/arch/mvme88k/conf/M19737
-rw-r--r--sys/arch/mvme88k/conf/files.mvme88k14
-rw-r--r--sys/arch/mvme88k/ddb/db_disasm.c68
-rw-r--r--sys/arch/mvme88k/ddb/db_interface.c134
-rw-r--r--sys/arch/mvme88k/ddb/db_sstep.c87
-rw-r--r--sys/arch/mvme88k/ddb/db_trace.c1545
-rw-r--r--sys/arch/mvme88k/dev/bugtty.c17
-rw-r--r--sys/arch/mvme88k/dev/busswfunc.h9
-rw-r--r--sys/arch/mvme88k/dev/busswitch.c153
-rw-r--r--sys/arch/mvme88k/dev/busswitchreg.h10
-rw-r--r--sys/arch/mvme88k/dev/cl.c41
-rw-r--r--sys/arch/mvme88k/dev/clock.c8
-rw-r--r--sys/arch/mvme88k/dev/dart.c9
-rw-r--r--sys/arch/mvme88k/dev/if_ie.c19
-rw-r--r--sys/arch/mvme88k/dev/if_ve.c10
-rw-r--r--sys/arch/mvme88k/dev/mainbus.c4
-rw-r--r--sys/arch/mvme88k/dev/nvram.c18
-rw-r--r--sys/arch/mvme88k/dev/pcctwo.c75
-rw-r--r--sys/arch/mvme88k/dev/pcctwofunc.h6
-rw-r--r--sys/arch/mvme88k/dev/pcctworeg.h3
-rw-r--r--sys/arch/mvme88k/dev/sclock.c6
-rw-r--r--sys/arch/mvme88k/dev/sram.c14
-rw-r--r--sys/arch/mvme88k/dev/ssh.c4
-rw-r--r--sys/arch/mvme88k/dev/sshdma.c95
-rw-r--r--sys/arch/mvme88k/dev/syscon.c4
-rw-r--r--sys/arch/mvme88k/dev/vme.c27
-rw-r--r--sys/arch/mvme88k/dev/vs.c3
-rw-r--r--sys/arch/mvme88k/dev/vsdma.c8
-rw-r--r--sys/arch/mvme88k/dev/vx.c14
-rw-r--r--sys/arch/mvme88k/include/asm.h27
-rw-r--r--sys/arch/mvme88k/include/asm_macro.h12
-rw-r--r--sys/arch/mvme88k/include/board.h11
-rw-r--r--sys/arch/mvme88k/include/cmmu.h166
-rw-r--r--sys/arch/mvme88k/include/cpu.h19
-rw-r--r--sys/arch/mvme88k/include/cpu_number.h5
-rw-r--r--sys/arch/mvme88k/include/db_machdep.h26
-rw-r--r--sys/arch/mvme88k/include/exception_vectors2.h276
-rw-r--r--sys/arch/mvme88k/include/intr.h7
-rw-r--r--sys/arch/mvme88k/include/locore.h38
-rw-r--r--sys/arch/mvme88k/include/m88110.h322
-rw-r--r--sys/arch/mvme88k/include/m8820x.h (renamed from sys/arch/mvme88k/include/m882xx.h)107
-rw-r--r--sys/arch/mvme88k/include/m88410.h142
-rw-r--r--sys/arch/mvme88k/include/mmu.h17
-rw-r--r--sys/arch/mvme88k/include/mvme187.h74
-rw-r--r--sys/arch/mvme88k/include/mvme197.h74
-rw-r--r--sys/arch/mvme88k/include/mvme1x7.h7
-rw-r--r--sys/arch/mvme88k/include/param.h24
-rw-r--r--sys/arch/mvme88k/include/psl.h23
-rw-r--r--sys/arch/mvme88k/include/reg.h22
-rw-r--r--sys/arch/mvme88k/include/signal.h14
-rw-r--r--sys/arch/mvme88k/include/trap.h23
-rw-r--r--sys/arch/mvme88k/mvme88k/cmmu.c793
-rw-r--r--sys/arch/mvme88k/mvme88k/eh.S2748
-rw-r--r--sys/arch/mvme88k/mvme88k/genassym.cf26
-rw-r--r--sys/arch/mvme88k/mvme88k/locore.S88
-rw-r--r--sys/arch/mvme88k/mvme88k/locore_asm_routines.S241
-rw-r--r--sys/arch/mvme88k/mvme88k/locore_c_routines.c102
-rw-r--r--sys/arch/mvme88k/mvme88k/m197_cmmu.c800
-rw-r--r--sys/arch/mvme88k/mvme88k/m88100_fp.S6
-rw-r--r--sys/arch/mvme88k/mvme88k/m88110.c1107
-rw-r--r--sys/arch/mvme88k/mvme88k/m88110_fp.S12
-rw-r--r--sys/arch/mvme88k/mvme88k/m88110_mmu.S49
-rw-r--r--sys/arch/mvme88k/mvme88k/m8820x.c (renamed from sys/arch/mvme88k/mvme88k/m18x_cmmu.c)1039
-rw-r--r--sys/arch/mvme88k/mvme88k/machdep.c528
-rw-r--r--sys/arch/mvme88k/mvme88k/pmap.c240
-rw-r--r--sys/arch/mvme88k/mvme88k/pmap_table.c13
-rw-r--r--sys/arch/mvme88k/mvme88k/process.S12
-rw-r--r--sys/arch/mvme88k/mvme88k/trap.c481
-rw-r--r--sys/arch/mvme88k/mvme88k/vm_machdep.c7
-rw-r--r--sys/arch/mvme88k/stand/bugcrt/bugcrt.c4
-rw-r--r--sys/arch/mvme88k/stand/bugcrt/crt.c4
74 files changed, 6277 insertions, 5923 deletions
diff --git a/sys/arch/mvme88k/conf/GENERIC b/sys/arch/mvme88k/conf/GENERIC
index ecac7fa8358..dd41ea96f56 100644
--- a/sys/arch/mvme88k/conf/GENERIC
+++ b/sys/arch/mvme88k/conf/GENERIC
@@ -1,12 +1,14 @@
-# $OpenBSD: GENERIC,v 1.22 2001/11/27 05:26:34 miod Exp $
+# $OpenBSD: GENERIC,v 1.23 2001/12/13 08:55:51 smurph Exp $
machine mvme88k
include "../../../conf/GENERIC"
-option MVME187 # support for 187
-option MVME188 # support for 188
-#option MVME197 # support for 197
+option M88100 # support for mc88100 1st generation RISC
+option M88110 # support for mc88120 2ond generation RISC
+option MVME187 # support for 187 (requires M88100)
+option MVME188 # support for 188 (requires M88100)
+#option MVME197 # support for 197 (requires M88110)
option "NCPUS=1" # number of CPUs supported (max 4)
option BUGMAP # use the Bug ROM VME mappings
#option DEBUG # print debugging statements
diff --git a/sys/arch/mvme88k/conf/M187 b/sys/arch/mvme88k/conf/M187
index de5ba16fd14..42f0534c32a 100644
--- a/sys/arch/mvme88k/conf/M187
+++ b/sys/arch/mvme88k/conf/M187
@@ -1,10 +1,11 @@
-# $OpenBSD: M187,v 1.14 2001/11/27 05:26:34 miod Exp $
+# $OpenBSD: M187,v 1.15 2001/12/13 08:55:51 smurph Exp $
machine mvme88k
include "../../../conf/GENERIC"
-option MVME187 # support for 187
+option M88100 # support for mc88100 1st generation RISC
+option MVME187 # support for 187 (requires M88100)
option "NCPUS=1" # Number of cpus supported (max 4)
option BUGMAP # use Bug Rom VME Mappings
#option DEBUG # print debugging statements
diff --git a/sys/arch/mvme88k/conf/M188 b/sys/arch/mvme88k/conf/M188
index bce658c7a96..0da9a562584 100644
--- a/sys/arch/mvme88k/conf/M188
+++ b/sys/arch/mvme88k/conf/M188
@@ -1,10 +1,13 @@
-# $OpenBSD: M188,v 1.11 2001/11/27 05:26:34 miod Exp $
+# $OpenBSD: M188,v 1.12 2001/12/13 08:55:51 smurph Exp $
machine mvme88k
include "../../../conf/GENERIC"
-option MVME188 # support for 187
+# processors this kernel should support
+
+option M88100 # support for mc88100 1st generation RISC
+option MVME188 # support for 188 (requires M88100)
option "NCPUS=1" # Number of cpus supported (max 4)
option BUGMAP # use Bug Rom VME Mappings
#option DEBUG # print debugging statements
diff --git a/sys/arch/mvme88k/conf/M197 b/sys/arch/mvme88k/conf/M197
index a65288c79a1..68804b99a1d 100644
--- a/sys/arch/mvme88k/conf/M197
+++ b/sys/arch/mvme88k/conf/M197
@@ -1,10 +1,13 @@
-# $OpenBSD: M197,v 1.9 2001/11/27 05:26:34 miod Exp $
+# $OpenBSD: M197,v 1.10 2001/12/13 08:55:51 smurph Exp $
machine mvme88k
include "../../../conf/GENERIC"
-option MVME197 # support for 197
+# processors this kernel should support
+
+option M88110 # support for mc88120 2ond generation RISC
+option MVME197 # support for 197 (requires M88110)
option "NCPUS=1" # Number of cpus supported (max 4)
option BUGMAP # use Bug Rom VME Mappings
#option DEBUG # print debugging statements
@@ -22,10 +25,10 @@ mainbus0 at root
# ------------------------------ mainbus devices ------------------------
bugtty0 at mainbus0
-busswitch0 at mainbus0 addr 0xfff00000
+bussw0 at mainbus0 addr 0xfff00000
# ----------------------------- busswitch devices -----------------------
-pcctwo0 at busswitch0 offset 0x42000
+pcctwo0 at bussw0 offset 0x42000
# ------------------------------ pcctwo devices -------------------------
clock0 at pcctwo0 ipl 5
@@ -44,19 +47,19 @@ vmes0 at vme0
vmel0 at vme0
# ------------------------------ vmes0 devices -------------------------
-vx0 at vmes0 addr 0xff780000 ipl 3 vec 0x70 len 0x10000
-vx1 at vmes0 addr 0xff790000 ipl 3 vec 0x71 len 0x10000
-vx2 at vmes0 addr 0xff7a0000 ipl 3 vec 0x72 len 0x10000
-vx3 at vmes0 addr 0xff7b0000 ipl 3 vec 0x73 len 0x10000
-ve0 at vmes0 addr 0xffff1200 ipl 1 vec 0x74 len 0x100
-ve1 at vmes0 addr 0xffff1400 ipl 1 vec 0x75 len 0x100
-ve2 at vmes0 addr 0xffff1600 ipl 1 vec 0x76 len 0x100
-vs0 at vmes0 addr 0xffff9000 ipl 2 vec 0x80 len 0x800
-vs1 at vmes0 addr 0xffff9800 ipl 2 vec 0x82 len 0x800
-vs2 at vmes0 addr 0xffff4800 ipl 2 vec 0x84 len 0x800
-vs3 at vmes0 addr 0xffff5800 ipl 2 vec 0x86 len 0x800
-vs4 at vmes0 addr 0xffff7000 ipl 2 vec 0x88 len 0x800
-vs5 at vmes0 addr 0xffff7800 ipl 2 vec 0x8a len 0x800
+vx0 at vmes0 addr 0xff780000 ipl 3 len 0x10000
+vx1 at vmes0 addr 0xff790000 ipl 3 len 0x10000
+vx2 at vmes0 addr 0xff7a0000 ipl 3 len 0x10000
+vx3 at vmes0 addr 0xff7b0000 ipl 3 len 0x10000
+ve0 at vmes0 addr 0xffff1200 ipl 1 len 0x100
+ve1 at vmes0 addr 0xffff1400 ipl 1 len 0x100
+ve2 at vmes0 addr 0xffff1600 ipl 1 len 0x100
+vs0 at vmes0 addr 0xffff9000 ipl 2 len 0x800
+vs1 at vmes0 addr 0xffff9800 ipl 2 len 0x800
+vs2 at vmes0 addr 0xffff4800 ipl 2 len 0x800
+vs3 at vmes0 addr 0xffff5800 ipl 2 len 0x800
+vs4 at vmes0 addr 0xffff7000 ipl 2 len 0x800
+vs5 at vmes0 addr 0xffff7800 ipl 2 len 0x800
# ------------------------------- vs0 devices --------------------------
scsibus* at vs?
diff --git a/sys/arch/mvme88k/conf/files.mvme88k b/sys/arch/mvme88k/conf/files.mvme88k
index c0f8958e1dd..9de76315669 100644
--- a/sys/arch/mvme88k/conf/files.mvme88k
+++ b/sys/arch/mvme88k/conf/files.mvme88k
@@ -1,4 +1,4 @@
-# $OpenBSD: files.mvme88k,v 1.15 2001/11/23 00:39:41 miod Exp $
+# $OpenBSD: files.mvme88k,v 1.16 2001/12/13 08:55:51 smurph Exp $
#
maxpartitions 16
@@ -14,12 +14,12 @@ file arch/mvme88k/dev/bugtty.c bugtty needs-count
device cpu
attach cpu at mainbus
-device busswitch { [offset = -1], [ ipl = 0 ] }
-attach busswitch at mainbus
-file arch/mvme88k/dev/busswitch.c busswitch needs-count
+device bussw { [offset = -1], [ ipl = 0 ] }
+attach bussw at mainbus
+file arch/mvme88k/dev/bussw.c bussw needs-count
device pcctwo { [offset = -1], [ ipl = 0 ] }
-attach pcctwo at busswitch, mainbus
+attach pcctwo at bussw, mainbus
file arch/mvme88k/dev/pcctwo.c pcctwo needs-count
device syscon { [offset = -1], [ ipl = 0 ] }
@@ -88,8 +88,8 @@ file netns/ns_cksum.c ns
file arch/mvme88k/mvme88k/autoconf.c
file arch/mvme88k/mvme88k/conf.c
file arch/mvme88k/mvme88k/cmmu.c
-file arch/mvme88k/mvme88k/m18x_cmmu.c mvme187 | mvme188
-file arch/mvme88k/mvme88k/m197_cmmu.c mvme197
+file arch/mvme88k/mvme88k/m8820x.c mvme187 | mvme188
+file arch/mvme88k/mvme88k/m88110.c mvme197
file arch/mvme88k/mvme88k/disksubr.c
file arch/mvme88k/mvme88k/dkbad.c
file arch/mvme88k/mvme88k/eh.S
diff --git a/sys/arch/mvme88k/ddb/db_disasm.c b/sys/arch/mvme88k/ddb/db_disasm.c
index 343433dfd45..704b4eefb17 100644
--- a/sys/arch/mvme88k/ddb/db_disasm.c
+++ b/sys/arch/mvme88k/ddb/db_disasm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: db_disasm.c,v 1.6 2001/08/26 02:37:00 miod Exp $ */
+/* $OpenBSD: db_disasm.c,v 1.7 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -30,6 +30,7 @@
* m88k disassembler for use in ddb
*/
+#include <sys/param.h> /* cputyp and friends */
#include <sys/types.h>
#include <machine/db_machdep.h>
@@ -47,7 +48,7 @@ static char *condname[6] = {
"gt0 ", "eq0 ", "ge0 ", "lt0 ", "ne0 ", "le0 "
};
-static char *ctrlreg[64] = {
+static char *m88100_ctrlreg[64] = {
"cr0(PID) ",
"cr1(PSR) ",
"cr2(EPSR) ",
@@ -83,6 +84,60 @@ static char *ctrlreg[64] = {
"fcr63(FPCR)"
};
+static char *m88110_ctrlreg[64] = {
+ "cr0(PID) ",
+ "cr1(PSR) ",
+ "cr2(EPSR) ",
+ 0,
+ "cr4(EXIP) ",
+ "cr5(ENIP) ",
+ 0,
+ "cr7(VBR) ",
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ "cr14(RES1) ",
+ "cr15(RES2) ",
+ "cr16(SR0) ",
+ "cr17(SR1) ",
+ "cr18(SR2) ",
+ "cr19(SR3) ",
+ "cr20(SR4) ",
+ 0,
+ 0,
+ 0,
+ 0,
+ "cr25(ICMD) ",
+ "cr26(ICTL) ",
+ "cr27(ISAR) ",
+ "cr28(ISAP) ",
+ "cr29(IUAP) ",
+ "cr30(IIR) ",
+ "cr31(IBP) ",
+ "cr32(IPPU) ",
+ "cr33(IPPL) ",
+ "cr34(ISR) ",
+ "cr35(ILAR) ",
+ "cr36(IPAR) ",
+ 0,0,0,
+ "cr40(DCMD) ",
+ "cr41(DCTL) ",
+ "cr42(DSAR) ",
+ "cr43(DSAP) ",
+ "cr44(DUAP) ",
+ "cr45(DIR) ",
+ "cr46(DBP) ",
+ "cr47(DPPU) ",
+ "cr48(DPPL) ",
+ "cr49(DSR) ",
+ "cr50(DLAR) ",
+ "cr51(DPAR) ",
+ 0,0,0,0,0,0,0,0,0,0,0,0
+};
+
#define printval(x) \
do { \
if ((x) < 0) \
@@ -142,11 +197,14 @@ ctrlregs(int inst, char *opcode, long iadr)
db_printf("\t%s",opcode);
if ( L6inst == 010 || L6inst == 011 )
- db_printf("\t\tr%-3d,%s", rd, ctrlreg[creg]);
+ db_printf("\t\tr%-3d,%s", rd,
+ cputyp == CPU_88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
else if ( L6inst == 020 || L6inst == 021 )
- db_printf("\t\tr%-3d,%s", rs1, ctrlreg[creg]);
+ db_printf("\t\tr%-3d,%s", rs1,
+ cputyp == CPU_88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
else
- db_printf("\t\tr%-3d,r%-3d,%s", rd, rs1, ctrlreg[creg]);
+ db_printf("\t\tr%-3d,r%-3d,%s", rd, rs1,
+ cputyp == CPU_88100 ? m88100_ctrlreg[creg] : m88110_ctrlreg[creg]);
}
diff --git a/sys/arch/mvme88k/ddb/db_interface.c b/sys/arch/mvme88k/ddb/db_interface.c
index 057c406afed..0e362e1c255 100644
--- a/sys/arch/mvme88k/ddb/db_interface.c
+++ b/sys/arch/mvme88k/ddb/db_interface.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: db_interface.c,v 1.18 2001/11/27 05:37:00 miod Exp $ */
+/* $OpenBSD: db_interface.c,v 1.19 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -37,12 +37,13 @@
#include <uvm/uvm_extern.h>
-#include <machine/m882xx.h> /* CMMU defs */
-#include <machine/trap.h> /* current_thread() */
-#include <machine/db_machdep.h> /* local ddb stuff */
-#include <machine/bugio.h> /* bug routines */
+#include <machine/asm_macro.h> /* flush_pipeline() */
+#include <machine/trap.h> /* current_thread() */
+#include <machine/db_machdep.h> /* local ddb stuff */
+#include <machine/bugio.h> /* bug routines */
#include <machine/locore.h>
-#include <machine/mmu.h>
+#include <machine/cmmu.h> /* CMMU defs */
+#include <machine/m8820x.h> /* temporary unitl I can do M88100 defs */
#include <machine/cpu_number.h>
#include <ddb/db_command.h>
@@ -70,6 +71,7 @@ char *db_task_name __P((void));
int m88k_dmx_print __P((unsigned, unsigned, unsigned, unsigned));
void m88k_db_pause __P((unsigned));
void m88k_db_print_frame __P((db_expr_t, int, db_expr_t, char *));
+void m88k_db_registers __P((db_expr_t, int, db_expr_t, char *));
void m88k_db_where __P((db_expr_t, int, db_expr_t, char *));
void m88k_db_frame_search __P((db_expr_t, int, db_expr_t, char *));
void m88k_db_iflush __P((db_expr_t, int, db_expr_t, char *));
@@ -254,7 +256,7 @@ m88k_db_print_frame(addr, have_addr, count, modif)
R(24), R(25), R(26), R(27), R(28), R(29));
db_printf("R30-31: 0x%08x 0x%08x\n", R(30), R(31));
- db_printf("sxip: 0x%08x ", s->sxip & ~3);
+ db_printf("%sxip: 0x%08x ", cputyp == CPU_88110 ? "e" : "s", s->sxip & ~3);
db_find_xtrn_sym_and_offset((db_addr_t)IPMASK(s->sxip),
&name, &offset);
if (name != 0 && (unsigned)offset <= db_maxoff)
@@ -262,27 +264,36 @@ m88k_db_print_frame(addr, have_addr, count, modif)
db_printf("\n");
if (s->snip != s->sxip + 4) {
- db_printf("snip: 0x%08x ", s->snip);
+ db_printf("%snip: 0x%08x ", cputyp == CPU_88110 ? "e" : "s", s->snip);
db_find_xtrn_sym_and_offset((db_addr_t)IPMASK(s->snip),
&name, &offset);
if (name != 0 && (unsigned)offset <= db_maxoff)
db_printf("%s+0x%08x", name, (unsigned)offset);
db_printf("\n");
}
-
- if (s->sfip != s->snip + 4) {
- db_printf("sfip: 0x%08x ", s->sfip);
- db_find_xtrn_sym_and_offset((db_addr_t)IPMASK(s->sfip),
- &name, &offset);
- if (name != 0 && (unsigned)offset <= db_maxoff)
- db_printf("%s+0x%08x", name, (unsigned)offset);
- db_printf("\n");
+
+ if (cputyp != CPU_88110) {
+ if (s->sfip != s->snip + 4) {
+ db_printf("sfip: 0x%08x ", s->sfip);
+ db_find_xtrn_sym_and_offset((db_addr_t)IPMASK(s->sfip),
+ &name, &offset);
+ if (name != 0 && (unsigned)offset <= db_maxoff)
+ db_printf("%s+0x%08x", name, (unsigned)offset);
+ db_printf("\n");
+ }
+ } else {
+ db_printf("fpsr: 0x%08x fpcr: 0x%08x fpecr: 0x%08x\n",
+ s->fpsr, s->fpcr, s->fpecr);
+ db_printf("dsap 0x%08x duap 0x%08x dsr 0x%08x dlar 0x%08x dpar 0x%08x\n",
+ s->dsap, s->duap, s->dsr, s->dlar, s->dpar);
+ db_printf("isap 0x%08x iuap 0x%08x isr 0x%08x ilar 0x%08x ipar 0x%08x\n",
+ s->isap, s->iuap, s->isr, s->ilar, s->ipar);
}
- db_printf("vector: 0x%02x interrupt mask: 0x%08x\n",
- s->vector, s->mask);
db_printf("epsr: 0x%08x current process: 0x%x\n",
s->epsr, curproc);
+ db_printf("vector: 0x%02x interrupt mask: 0x%08x\n",
+ s->vector, s->mask);
/*
* If the vector indicates trap, instead of an exception or
@@ -292,54 +303,68 @@ m88k_db_print_frame(addr, have_addr, count, modif)
*/
if (!(s->vector <= 10 || (114 <= s->vector && s->vector <= 127))) {
- db_printf("\n\n");
+ db_printf("\n");
return;
}
- if (s->vector == /*data*/3 || s->dmt0 & 1) {
- db_printf("dmt,d,a0: 0x%08x 0x%08x 0x%08x ",
- s->dmt0, s->dmd0, s->dma0);
- db_find_xtrn_sym_and_offset((db_addr_t)s->dma0, &name, &offset);
- if (name != 0 && (unsigned)offset <= db_maxoff)
- db_printf("%s+0x%08x", name, (unsigned)offset);
- db_printf("\n ");
- surpress1 = m88k_dmx_print(s->dmt0|0x01, s->dmd0, s->dma0, 0);
- db_printf("\n");
-
- if ((s->dmt1 & 1) && (!surpress1)) {
- db_printf("dmt,d,a1: 0x%08x 0x%08x 0x%08x ",
- s->dmt1, s->dmd1, s->dma1);
- db_find_xtrn_sym_and_offset((db_addr_t)s->dma1,
- &name, &offset);
+ if (cputyp != CPU_88110) {
+ if (s->vector == /*data*/3 || s->dmt0 & 1) {
+ db_printf("dmt,d,a0: 0x%08x 0x%08x 0x%08x ",
+ s->dmt0, s->dmd0, s->dma0);
+ db_find_xtrn_sym_and_offset((db_addr_t)s->dma0, &name, &offset);
if (name != 0 && (unsigned)offset <= db_maxoff)
db_printf("%s+0x%08x", name, (unsigned)offset);
db_printf("\n ");
- surpress2 = m88k_dmx_print(s->dmt1, s->dmd1, s->dma1, 1);
+ surpress1 = m88k_dmx_print(s->dmt0|0x01, s->dmd0, s->dma0, 0);
db_printf("\n");
-
- if ((s->dmt2 & 1) && (!surpress2)) {
- db_printf("dmt,d,a2: 0x%08x 0x%08x 0x%08x ",
- s->dmt2, s->dmd2, s->dma2);
- db_find_xtrn_sym_and_offset((db_addr_t)s->dma2,
+
+ if ((s->dmt1 & 1) && (!surpress1)) {
+ db_printf("dmt,d,a1: 0x%08x 0x%08x 0x%08x ",
+ s->dmt1, s->dmd1, s->dma1);
+ db_find_xtrn_sym_and_offset((db_addr_t)s->dma1,
&name, &offset);
if (name != 0 && (unsigned)offset <= db_maxoff)
db_printf("%s+0x%08x", name, (unsigned)offset);
db_printf("\n ");
- m88k_dmx_print(s->dmt2, s->dmd2, s->dma2, 2);
+ surpress2 = m88k_dmx_print(s->dmt1, s->dmd1, s->dma1, 1);
db_printf("\n");
+
+ if ((s->dmt2 & 1) && (!surpress2)) {
+ db_printf("dmt,d,a2: 0x%08x 0x%08x 0x%08x ",
+ s->dmt2, s->dmd2, s->dma2);
+ db_find_xtrn_sym_and_offset((db_addr_t)s->dma2,
+ &name, &offset);
+ if (name != 0 && (unsigned)offset <= db_maxoff)
+ db_printf("%s+0x%08x", name, (unsigned)offset);
+ db_printf("\n ");
+ m88k_dmx_print(s->dmt2, s->dmd2, s->dma2, 2);
+ db_printf("\n");
+ }
}
}
}
-
+
if (s->fpecr & 255) { /* floating point error occurred */
db_printf("fpecr: 0x%08x fpsr: 0x%08x fpcr: 0x%08x\n",
s->fpecr, s->fpsr, s->fpcr);
- db_printf("fcr1-4: 0x%08x 0x%08x 0x%08x 0x%08x\n",
- s->fphs1, s->fpls1, s->fphs2, s->fpls2);
- db_printf("fcr5-8: 0x%08x 0x%08x 0x%08x 0x%08x\n",
- s->fppt, s->fprh, s->fprl, s->fpit);
+ if (cputyp != CPU_88110) {
+ db_printf("fcr1-4: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ s->fphs1, s->fpls1, s->fphs2, s->fpls2);
+ db_printf("fcr5-8: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ s->fppt, s->fprh, s->fprl, s->fpit);
+ }
}
- db_printf("\n\n");
+ db_printf("\n");
+}
+
+void
+m88k_db_registers(addr, have_addr, count, modif)
+ db_expr_t addr;
+ int have_addr;
+ int count;
+ char *modif;
+{
+ m88k_db_print_frame((db_expr_t)DDB_REGS, TRUE, 0, modif);
}
/************************/
@@ -461,10 +486,13 @@ ddb_break_trap(type, eframe)
if (type == T_KDB_BREAK) {
/*
* back up an instruction and retry the instruction
- * at the breakpoint address
+ * at the breakpoint address. mc88110's exip reg
+ * already has the adress of the exception instruction.
*/
- eframe->sfip = eframe->snip;
- eframe->snip = eframe->sxip;
+ if (cputyp != CPU_88110) {
+ eframe->sfip = eframe->snip;
+ eframe->snip = eframe->sxip;
+ }
}
return 0;
@@ -578,7 +606,10 @@ m88k_db_where(addr, have_addr, count, modif)
s = DDB_REGS;
- l = m88k_pc(s); /* clear low bits */
+ if (cputyp == CPU_88110)
+ l = s->exip & ~3;
+ else
+ l = m88k_pc(s); /* clear low bits */
db_find_xtrn_sym_and_offset((db_addr_t) l,&name, (db_expr_t*)&offset);
if (name && (unsigned)offset <= db_maxoff)
@@ -815,6 +846,7 @@ struct db_command db_machine_cmds[] =
{
{"cache", 0, 0, m88k_cache_cmds},
{"frame", m88k_db_print_frame, 0, 0},
+ {"regs", m88k_db_registers, 0, 0},
{"noise", m88k_db_noise, 0, 0},
{"searchframe", m88k_db_frame_search, 0, 0},
{"translate", m88k_db_translate, 0, 0},
diff --git a/sys/arch/mvme88k/ddb/db_sstep.c b/sys/arch/mvme88k/ddb/db_sstep.c
index 7e52840808c..518934ee862 100644
--- a/sys/arch/mvme88k/ddb/db_sstep.c
+++ b/sys/arch/mvme88k/ddb/db_sstep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: db_sstep.c,v 1.7 2001/03/16 00:01:51 miod Exp $ */
+/* $OpenBSD: db_sstep.c,v 1.8 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -30,6 +30,7 @@
#include <sys/systm.h>
#include <machine/db_machdep.h>
#include <ddb/db_access.h> /* db_get_value() */
+#include <ddb/db_break.h> /* db_breakpoint_t */
/*
* Support routines for software single step.
@@ -38,8 +39,12 @@
*
*/
-boolean_t inst_delayed __P((unsigned ins));
-db_expr_t getreg_val __P((unsigned regno, db_regs_t *frame));
+boolean_t inst_delayed __P((unsigned int ins));
+
+#ifdef INTERNAL_SSTEP
+db_breakpoint_t db_not_taken_bkpt = 0;
+db_breakpoint_t db_taken_bkpt = 0;
+#endif
/*
* Returns TRUE is the instruction a branch or jump instruction
@@ -47,7 +52,7 @@ db_expr_t getreg_val __P((unsigned regno, db_regs_t *frame));
*/
boolean_t
inst_branch(ins)
- unsigned ins;
+ unsigned int ins;
{
/* check high five bits */
switch (ins >> (32 - 5)) {
@@ -72,7 +77,7 @@ inst_branch(ins)
*/
unsigned
inst_load(ins)
- unsigned ins;
+ unsigned int ins;
{
/* look at the top six bits, for starters */
switch (ins >> (32 - 6)) {
@@ -116,7 +121,7 @@ inst_load(ins)
*/
unsigned
inst_store(ins)
- unsigned ins;
+ unsigned int ins;
{
/* decode top 6 bits again */
switch (ins >> (32 - 6)) {
@@ -156,7 +161,7 @@ inst_store(ins)
*/
boolean_t
inst_delayed(ins)
- unsigned ins;
+ unsigned int ins;
{
/* check the br, bsr, bb0, bb1, bcnd cases */
switch ((ins & 0xfc000000U) >> (32 - 6)) {
@@ -248,8 +253,10 @@ branch_taken(inst, pc, func, func_data)
/* check jmp/jsr case */
/* check bits 5-31, skipping 10 & 11 */
- if ((inst & 0xfffff3e0U) == 0xf400c000U)
- return (*func)(func_data, inst & 0x1f); /* the register value */
+ if ((inst & 0xfffff3e0U) == 0xf400c000U){
+ return (*func)(func_data, (inst & 0x0000001fU)); /* the register value */
+ }
+
panic("branch_taken");
return 0; /* keeps compiler happy */
@@ -260,17 +267,71 @@ branch_taken(inst, pc, func, func_data)
* Returns the value of the register in the specified
* frame. Only makes sense for general registers.
*/
-db_expr_t
-getreg_val(regno, frame)
- unsigned regno;
+
+register_t
+getreg_val(frame, regno)
db_regs_t *frame;
+ int regno;
{
if (regno == 0)
return 0;
else if (regno < 31)
return frame->r[regno];
else {
- panic("bad register number to getreg_val.");
+ panic("bad register number (%d) to getreg_val.", regno);
return 0;/*to make compiler happy */
}
}
+
+#ifdef INTERNAL_SSTEP
+void
+db_set_single_step(regs)
+ register db_regs_t *regs;
+{
+ if (cputyp == CPU_88110){
+ ((regs)->epsr |= (PSR_TRACE | PSR_SER));
+ } else {
+ db_addr_t pc = PC_REGS(regs);
+#ifndef SOFTWARE_SSTEP_EMUL
+ db_addr_t brpc;
+ u_int inst;
+
+ /*
+ * User was stopped at pc, e.g. the instruction
+ * at pc was not executed.
+ */
+ inst = db_get_value(pc, sizeof(int), FALSE);
+ if (inst_branch(inst) || inst_call(inst) || inst_return(inst)) {
+ brpc = branch_taken(inst, pc, getreg_val, regs);
+ if (brpc != pc) { /* self-branches are hopeless */
+ db_taken_bkpt = db_set_temp_breakpoint(brpc);
+ }
+#if 0
+ /* XXX this seems like a true bug, no? */
+ pc = next_instr_address(pc, 1);
+#endif
+ }
+#endif /*SOFTWARE_SSTEP_EMUL*/
+ pc = next_instr_address(pc, 0);
+ db_not_taken_bkpt = db_set_temp_breakpoint(pc);
+ }
+}
+
+void
+db_clear_single_step(regs)
+ db_regs_t *regs;
+{
+ if (cputyp == CPU_88110){
+ ((regs)->epsr &= ~(PSR_TRACE | PSR_SER));
+ } else {
+ if (db_taken_bkpt != 0) {
+ db_delete_temp_breakpoint(db_taken_bkpt);
+ db_taken_bkpt = 0;
+ }
+ if (db_not_taken_bkpt != 0) {
+ db_delete_temp_breakpoint(db_not_taken_bkpt);
+ db_not_taken_bkpt = 0;
+ }
+ }
+}
+#endif
diff --git a/sys/arch/mvme88k/ddb/db_trace.c b/sys/arch/mvme88k/ddb/db_trace.c
index 8f708a2a8d8..ebba9135f91 100644
--- a/sys/arch/mvme88k/ddb/db_trace.c
+++ b/sys/arch/mvme88k/ddb/db_trace.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: db_trace.c,v 1.9 2001/11/27 05:36:10 miod Exp $ */
+/* $OpenBSD: db_trace.c,v 1.10 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -38,52 +38,52 @@
#include <ddb/db_command.h> /* db_recover */
union instruction {
- unsigned rawbits;
-
- struct {
- unsigned int : 5;
- unsigned int n: 1;
- signed int d26:26;
- } br;
-
- struct {
- unsigned int : 4;
- unsigned int isbb1: 1; /* isbb1==0 means bb0, isbb1==1 means bb1 */
- unsigned int n : 1;
- unsigned int b5 : 5;
- unsigned int s1 : 5;
- signed int d16 :16;
- } bb; /* bcnd too, except "isbb1" makes no sense for bcnd */
-
- struct {
- unsigned int : 6;
- unsigned int b5 : 5;
- unsigned int s1 : 5;
- unsigned int : 7;
- unsigned int vec9 : 9;
- } tb; /* tcnd too */
-
- struct {
- unsigned int :21;
- unsigned int n : 1;
- unsigned int : 5;
- unsigned int s2 : 5;
- } jump; /* jmp, jsr */
-
- struct {
- unsigned int : 6;
- unsigned int d : 5;
- unsigned int s1 : 5;
- unsigned int i16 :16;
- } diatic; /* general reg/reg/i16 instructions */
-
- struct {
- unsigned int : 6;
- unsigned int d : 5;
- unsigned int s1 : 5;
- unsigned int :11;
- unsigned int s2 : 5;
- } triatic; /* general reg/reg/reg instructions */
+ unsigned rawbits;
+
+ struct {
+ unsigned int : 5;
+ unsigned int n: 1;
+ signed int d26:26;
+ } br;
+
+ struct {
+ unsigned int : 4;
+ unsigned int isbb1: 1; /* isbb1==0 means bb0, isbb1==1 means bb1 */
+ unsigned int n : 1;
+ unsigned int b5 : 5;
+ unsigned int s1 : 5;
+ signed int d16 :16;
+ } bb; /* bcnd too, except "isbb1" makes no sense for bcnd */
+
+ struct {
+ unsigned int : 6;
+ unsigned int b5 : 5;
+ unsigned int s1 : 5;
+ unsigned int : 7;
+ unsigned int vec9 : 9;
+ } tb; /* tcnd too */
+
+ struct {
+ unsigned int :21;
+ unsigned int n : 1;
+ unsigned int : 5;
+ unsigned int s2 : 5;
+ } jump; /* jmp, jsr */
+
+ struct {
+ unsigned int : 6;
+ unsigned int d : 5;
+ unsigned int s1 : 5;
+ unsigned int i16 :16;
+ } diatic; /* general reg/reg/i16 instructions */
+
+ struct {
+ unsigned int : 6;
+ unsigned int d : 5;
+ unsigned int s1 : 5;
+ unsigned int :11;
+ unsigned int s2 : 5;
+ } triatic; /* general reg/reg/reg instructions */
};
@@ -100,7 +100,7 @@ int frame_is_sane __P((db_regs_t *regs));
char *m88k_exception_name __P((unsigned vector));
unsigned db_trace_get_val __P((vm_offset_t addr, unsigned *ptr));
void db_stack_trace_cmd __P((db_regs_t *addr, int have_addr,
- db_expr_t count, char *modif));
+ db_expr_t count, char *modif));
/*
* Some macros to tell if the given text is the instruction.
@@ -146,41 +146,40 @@ extern int quiet_db_read_bytes;
/* lifted from mips */
static int
-db_setf_regs(
- struct db_variable *vp,
- db_expr_t *valuep,
- int op) /* read/write */
+db_setf_regs(struct db_variable *vp,
+ db_expr_t *valuep,
+ int op) /* read/write */
{
- register int *regp = (int *) ((char *) DDB_REGS + (int) (vp->valuep));
+ register int *regp = (int *) ((char *) DDB_REGS + (int) (vp->valuep));
- if (op == DB_VAR_GET)
- *valuep = *regp;
- else if (op == DB_VAR_SET)
- *regp = *valuep;
+ if (op == DB_VAR_GET)
+ *valuep = *regp;
+ else if (op == DB_VAR_SET)
+ *regp = *valuep;
- return (0); /* silence warning */
+ return (0); /* silence warning */
}
#define N(s, x) {s, (long *)&(((db_regs_t *) 0)->x), db_setf_regs}
struct db_variable db_regs[] = {
- N("r1", r[1]), N("r2", r[2]), N("r3", r[3]), N("r4", r[4]),
- N("r5", r[5]), N("r6", r[6]), N("r7", r[7]), N("r8", r[8]),
- N("r9", r[9]), N("r10", r[10]), N("r11", r[11]), N("r12", r[12]),
- N("r13", r[13]), N("r14", r[14]), N("r15", r[15]), N("r16", r[16]),
- N("r17", r[17]), N("r18", r[18]), N("r19", r[19]), N("r20", r[20]),
- N("r21", r[21]), N("r22", r[22]), N("r23", r[23]), N("r24", r[24]),
- N("r25", r[25]), N("r26", r[26]), N("r27", r[27]), N("r28", r[28]),
- N("r29", r[29]), N("r30", r[30]), N("r31", r[31]), N("epsr", epsr),
- N("sxip", sxip), N("snip", snip), N("sfip", sfip), N("ssbr", ssbr),
- N("dmt0", dmt0), N("dmd0", dmd0), N("dma0", dma0), N("dmt1", dmt1),
- N("dmd1", dmd1), N("dma1", dma1), N("dmt2", dmt2), N("dmd2", dmd2),
- N("dma2", dma2), N("fpecr", fpecr),N("fphs1", fphs1),N("fpls1", fpls1),
- N("fphs2", fphs2), N("fpls2", fpls2),N("fppt", fppt), N("fprh", fprh),
- N("fprl", fprl), N("fpit", fpit), N("fpsr", fpsr), N("fpcr", fpcr),
- N("mask", mask), /* interrupt mask */
- N("mode", mode), /* interrupt mode */
- N("exvc", vector), /* exception vector */
+ N("r1", r[1]), N("r2", r[2]), N("r3", r[3]), N("r4", r[4]),
+ N("r5", r[5]), N("r6", r[6]), N("r7", r[7]), N("r8", r[8]),
+ N("r9", r[9]), N("r10", r[10]), N("r11", r[11]), N("r12", r[12]),
+ N("r13", r[13]), N("r14", r[14]), N("r15", r[15]), N("r16", r[16]),
+ N("r17", r[17]), N("r18", r[18]), N("r19", r[19]), N("r20", r[20]),
+ N("r21", r[21]), N("r22", r[22]), N("r23", r[23]), N("r24", r[24]),
+ N("r25", r[25]), N("r26", r[26]), N("r27", r[27]), N("r28", r[28]),
+ N("r29", r[29]), N("r30", r[30]), N("r31", r[31]), N("epsr", epsr),
+ N("sxip", sxip), N("snip", snip), N("sfip", sfip), N("ssbr", ssbr),
+ N("dmt0", dmt0), N("dmd0", dmd0), N("dma0", dma0), N("dmt1", dmt1),
+ N("dmd1", dmd1), N("dma1", dma1), N("dmt2", dmt2), N("dmd2", dmd2),
+ N("dma2", dma2), N("fpecr", fpecr),N("fphs1", fphs1),N("fpls1", fpls1),
+ N("fphs2", fphs2), N("fpls2", fpls2),N("fppt", fppt), N("fprh", fprh),
+ N("fprl", fprl), N("fpit", fpit), N("fpsr", fpsr), N("fpcr", fpcr),
+ N("mask", mask), /* interrupt mask */
+ N("mode", mode), /* interrupt mode */
+ N("exvc", vector), /* exception vector */
};
#undef N
@@ -203,76 +202,76 @@ struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
static unsigned
m88k_instruction_info(unsigned instruction)
{
- static struct { unsigned mask, value, flags; } *ptr, control[] =
- {
- /* runs in the same order as 2nd Ed 88100 manual Table 3-14 */
- { 0xf0000000U, 0x00000000U, /* xmem */ TRASHES | STORE | LOAD },
- { 0xec000000U, 0x00000000U, /* ld.d */ TRASHES | LOAD | DOUBLE },
- { 0xe0000000U, 0x00000000U, /* load */ TRASHES | LOAD },
- { 0xfc000000U, 0x20000000U, /* st.d */ STORE | DOUBLE },
- { 0xf0000000U, 0x20000000U, /* store */ STORE },
- { 0xc0000000U, 0x40000000U, /* arith */ TRASHES },
- { 0xfc004000U, 0x80004000U, /* ld cr */ TRASHES },
- { 0xfc004000U, 0x80000000U, /* st cr */ 0 },
- { 0xfc008060U, 0x84000000U, /* f */ TRASHES },
- { 0xfc008060U, 0x84000020U, /* f.d */ TRASHES | DOUBLE },
- { 0xfc000000U, 0xcc000000U, /* bsr.n */ FLOW_CTRL | DELAYED | BSR },
- { 0xfc000000U, 0xc8000000U, /* bsr */ FLOW_CTRL | BSR },
- { 0xe4000000U, 0xc4000000U, /* br/bb.n */ FLOW_CTRL | DELAYED },
- { 0xe4000000U, 0xc0000000U, /* br/bb */ FLOW_CTRL },
- { 0xfc000000U, 0xec000000U, /* bcnd.n */ FLOW_CTRL | DELAYED },
- { 0xfc000000U, 0xe8000000U, /* bcnd */ FLOW_CTRL },
- { 0xfc00c000U, 0xf0008000U, /* bits */ TRASHES },
- { 0xfc00c000U, 0xf000c000U, /* trap */ 0 },
- { 0xfc00f0e0U, 0xf4002000U, /* st */ 0 },
- { 0xfc00cce0U, 0xf4000000U, /* ld.d */ TRASHES | DOUBLE },
- { 0xfc00c0e0U, 0xf4000000U, /* ld */ TRASHES },
- { 0xfc00c0e0U, 0xf4004000U, /* arith */ TRASHES },
- { 0xfc00c3e0U, 0xf4008000U, /* bits */ TRASHES },
- { 0xfc00ffe0U, 0xf400cc00U, /* jsr.n */ FLOW_CTRL | DELAYED | JSR },
- { 0xfc00ffe0U, 0xf400c800U, /* jsr */ FLOW_CTRL | JSR },
- { 0xfc00ffe0U, 0xf400c400U, /* jmp.n */ FLOW_CTRL | DELAYED },
- { 0xfc00ffe0U, 0xf400c000U, /* jmp */ FLOW_CTRL },
- { 0xfc00fbe0U, 0xf400e800U, /* ff */ TRASHES },
- { 0xfc00ffe0U, 0xf400f800U, /* tbnd */ 0 },
- { 0xfc00ffe0U, 0xf400fc00U, /* rte */ FLOW_CTRL },
- { 0xfc000000U, 0xf8000000U, /* tbnd */ 0 },
- };
+ static struct {
+ unsigned mask, value, flags;
+ } *ptr, control[] = {
+ /* runs in the same order as 2nd Ed 88100 manual Table 3-14 */
+ { 0xf0000000U, 0x00000000U, /* xmem */ TRASHES | STORE | LOAD},
+ { 0xec000000U, 0x00000000U, /* ld.d */ TRASHES | LOAD | DOUBLE},
+ { 0xe0000000U, 0x00000000U, /* load */ TRASHES | LOAD},
+ { 0xfc000000U, 0x20000000U, /* st.d */ STORE | DOUBLE},
+ { 0xf0000000U, 0x20000000U, /* store */ STORE},
+ { 0xc0000000U, 0x40000000U, /* arith */ TRASHES},
+ { 0xfc004000U, 0x80004000U, /* ld cr */ TRASHES},
+ { 0xfc004000U, 0x80000000U, /* st cr */ 0},
+ { 0xfc008060U, 0x84000000U, /* f */ TRASHES},
+ { 0xfc008060U, 0x84000020U, /* f.d */ TRASHES | DOUBLE},
+ { 0xfc000000U, 0xcc000000U, /* bsr.n */ FLOW_CTRL | DELAYED | BSR},
+ { 0xfc000000U, 0xc8000000U, /* bsr */ FLOW_CTRL | BSR},
+ { 0xe4000000U, 0xc4000000U, /* br/bb.n */ FLOW_CTRL | DELAYED},
+ { 0xe4000000U, 0xc0000000U, /* br/bb */ FLOW_CTRL},
+ { 0xfc000000U, 0xec000000U, /* bcnd.n */ FLOW_CTRL | DELAYED},
+ { 0xfc000000U, 0xe8000000U, /* bcnd */ FLOW_CTRL},
+ { 0xfc00c000U, 0xf0008000U, /* bits */ TRASHES},
+ { 0xfc00c000U, 0xf000c000U, /* trap */ 0},
+ { 0xfc00f0e0U, 0xf4002000U, /* st */ 0},
+ { 0xfc00cce0U, 0xf4000000U, /* ld.d */ TRASHES | DOUBLE},
+ { 0xfc00c0e0U, 0xf4000000U, /* ld */ TRASHES},
+ { 0xfc00c0e0U, 0xf4004000U, /* arith */ TRASHES},
+ { 0xfc00c3e0U, 0xf4008000U, /* bits */ TRASHES},
+ { 0xfc00ffe0U, 0xf400cc00U, /* jsr.n */ FLOW_CTRL | DELAYED | JSR},
+ { 0xfc00ffe0U, 0xf400c800U, /* jsr */ FLOW_CTRL | JSR},
+ { 0xfc00ffe0U, 0xf400c400U, /* jmp.n */ FLOW_CTRL | DELAYED},
+ { 0xfc00ffe0U, 0xf400c000U, /* jmp */ FLOW_CTRL},
+ { 0xfc00fbe0U, 0xf400e800U, /* ff */ TRASHES},
+ { 0xfc00ffe0U, 0xf400f800U, /* tbnd */ 0},
+ { 0xfc00ffe0U, 0xf400fc00U, /* rte */ FLOW_CTRL},
+ { 0xfc000000U, 0xf8000000U, /* tbnd */ 0},
+ };
#define ctrl_count (sizeof(control)/sizeof(control[0]))
- for (ptr = &control[0]; ptr < &control[ctrl_count]; ptr++)
- if ((instruction & ptr->mask) == ptr->value)
- return ptr->flags;
- SHOW_INSTRUCTION(0, instruction, "bad m88k_instruction_info");
- return 0;
+ for (ptr = &control[0]; ptr < &control[ctrl_count]; ptr++)
+ if ((instruction & ptr->mask) == ptr->value)
+ return ptr->flags;
+ SHOW_INSTRUCTION(0, instruction, "bad m88k_instruction_info");
+ return 0;
}
static int
hex_value_needs_0x(unsigned value)
{
- int i;
- unsigned last = 0;
- unsigned char c;
- unsigned have_a_hex_digit = 0;
+ int i;
+ unsigned last = 0;
+ unsigned char c;
+ unsigned have_a_hex_digit = 0;
- if (value <= 9)
- return 0;
+ if (value <= 9)
+ return 0;
- for (i = 0; i < 8; i++) {
- c = value & 0xf;
- value >>= 4;
- if (c)
- last = c;
- if (c > 9)
- have_a_hex_digit = 1;
- }
- if (have_a_hex_digit == 0)
- return 1;
- if (last > 9)
- return 1;
- return 0;
+ for (i = 0; i < 8; i++) {
+ c = value & 0xf;
+ value >>= 4;
+ if (c)
+ last = c;
+ if (c > 9)
+ have_a_hex_digit = 1;
+ }
+ if (have_a_hex_digit == 0)
+ return 1;
+ if (last > 9)
+ return 1;
+ return 0;
}
-
/*
* returns
* 1 if regs seems to be a reasonable kernel exception frame.
@@ -283,55 +282,62 @@ hex_value_needs_0x(unsigned value)
int
frame_is_sane(db_regs_t *regs)
{
- /* no good if we can't read the whole frame */
- if (badwordaddr((vm_offset_t)regs) || badwordaddr((vm_offset_t)&regs->mode))
- return 0;
+ /* no good if we can't read the whole frame */
+ if (badwordaddr((vm_offset_t)regs) || badwordaddr((vm_offset_t)&regs->mode)){
+ db_printf("[WARNING: frame at 0x%x : unreadable]\n", regs);
+ return 0;
+ }
#ifndef DIAGNOSTIC
- /* disabled for now -- see fpu_enable in mvme88k/eh.s */
- /* r0 must be 0 (obviously) */
- if (regs->r[0] != 0)
- return 0;
+ /* disabled for now -- see fpu_enable in luna88k/eh.s */
+ /* r0 must be 0 (obviously) */
+ if (regs->r[0] != 0){
+ db_printf("[WARNING: frame at 0x%x : r[0] != 0]\n", regs);
+ return 0;
+ }
#endif
- /* stack sanity ... r31 must be nonzero, but must be word aligned */
- if (regs->r[31] == 0 || (regs->r[31] & 3) != 0)
- return 0;
+ /* stack sanity ... r31 must be nonzero, but must be word aligned */
+ if (regs->r[31] == 0 || (regs->r[31] & 3) != 0) {
+ db_printf("[WARNING: frame at 0x%x : r[31] == 0 or not word aligned]\n", regs);
+ return 0;
+ }
- /* sxip is reasonable */
+ if (cputyp != CPU_88110) {
+ /* sxip is reasonable */
#if 0
- if ((regs->sxip & 1) == 1)
- return 0;
+ if ((regs->sxip & 1) == 1)
+ return 0;
#endif
- /* snip is reasonable */
- if ((regs->snip & 3) != 2)
- return 0;
- /* sfip is reasonable */
- if ((regs->sfip & 3) != 2)
- return 0;
+ /* snip is reasonable */
+ if ((regs->snip & 3) != 2)
+ return 0;
+ /* sfip is reasonable */
+ if ((regs->sfip & 3) != 2)
+ return 0;
+ }
- /* epsr sanity */
- if ((regs->epsr & 0x8FFFFFF5U) == 0x800003f0U) /* kernel mode */
- {
- if (regs->epsr & 0x40000000)
- db_printf("[WARNING: byte order in kernel frame at %x "
- "is little-endian!]\n", regs);
- return 1;
- }
- if ((regs->epsr & 0x8FFFFFFFU) == 0x000003f0U) /* user mode */
- {
- if (regs->epsr & 0x40000000)
- db_printf("[WARNING: byte order in user frame at %x "
- "is little-endian!]\n", regs);
- return 2;
- }
- return 0;
+ /* epsr sanity */
+ if ((regs->epsr & PSR_MODE)) { /* kernel mode */
+ if (regs->epsr & PSR_BO)
+ db_printf("[WARNING: byte order in kernel frame at %x "
+ "is little-endian!]\n", regs);
+ return 1;
+ }
+ if (!(regs->epsr & PSR_MODE)) { /* user mode */
+ if (regs->epsr & PSR_BO)
+ db_printf("[WARNING: byte order in user frame at %x "
+ "is little-endian!]\n", regs);
+ return 2;
+ }
+ db_printf("[WARNING: not an exception frame?]\n");
+ return 0;
}
char *
m88k_exception_name(unsigned vector)
{
- switch (vector) {
+ switch (vector) {
default:
case 0: return "Reset";
case 1: return "Interrupt";
@@ -344,6 +350,7 @@ m88k_exception_name(unsigned vector)
case 8: return "Integer Divide Exception";
case 9: return "Integer Overflow Exception";
case 10: return "Error Exception";
+ case 11: return "Non Maskable Interrupt";
case 114: return "FPU precise";
case 115: return "FPU imprecise";
case DDB_ENTRY_BKPT_NO:
@@ -353,7 +360,7 @@ m88k_exception_name(unsigned vector)
case DDB_ENTRY_TRAP_NO:
return "ddb trap";
case 451: return "Syscall";
- }
+ }
}
/*
@@ -363,30 +370,30 @@ m88k_exception_name(unsigned vector)
unsigned
db_trace_get_val(vm_offset_t addr, unsigned *ptr)
{
- label_t db_jmpbuf;
- label_t *prev = db_recover;
- boolean_t old_quiet_db_read_bytes = quiet_db_read_bytes;
+ label_t db_jmpbuf;
+ label_t *prev = db_recover;
+ boolean_t old_quiet_db_read_bytes = quiet_db_read_bytes;
- quiet_db_read_bytes = 1;
+ quiet_db_read_bytes = 1;
- if (setjmp((db_recover = &db_jmpbuf)) != 0) {
- db_recover = prev;
- quiet_db_read_bytes = old_quiet_db_read_bytes;
- return 0;
- } else {
- db_read_bytes(addr, 4, (char*)ptr);
- db_recover = prev;
- quiet_db_read_bytes = old_quiet_db_read_bytes;
- return 1;
- }
+ if (setjmp((db_recover = &db_jmpbuf)) != 0) {
+ db_recover = prev;
+ quiet_db_read_bytes = old_quiet_db_read_bytes;
+ return 0;
+ } else {
+ db_read_bytes(addr, 4, (char*)ptr);
+ db_recover = prev;
+ quiet_db_read_bytes = old_quiet_db_read_bytes;
+ return 1;
+ }
}
-#define FIRST_CALLPRESERVED_REG 14
-#define LAST_CALLPRESERVED_REG 29
-#define FIRST_ARG_REG 2
-#define LAST_ARG_REG 9
-#define RETURN_VAL_REG 1
+#define FIRST_CALLPRESERVED_REG 14
+#define LAST_CALLPRESERVED_REG 29
+#define FIRST_ARG_REG 2
+#define LAST_ARG_REG 9
+#define RETURN_VAL_REG 1
static unsigned global_saved_list = 0x0; /* one bit per register */
static unsigned local_saved_list = 0x0; /* one bit per register */
@@ -401,15 +408,15 @@ save_reg(int reg, unsigned value)
#ifdef TRACE_DEBUG
if (DEBUGGING_ON) db_printf("save_reg(%d, %x)\n", reg, value);
#endif
- if (trashed_list & reg_bit(reg)) {
+ if (trashed_list & reg_bit(reg)) {
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("<trashed>\n");
+ if (DEBUGGING_ON) db_printf("<trashed>\n");
#endif
- return; /* don't save trashed registers */
- }
- saved_reg[(reg%32)] = value;
- global_saved_list |= reg_bit(reg);
- local_saved_list |= reg_bit(reg);
+ return; /* don't save trashed registers */
+ }
+ saved_reg[(reg%32)] = value;
+ global_saved_list |= reg_bit(reg);
+ local_saved_list |= reg_bit(reg);
}
#define mark_reg_trashed(reg) (trashed_list |= reg_bit(reg))
@@ -428,32 +435,31 @@ save_reg(int reg, unsigned value)
static void
print_args(void)
{
- int reg, last_arg;
-
- /* find the highest argument register saved */
- for (last_arg = LAST_ARG_REG; last_arg >= FIRST_ARG_REG; last_arg--)
- if (have_local_reg(last_arg))
- break;
- if (last_arg < FIRST_ARG_REG)
- return; /* none were saved */
-
- db_printf("(");
-
- /* print each one, up to the highest */
- for (reg = FIRST_ARG_REG; /*nothing */; reg++)
- {
- if (!have_local_reg(reg))
- db_printf("?");
- else {
- unsigned value = saved_reg_value(reg);
- db_printf("%s%x", hex_value_needs_0x(value) ? "0x" : "", value);
+ int reg, last_arg;
+
+ /* find the highest argument register saved */
+ for (last_arg = LAST_ARG_REG; last_arg >= FIRST_ARG_REG; last_arg--)
+ if (have_local_reg(last_arg))
+ break;
+ if (last_arg < FIRST_ARG_REG)
+ return; /* none were saved */
+
+ db_printf("(");
+
+ /* print each one, up to the highest */
+ for (reg = FIRST_ARG_REG; /*nothing */; reg++) {
+ if (!have_local_reg(reg))
+ db_printf("?");
+ else {
+ unsigned value = saved_reg_value(reg);
+ db_printf("%s%x", hex_value_needs_0x(value) ? "0x" : "", value);
+ }
+ if (reg == last_arg)
+ break;
+ else
+ db_printf(", ");
}
- if (reg == last_arg)
- break;
- else
- db_printf(", ");
- }
- db_printf(")");
+ db_printf(")");
}
@@ -485,45 +491,45 @@ print_args(void)
static int
is_jump_source_ok(unsigned return_to, unsigned jump_to)
{
- unsigned flags;
- union instruction instruction;
-
- /*
- * Delayed branches are most common... look two instructions before
- * where we were going to return to to see if it's a delayed branch.
- */
- if (!db_trace_get_val(return_to - 8, &instruction.rawbits))
- return JUMP_SOURCE_IS_BAD;
- flags = m88k_instruction_info(instruction.rawbits);
-
- if ((flags & FLOW_CTRL) && (flags & DELAYED) && (flags & (JSR|BSR))) {
- if (flags & JSR)
- return JUMP_SOURCE_IS_OK; /* have to assume it's correct */
- /* calculate the offset */
- if (br_dest(return_to - 8, instruction) == jump_to)
- return JUMP_SOURCE_IS_OK; /* exactamundo! */
- else
- return JUMP_SOURCE_IS_UNLIKELY; /* seems wrong */
- }
-
- /*
- * Try again, looking for a non-delayed jump one back.
- */
- if (!db_trace_get_val(return_to - 4, &instruction.rawbits))
- return JUMP_SOURCE_IS_BAD;
- flags = m88k_instruction_info(instruction.rawbits);
-
- if ((flags & FLOW_CTRL) && !(flags & DELAYED) && (flags & (JSR|BSR))) {
- if (flags & JSR)
- return JUMP_SOURCE_IS_OK; /* have to assume it's correct */
- /* calculate the offset */
- if (br_dest(return_to - 4, instruction) == jump_to)
- return JUMP_SOURCE_IS_OK; /* exactamundo! */
- else
- return JUMP_SOURCE_IS_UNLIKELY; /* seems wrong */
- }
-
- return JUMP_SOURCE_IS_UNLIKELY;
+ unsigned flags;
+ union instruction instruction;
+
+ /*
+ * Delayed branches are most common... look two instructions before
+ * where we were going to return to to see if it's a delayed branch.
+ */
+ if (!db_trace_get_val(return_to - 8, &instruction.rawbits))
+ return JUMP_SOURCE_IS_BAD;
+ flags = m88k_instruction_info(instruction.rawbits);
+
+ if ((flags & FLOW_CTRL) && (flags & DELAYED) && (flags & (JSR|BSR))) {
+ if (flags & JSR)
+ return JUMP_SOURCE_IS_OK; /* have to assume it's correct */
+ /* calculate the offset */
+ if (br_dest(return_to - 8, instruction) == jump_to)
+ return JUMP_SOURCE_IS_OK; /* exactamundo! */
+ else
+ return JUMP_SOURCE_IS_UNLIKELY; /* seems wrong */
+ }
+
+ /*
+ * Try again, looking for a non-delayed jump one back.
+ */
+ if (!db_trace_get_val(return_to - 4, &instruction.rawbits))
+ return JUMP_SOURCE_IS_BAD;
+ flags = m88k_instruction_info(instruction.rawbits);
+
+ if ((flags & FLOW_CTRL) && !(flags & DELAYED) && (flags & (JSR|BSR))) {
+ if (flags & JSR)
+ return JUMP_SOURCE_IS_OK; /* have to assume it's correct */
+ /* calculate the offset */
+ if (br_dest(return_to - 4, instruction) == jump_to)
+ return JUMP_SOURCE_IS_OK; /* exactamundo! */
+ else
+ return JUMP_SOURCE_IS_UNLIKELY; /* seems wrong */
+ }
+
+ return JUMP_SOURCE_IS_UNLIKELY;
}
static char *note = 0;
@@ -554,455 +560,440 @@ static int next_address_likely_wrong = 0;
static int
stack_decode(unsigned addr, unsigned *stack)
{
- db_sym_t proc;
- unsigned offset_from_proc;
- unsigned instructions_to_search;
- unsigned check_addr;
- unsigned function_addr; /* start of function */
- unsigned r31 = *stack; /* the r31 of the function */
- unsigned inst; /* text of an instruction */
- unsigned ret_addr; /* address to which we return */
- unsigned tried_to_save_r1 = 0;
+ db_sym_t proc;
+ unsigned offset_from_proc;
+ unsigned instructions_to_search;
+ unsigned check_addr;
+ unsigned function_addr; /* start of function */
+ unsigned r31 = *stack; /* the r31 of the function */
+ unsigned inst; /* text of an instruction */
+ unsigned ret_addr; /* address to which we return */
+ unsigned tried_to_save_r1 = 0;
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON)
- db_printf("\n>>>stack_decode(addr=%x, stack=%x)\n",
- addr, *stack);
+ if (DEBUGGING_ON)
+ db_printf("\n>>>stack_decode(addr=%x, stack=%x)\n",
+ addr, *stack);
#endif
- /* get what we hope will be the db_sym_t for the function name */
- proc = db_search_symbol(addr, DB_STGY_PROC, &offset_from_proc);
- if (offset_from_proc == addr) /* i.e. no symbol found */
- proc = DB_SYM_NULL;
-
- /*
- * Somehow, find the start of this function.
- * If we found a symbol above, it'll have the address.
- * Otherwise, we've got to search for it....
- */
- if (proc != DB_SYM_NULL)
- {
- char *names;
- db_symbol_values(proc, &names, &function_addr);
- if (names == 0)
- return 0;
- #ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("name %s address 0x%x\n",
- names, function_addr);
- #endif
- }
- else
- {
- int instructions_to_check = 400;
+ /* get what we hope will be the db_sym_t for the function name */
+ proc = db_search_symbol(addr, DB_STGY_PROC, &offset_from_proc);
+ if (offset_from_proc == addr) /* i.e. no symbol found */
+ proc = DB_SYM_NULL;
+
/*
- * hmm - unable to find symbol. Search back
- * looking for a function prolog.
+ * Somehow, find the start of this function.
+ * If we found a symbol above, it'll have the address.
+ * Otherwise, we've got to search for it....
*/
- for (check_addr = addr; instructions_to_check-- > 0; check_addr -= 4)
- {
- if (!db_trace_get_val(check_addr, &inst))
- break;
-
- if (SUBU_R31_R31_IMM(inst))
- {
+ if (proc != DB_SYM_NULL) {
+ char *names;
+ db_symbol_values(proc, &names, &function_addr);
+ if (names == 0)
+ return 0;
+ #ifdef TRACE_DEBUG
+ if (DEBUGGING_ON) db_printf("name %s address 0x%x\n",
+ names, function_addr);
+ #endif
+ } else {
+ int instructions_to_check = 400;
+ /*
+ * hmm - unable to find symbol. Search back
+ * looking for a function prolog.
+ */
+ for (check_addr = addr; instructions_to_check-- > 0; check_addr -= 4) {
+ if (!db_trace_get_val(check_addr, &inst))
+ break;
+
+ if (SUBU_R31_R31_IMM(inst)) {
#if 0
- /*
- * If the next instruction is "st r1, r31, ####"
- * then we can feel safe we have the start of
- * a function.
- */
- if (!db_trace_get_val(check_addr + 4, &inst))
- continue;
- if (ST_R1_R31_IMM(instr))
- break; /* sucess */
+ /*
+ * If the next instruction is "st r1, r31, ####"
+ * then we can feel safe we have the start of
+ * a function.
+ */
+ if (!db_trace_get_val(check_addr + 4, &inst))
+ continue;
+ if (ST_R1_R31_IMM(instr))
+ break; /* sucess */
#else
- /*
- * Latest GCC optimizer is just too good... the store
- * of r1 might come much later... so we'll have to
- * settle for just the "subr r31, r31, ###" to mark
- * the start....
- */
- break;
+ /*
+ * Latest GCC optimizer is just too good... the store
+ * of r1 might come much later... so we'll have to
+ * settle for just the "subr r31, r31, ###" to mark
+ * the start....
+ */
+ break;
#endif
- }
- /*
- * if we come across a [jmp r1] or [jmp.n r1] assume we have hit
- * the previous functions epilogue and stop our search.
- * Since we know we would have hit the "subr r31, r31" if it was
- * right in front of us, we know this doesn't have one so
- * we just return failure....
- */
- if (JMP_R1(inst) || JMPN_R1(inst)) {
+ }
+ /*
+ * if we come across a [jmp r1] or [jmp.n r1] assume we have hit
+ * the previous functions epilogue and stop our search.
+ * Since we know we would have hit the "subr r31, r31" if it was
+ * right in front of us, we know this doesn't have one so
+ * we just return failure....
+ */
+ if (JMP_R1(inst) || JMPN_R1(inst)) {
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON)
- db_printf("ran into a [jmp r1] at %x (addr=%x)\n",
- check_addr, addr);
+ if (DEBUGGING_ON)
+ db_printf("ran into a [jmp r1] at %x (addr=%x)\n",
+ check_addr, addr);
#endif
- return 0;
- }
- }
- if (instructions_to_check < 0) {
+ return 0;
+ }
+ }
+ if (instructions_to_check < 0) {
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON)
- db_printf("couldn't find func start (addr=%x)\n", addr);
+ if (DEBUGGING_ON)
+ db_printf("couldn't find func start (addr=%x)\n", addr);
#endif
- return 0; /* bummer, couldn't find it */
+ return 0; /* bummer, couldn't find it */
+ }
+ function_addr = check_addr;
}
- function_addr = check_addr;
- }
-
- /*
- * We now know the start of the function (function_addr).
- * If we're stopped right there, or if it's not a
- * subu r31, r31, ####
- * then we're done.
- */
- if (addr == function_addr) {
+
+ /*
+ * We now know the start of the function (function_addr).
+ * If we're stopped right there, or if it's not a
+ * subu r31, r31, ####
+ * then we're done.
+ */
+ if (addr == function_addr) {
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("at start of func\n");
+ if (DEBUGGING_ON) db_printf("at start of func\n");
#endif
- return 0;
- }
- if (!db_trace_get_val(function_addr, &inst)) {
+ return 0;
+ }
+ if (!db_trace_get_val(function_addr, &inst)) {
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("couldn't read %x at line %d\n",
- function_addr, __LINE__);
+ if (DEBUGGING_ON) db_printf("couldn't read %x at line %d\n",
+ function_addr, __LINE__);
#endif
- return 0;
- }
- SHOW_INSTRUCTION(function_addr, inst, "start of function: ");
- if (!SUBU_R31_R31_IMM(inst)) {
+ return 0;
+ }
+ SHOW_INSTRUCTION(function_addr, inst, "start of function: ");
+ if (!SUBU_R31_R31_IMM(inst)) {
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("<not subu,r31,r31,imm>\n");
+ if (DEBUGGING_ON) db_printf("<not subu,r31,r31,imm>\n");
#endif
- return 0;
- }
-
- /* add the size of this frame to the stack (for the next frame) */
- *stack += IMM16VAL(inst);
-
- /*
- * Search from the beginning of the function (funstart) to where we are
- * in the function (addr) looking to see what kind of registers have
- * been saved on the stack.
- *
- * We'll stop looking before we get to ADDR if we hit a branch.
- */
- clear_local_saved_regs();
- check_addr = function_addr + 4; /* we know the first inst isn't a store */
-
- for (instructions_to_search = (addr - check_addr)/sizeof(long);
- instructions_to_search-- > 0;
- check_addr += 4)
- {
- union instruction instruction;
- unsigned flags;
+ return 0;
+ }
+
+ /* add the size of this frame to the stack (for the next frame) */
+ *stack += IMM16VAL(inst);
+
+ /*
+ * Search from the beginning of the function (funstart) to where we are
+ * in the function (addr) looking to see what kind of registers have
+ * been saved on the stack.
+ *
+ * We'll stop looking before we get to ADDR if we hit a branch.
+ */
+ clear_local_saved_regs();
+ check_addr = function_addr + 4; /* we know the first inst isn't a store */
- /* read the instruction */
- if (!db_trace_get_val(check_addr, &instruction.rawbits)) {
+ for (instructions_to_search = (addr - check_addr)/sizeof(long);
+ instructions_to_search-- > 0;
+ check_addr += 4) {
+ union instruction instruction;
+ unsigned flags;
+
+ /* read the instruction */
+ if (!db_trace_get_val(check_addr, &instruction.rawbits)) {
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("couldn't read %x at line %d\n",
- check_addr, __LINE__);
+ if (DEBUGGING_ON) db_printf("couldn't read %x at line %d\n",
+ check_addr, __LINE__);
#endif
- break;
- }
-
- SHOW_INSTRUCTION(check_addr, instruction.rawbits, "prolog: ");
+ break;
+ }
- /* find out the particulars about this instruction */
- flags = m88k_instruction_info(instruction.rawbits);
+ SHOW_INSTRUCTION(check_addr, instruction.rawbits, "prolog: ");
+
+ /* find out the particulars about this instruction */
+ flags = m88k_instruction_info(instruction.rawbits);
+
+ /* if a store to something off the stack pointer, note the value */
+ if ((flags & STORE) && instruction.diatic.s1 == /*stack pointer*/31) {
+ unsigned value;
+ if (!have_local_reg(instruction.diatic.d)) {
+ if (instruction.diatic.d == 1)
+ tried_to_save_r1 = r31 + instruction.diatic.i16 ;
+ if (db_trace_get_val(r31 + instruction.diatic.i16, &value))
+ save_reg(instruction.diatic.d, value);
+ }
+ if ((flags & DOUBLE) && !have_local_reg(instruction.diatic.d + 1)) {
+ if (instruction.diatic.d == 0)
+ tried_to_save_r1 = r31+instruction.diatic.i16 +4;
+ if (db_trace_get_val(r31+instruction.diatic.i16 +4, &value))
+ save_reg(instruction.diatic.d + 1, value);
+ }
+ }
- /* if a store to something off the stack pointer, note the value */
- if ((flags & STORE) && instruction.diatic.s1 == /*stack pointer*/31)
- {
- unsigned value;
- if (!have_local_reg(instruction.diatic.d)) {
- if (instruction.diatic.d == 1)
- tried_to_save_r1 = r31 + instruction.diatic.i16 ;
- if (db_trace_get_val(r31 + instruction.diatic.i16, &value))
- save_reg(instruction.diatic.d, value);
- }
- if ((flags & DOUBLE) && !have_local_reg(instruction.diatic.d + 1)) {
- if (instruction.diatic.d == 0)
- tried_to_save_r1 = r31+instruction.diatic.i16 +4;
- if (db_trace_get_val(r31+instruction.diatic.i16 +4, &value))
- save_reg(instruction.diatic.d + 1, value);
- }
- }
+ /* if an inst that kills D (and maybe D+1), note that */
+ if (flags & TRASHES) {
+ mark_reg_trashed(instruction.diatic.d);
+ if (flags & DOUBLE)
+ mark_reg_trashed(instruction.diatic.d + 1);
+ }
- /* if an inst that kills D (and maybe D+1), note that */
- if (flags & TRASHES) {
- mark_reg_trashed(instruction.diatic.d);
- if (flags & DOUBLE)
- mark_reg_trashed(instruction.diatic.d + 1);
+ /* if a flow control instruction, stop now (or next if delayed) */
+ if ((flags & FLOW_CTRL) && instructions_to_search != 0)
+ instructions_to_search = (flags & DELAYED) ? 1 : 0;
}
- /* if a flow control instruction, stop now (or next if delayed) */
- if ((flags & FLOW_CTRL) && instructions_to_search != 0)
- instructions_to_search = (flags & DELAYED) ? 1 : 0;
- }
-
- /*
- * If we didn't save r1 at some point, we're hosed.
- */
- if (!have_local_reg(1)) {
- if (tried_to_save_r1) {
- db_printf(" <return value of next fcn unreadable in %08x>\n",
- tried_to_save_r1);
- }
+ /*
+ * If we didn't save r1 at some point, we're hosed.
+ */
+ if (!have_local_reg(1)) {
+ if (tried_to_save_r1) {
+ db_printf(" <return value of next fcn unreadable in %08x>\n",
+ tried_to_save_r1);
+ }
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("didn't save r1\n");
+ if (DEBUGGING_ON) db_printf("didn't save r1\n");
#endif
- return 0;
- }
+ return 0;
+ }
- ret_addr = saved_reg_value(1);
+ ret_addr = saved_reg_value(1);
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON)
- db_printf("Return value is = %x, function_addr is %x.\n",
- ret_addr, function_addr);
+ if (DEBUGGING_ON)
+ db_printf("Return value is = %x, function_addr is %x.\n",
+ ret_addr, function_addr);
#endif
- /*
- * In support of this, continuation.s puts the low bit on the
- * return address for continuations (the return address will never
- * be used, so it's ok to do anything you want to it).
- */
- if (ret_addr & 1) {
- note = "<<can not trace past a continuation>>";
- ret_addr = 0;
- } else if (ret_addr != 0x00) {
- switch(is_jump_source_ok(ret_addr, function_addr)) {
- case JUMP_SOURCE_IS_OK:
- break; /* excellent */
-
- case JUMP_SOURCE_IS_BAD:
+ /*
+ * In support of this, continuation.s puts the low bit on the
+ * return address for continuations (the return address will never
+ * be used, so it's ok to do anything you want to it).
+ */
+ if (ret_addr & 1) {
+ note = "<<can not trace past a continuation>>";
+ ret_addr = 0;
+ } else if (ret_addr != 0x00) {
+ switch (is_jump_source_ok(ret_addr, function_addr)) {
+ case JUMP_SOURCE_IS_OK:
+ break; /* excellent */
+
+ case JUMP_SOURCE_IS_BAD:
#ifdef TRACE_DEBUG
- if (DEBUGGING_ON) db_printf("jump is bad\n");
+ if (DEBUGGING_ON) db_printf("jump is bad\n");
#endif
- return 0; /* bummer */
+ return 0; /* bummer */
- case JUMP_SOURCE_IS_UNLIKELY:
- next_address_likely_wrong = 1;;
- break;
+ case JUMP_SOURCE_IS_UNLIKELY:
+ next_address_likely_wrong = 1;;
+ break;
+ }
}
- }
- return ret_addr;
+ return ret_addr;
}
static void
db_stack_trace_cmd2(db_regs_t *regs)
{
- unsigned stack;
- unsigned depth=1;
- unsigned where;
- unsigned ft;
- unsigned pair[2];
- int i;
-
- /*
- * Frame_is_sane returns:
- * 1 if regs seems to be a reasonable kernel exception frame.
- * 2 if regs seems to be a reasonable user exception frame
- * (in the current task).
- * 0 if this looks like neither.
- */
- if (ft = frame_is_sane(regs), ft == 0)
- {
- db_printf("Register frame 0x%x is suspicous; skipping trace\n", regs);
- return;
- }
-
- /* if user space and no user space trace specified, puke */
- if (ft == 2 && !(trace_flags & TRACE_USER_FLAG))
- return;
-
- /* fetch address */
- /* use sxip if valid, otherwise try snip or sfip */
- where = ((regs->sxip & 2) ? regs->sxip :
- ((regs->snip & 2) ? regs->snip :
- regs->sfip) ) & ~3;
- stack = regs->r[31];
- db_printf("stack base = 0x%x\n", stack);
- db_printf("(0) "); /*depth of trace */
- if (trace_flags & TRACE_SHOWADDRESS_FLAG)
- db_printf("%08x ", where);
- db_printsym(where, DB_STGY_PROC);
- clear_global_saved_regs();
-
- /* see if this routine had a stack frame */
- if ((where=stack_decode(where, &stack))==0)
- {
- where = regs->r[1];
- db_printf("(stackless)");
- }
- else
- {
- print_args();
- if (trace_flags & TRACE_SHOWFRAME_FLAG)
- db_printf(" [frame 0x%x]", stack);
- }
- db_printf("\n");
- if (note) {
- db_printf(" %s\n", note);
- note = 0;
- }
-
- do
- {
+ unsigned stack;
+ unsigned depth=1;
+ unsigned where;
+ unsigned ft;
+ unsigned pair[2];
+ int i;
+
/*
- * If requested, show preserved registers at the time
- * the next-shown call was made. Only registers known to have
- * changed from the last exception frame are shown, as others
- * can be gotten at by looking at the exception frame.
+ * Frame_is_sane returns:
+ * 1 if regs seems to be a reasonable kernel exception frame.
+ * 2 if regs seems to be a reasonable user exception frame
+ * (in the current task).
+ * 0 if this looks like neither.
*/
- if (trace_flags & TRACE_SHOWCALLPRESERVED_FLAG)
- {
- int r, title_printed = 0;
-
- for (r = FIRST_CALLPRESERVED_REG; r<=LAST_CALLPRESERVED_REG; r++) {
- if (have_global_reg(r)) {
- unsigned value = saved_reg_value(r);
- if (title_printed == 0) {
- title_printed = 1;
- db_printf("[in next func:");
- }
- if (value == 0)
- db_printf(" r%d", r);
- else if (value <= 9)
- db_printf(" r%d=%x", r, value);
- else
- db_printf(" r%d=x%x", r, value);
- }
- }
- if (title_printed)
- db_printf("]\n");
+ if (ft = frame_is_sane(regs), ft == 0) {
+ db_printf("Register frame 0x%x is suspicous; skipping trace\n", regs);
+ return;
}
- db_printf("(%d)%c", depth++, next_address_likely_wrong ? '?':' ');
- next_address_likely_wrong = 0;
+ /* if user space and no user space trace specified, puke */
+ if (ft == 2 && !(trace_flags & TRACE_USER_FLAG))
+ return;
+ /* fetch address */
+ /* use sxip if valid, otherwise try snip or sfip */
+ if (cputyp == CPU_88110) {
+ where = regs->exip & ~3;
+ } else {
+ where = ((regs->sxip & 2) ? regs->sxip :
+ ((regs->snip & 2) ? regs->snip :
+ regs->sfip) ) & ~3;
+ }
+ stack = regs->r[31];
+ db_printf("stack base = 0x%x\n", stack);
+ db_printf("(0) "); /*depth of trace */
if (trace_flags & TRACE_SHOWADDRESS_FLAG)
- db_printf("%08x ", where);
+ db_printf("%08x ", where);
db_printsym(where, DB_STGY_PROC);
- where = stack_decode(where, &stack);
- print_args();
- if (trace_flags & TRACE_SHOWFRAME_FLAG)
- db_printf(" [frame 0x%x]", stack);
+ clear_global_saved_regs();
+
+ /* see if this routine had a stack frame */
+ if ((where=stack_decode(where, &stack))==0) {
+ where = regs->r[1];
+ db_printf("(stackless)");
+ } else {
+ print_args();
+ if (trace_flags & TRACE_SHOWFRAME_FLAG)
+ db_printf(" [frame 0x%x]", stack);
+ }
db_printf("\n");
if (note) {
- db_printf(" %s\n", note);
- note = 0;
+ db_printf(" %s\n", note);
+ note = 0;
}
- } while (where);
- /* try to trace back over trap/exception */
+ do {
+ /*
+ * If requested, show preserved registers at the time
+ * the next-shown call was made. Only registers known to have
+ * changed from the last exception frame are shown, as others
+ * can be gotten at by looking at the exception frame.
+ */
+ if (trace_flags & TRACE_SHOWCALLPRESERVED_FLAG) {
+ int r, title_printed = 0;
+
+ for (r = FIRST_CALLPRESERVED_REG; r<=LAST_CALLPRESERVED_REG; r++) {
+ if (have_global_reg(r)) {
+ unsigned value = saved_reg_value(r);
+ if (title_printed == 0) {
+ title_printed = 1;
+ db_printf("[in next func:");
+ }
+ if (value == 0)
+ db_printf(" r%d", r);
+ else if (value <= 9)
+ db_printf(" r%d=%x", r, value);
+ else
+ db_printf(" r%d=x%x", r, value);
+ }
+ }
+ if (title_printed)
+ db_printf("]\n");
+ }
- stack &= ~7; /* double word aligned */
- /* take last top of stack, and try to find an exception frame near it */
+ db_printf("(%d)%c", depth++, next_address_likely_wrong ? '?':' ');
+ next_address_likely_wrong = 0;
+
+ if (trace_flags & TRACE_SHOWADDRESS_FLAG)
+ db_printf("%08x ", where);
+ db_printsym(where, DB_STGY_PROC);
+ where = stack_decode(where, &stack);
+ print_args();
+ if (trace_flags & TRACE_SHOWFRAME_FLAG)
+ db_printf(" [frame 0x%x]", stack);
+ db_printf("\n");
+ if (note) {
+ db_printf(" %s\n", note);
+ note = 0;
+ }
+ } while (where);
+
+ /* try to trace back over trap/exception */
- i = FRAME_PLAY;
+ stack &= ~7; /* double word aligned */
+ /* take last top of stack, and try to find an exception frame near it */
+
+ i = FRAME_PLAY;
#ifdef TRACE_DEBUG
if (DEBUGGING_ON)
- db_printf("(searching for exception frame at 0x%x)\n", stack);
+ db_printf("(searching for exception frame at 0x%x)\n", stack);
#endif
- while (i)
- {
+ while (i) {
+ /*
+ * On the stack, a pointer to the exception frame is written
+ * in two adjacent words. In the case of a fault from the kernel,
+ * this should point to the frame right above them:
+ *
+ * Exception Frame Top
+ * ..
+ * Exception Frame Bottom <-- frame addr
+ * frame addr
+ * frame addr <-- stack pointer
+ *
+ * In the case of a fault from user mode, the top of stack
+ * will just have the address of the frame
+ * replicated twice.
+ *
+ * frame addr <-- top of stack
+ * frame addr
+ *
+ * Here we are just looking for kernel exception frames.
+ */
+
+ if (badwordaddr((vm_offset_t)stack) ||
+ badwordaddr((vm_offset_t)(stack+4)))
+ break;
+
+ db_read_bytes((vm_offset_t)stack, 2*sizeof(int), (char*)pair);
+
+ /* the pairs should match and equal stack+8 */
+ if (pair[0] == pair[1]) {
+ if (pair[0] != stack+8) {
+ /*
+ if (!badwordaddr((vm_offset_t)pair[0]) && (pair[0]!=0))
+ db_printf("stack_trace:found pair 0x%x but != to stack+8\n",
+ pair[0]);
+ */
+
+ } else if (frame_is_sane((db_regs_t*)pair[0])) {
+ db_regs_t *frame = (db_regs_t *) pair[0];
+ char *cause = m88k_exception_name(frame -> vector);
+
+ db_printf("-------------- %s [EF: 0x%x] -------------\n",
+ cause, frame);
+ db_stack_trace_cmd2(frame);
+ return;
+ }
+ #ifdef TRACE_DEBUG
+ else if (DEBUGGING_ON)
+ db_printf("pair matched, but frame at 0x%x looks insane\n",
+ stack+8);
+ #endif
+ }
+ stack += 8;
+ i--;
+ }
+
/*
- * On the stack, a pointer to the exception frame is written
- * in two adjacent words. In the case of a fault from the kernel,
- * this should point to the frame right above them:
- *
- * Exception Frame Top
- * ..
- * Exception Frame Bottom <-- frame addr
- * frame addr
- * frame addr <-- stack pointer
- *
- * In the case of a fault from user mode, the top of stack
- * will just have the address of the frame
- * replicated twice.
- *
- * frame addr <-- top of stack
- * frame addr
- *
- * Here we are just looking for kernel exception frames.
+ * If we go here, crawling back on the stack failed to find us
+ * a previous exception frame. Look for a user frame pointer
+ * pointed to by a word 8 bytes off of the top of the stack
+ * if the "u" option was specified.
*/
+ if (trace_flags & TRACE_USER_FLAG) {
+ db_regs_t *user;
- if (badwordaddr((vm_offset_t)stack) ||
- badwordaddr((vm_offset_t)(stack+4)))
- break;
+ /* Make sure we are back on the right page */
+ stack -= 4*FRAME_PLAY;
+ stack = stack & ~(KERNEL_STACK_SIZE-1); /* point to the bottom */
+ stack += KERNEL_STACK_SIZE - 8;
- db_read_bytes((vm_offset_t)stack, 2*sizeof(int), (char*)pair);
+ if (badwordaddr((vm_offset_t)stack) ||
+ badwordaddr((vm_offset_t)stack))
+ return;
- /* the pairs should match and equal stack+8 */
- if (pair[0] == pair[1])
- {
- if (pair[0] != stack+8)
- {
- /*
- if (!badwordaddr((vm_offset_t)pair[0]) && (pair[0]!=0))
- db_printf("stack_trace:found pair 0x%x but != to stack+8\n",
- pair[0]);
- */
- }
- else if (frame_is_sane((db_regs_t*)pair[0]))
- {
- db_regs_t *frame = (db_regs_t *) pair[0];
- char *cause = m88k_exception_name(frame -> vector);
-
- db_printf("-------------- %s [EF: 0x%x] -------------\n",
- cause, frame);
- db_stack_trace_cmd2(frame);
- return;
- }
- #ifdef TRACE_DEBUG
- else if (DEBUGGING_ON)
- db_printf("pair matched, but frame at 0x%x looks insane\n",
- stack+8);
- #endif
- }
- stack += 8;
- i--;
- }
-
- /*
- * If we go here, crawling back on the stack failed to find us
- * a previous exception frame. Look for a user frame pointer
- * pointed to by a word 8 bytes off of the top of the stack
- * if the "u" option was specified.
- */
- if (trace_flags & TRACE_USER_FLAG)
- {
- db_regs_t *user;
-
- /* Make sure we are back on the right page */
- stack -= 4*FRAME_PLAY;
- stack = stack & ~(KERNEL_STACK_SIZE-1); /* point to the bottom */
- stack += KERNEL_STACK_SIZE - 8;
-
- if (badwordaddr((vm_offset_t)stack) ||
- badwordaddr((vm_offset_t)stack))
- return;
-
- db_read_bytes((vm_offset_t)stack, 2*sizeof(int), (char*)pair);
- if (pair[0] != pair[1])
- return;
-
- /* have a hit */
- user = *((db_regs_t **) stack);
-
- if (frame_is_sane(user) == 2)
- {
- db_printf("---------------- %s [EF : 0x%x] -------------\n",
- m88k_exception_name(user->vector), user);
- db_stack_trace_cmd2(user);
+ db_read_bytes((vm_offset_t)stack, 2*sizeof(int), (char*)pair);
+ if (pair[0] != pair[1])
+ return;
+
+ /* have a hit */
+ user = *((db_regs_t **) stack);
+
+ if (frame_is_sane(user) == 2) {
+ db_printf("---------------- %s [EF : 0x%x] -------------\n",
+ m88k_exception_name(user->vector), user);
+ db_stack_trace_cmd2(user);
+ }
}
- }
}
/*
@@ -1013,153 +1004,153 @@ db_stack_trace_cmd2(db_regs_t *regs)
*/
void
db_stack_trace_cmd(
- db_regs_t *addr,
- int have_addr,
- db_expr_t count,
- char *modif)
+ db_regs_t *addr,
+ int have_addr,
+ db_expr_t count,
+ char *modif)
{
- enum { Default, Stack, Proc, Frame } style = Default;
- db_regs_t frame; /* a m88100_saved_state */
- db_regs_t *regs;
- union {
- db_regs_t *frame;
- struct proc *proc;
- unsigned num;
- } arg;
- arg.frame = addr;
-
- trace_flags = 0; /* flags will be set via modifers */
-
- while (modif && *modif) {
- switch (*modif++)
- {
- case 'd':
+ enum {
+ Default, Stack, Proc, Frame
+ } style = Default;
+ db_regs_t frame; /* a m88100_saved_state */
+ db_regs_t *regs;
+ union {
+ db_regs_t *frame;
+ struct proc *proc;
+ unsigned num;
+ } arg;
+ arg.frame = addr;
+
+ trace_flags = 0; /* flags will be set via modifers */
+
+ while (modif && *modif) {
+ switch (*modif++) {
+ case 'd':
#ifdef TRACE_DEBUG
- trace_flags |= TRACE_DEBUG_FLAG;
+ trace_flags |= TRACE_DEBUG_FLAG;
#else
- db_printtf("<debug trace not compiled in, ignoring>\n");
+ db_printtf("<debug trace not compiled in, ignoring>\n");
#endif
- break;
-
- case 's': style = Stack ; break;
- case 'f': style = Frame ; break;
- case 'p': trace_flags |= TRACE_SHOWCALLPRESERVED_FLAG; break;
- case 'a': trace_flags |= TRACE_SHOWADDRESS_FLAG; break;
- case 'F': trace_flags |= TRACE_SHOWFRAME_FLAG; break;
- case 'u': trace_flags |= TRACE_USER_FLAG; break;
- default:
- db_printf("unknown trace modifier [%c]\n", modif[-1]);
- /*FALLTHROUGH*/
- case 'h':
- db_printf("usage: trace/[MODIFIER] [ARG]\n");
- db_printf(" u = include user trace\n");
- db_printf(" F = print stack frames\n");
- db_printf(" a = show return addresses\n");
- db_printf(" p = show call-preserved registers\n");
- db_printf(" s = ARG is a stack pointer\n");
- db_printf(" f = ARG is a frame pointer\n");
+ break;
+
+ case 's': style = Stack ; break;
+ case 'f': style = Frame ; break;
+ case 'p': trace_flags |= TRACE_SHOWCALLPRESERVED_FLAG; break;
+ case 'a': trace_flags |= TRACE_SHOWADDRESS_FLAG; break;
+ case 'F': trace_flags |= TRACE_SHOWFRAME_FLAG; break;
+ case 'u': trace_flags |= TRACE_USER_FLAG; break;
+ default:
+ db_printf("unknown trace modifier [%c]\n", modif[-1]);
+ /*FALLTHROUGH*/
+ case 'h':
+ db_printf("usage: trace/[MODIFIER] [ARG]\n");
+ db_printf(" u = include user trace\n");
+ db_printf(" F = print stack frames\n");
+ db_printf(" a = show return addresses\n");
+ db_printf(" p = show call-preserved registers\n");
+ db_printf(" s = ARG is a stack pointer\n");
+ db_printf(" f = ARG is a frame pointer\n");
#ifdef TRACE_DEBUG
- db_printf(" d = trace-debugging output\n");
+ db_printf(" d = trace-debugging output\n");
#endif
- return;
+ return;
+ }
}
- }
-
- if (!have_addr && style != Default) {
- db_printf("expecting argument with /s or /f\n");
- return;
- }
- if (have_addr && style == Default)
- style = Proc;
-
- switch(style)
- {
- case Default:
- regs = DDB_REGS;
- break;
-
- case Frame:
- regs = arg.frame;
- break;
-
- case Proc:
- break;
-
- case Stack:
- {
- unsigned val1, val2, sxip;
- unsigned ptr;
- bzero((void*)&frame, sizeof(frame));
- #define REASONABLE_FRAME_DISTANCE 2048
- /*
- * We've got to find the top of a stack frame so we can get both
- * a PC and and real SP.
- */
- for (ptr = arg.num;/**/; ptr += 4) {
- /* Read a word from the named stack */
- if (db_trace_get_val(ptr, &val1) == 0) {
- db_printf("can't read from %x, aborting.\n", ptr);
+ if (!have_addr && style != Default) {
+ db_printf("expecting argument with /s or /f\n");
return;
- }
-
- /*
- * See if it's a frame pointer.... if so it will be larger than
- * the address it was taken from (i.e. point back up the stack)
- * and we'll be able to read where it points.
- */
- if (val1 <= ptr ||
- (val1 & 3) ||
- val1 > (ptr + REASONABLE_FRAME_DISTANCE))
- continue;
-
- /* peek at the next word to see if it could be a return address */
- if (db_trace_get_val(ptr, &sxip) == 0) {
- db_printf("can't read from %x, aborting.\n", ptr);
- return;
- }
- if (sxip == 0 || !db_trace_get_val(sxip, &val2))
- continue;
-
- if (db_trace_get_val(val1, &val2) == 0) {
- db_printf("can't read from %x, aborting.\n", val1);
- continue;
- }
-
- /*
- * The value we've just read will be either another frame pointer,
- * or the start of another exception frame.
- */
- if (
+ }
+ if (have_addr && style == Default)
+ style = Proc;
+
+ switch (style) {
+ case Default:
+ regs = DDB_REGS;
+ break;
+
+ case Frame:
+ regs = arg.frame;
+ break;
+
+ case Proc:
+ break;
+
+ case Stack:
+ {
+ unsigned val1, val2, sxip;
+ unsigned ptr;
+ bzero((void*)&frame, sizeof(frame));
+ #define REASONABLE_FRAME_DISTANCE 2048
+
+ /*
+ * We've got to find the top of a stack frame so we can get both
+ * a PC and and real SP.
+ */
+ for (ptr = arg.num;/**/; ptr += 4) {
+ /* Read a word from the named stack */
+ if (db_trace_get_val(ptr, &val1) == 0) {
+ db_printf("can't read from %x, aborting.\n", ptr);
+ return;
+ }
+
+ /*
+ * See if it's a frame pointer.... if so it will be larger than
+ * the address it was taken from (i.e. point back up the stack)
+ * and we'll be able to read where it points.
+ */
+ if (val1 <= ptr ||
+ (val1 & 3) ||
+ val1 > (ptr + REASONABLE_FRAME_DISTANCE))
+ continue;
+
+ /* peek at the next word to see if it could be a return address */
+ if (db_trace_get_val(ptr, &sxip) == 0) {
+ db_printf("can't read from %x, aborting.\n", ptr);
+ return;
+ }
+ if (sxip == 0 || !db_trace_get_val(sxip, &val2))
+ continue;
+
+ if (db_trace_get_val(val1, &val2) == 0) {
+ db_printf("can't read from %x, aborting.\n", val1);
+ continue;
+ }
+
+ /*
+ * The value we've just read will be either another frame pointer,
+ * or the start of another exception frame.
+ */
+ if (
#ifdef JEFF_DEBUG
- val2 == 0
+ val2 == 0
#else
- val2 == 0x12345678
+ val2 == 0x12345678
#endif
- && db_trace_get_val(val1-4, &val2) && val2 == val1
- && db_trace_get_val(val1-8, &val2) && val2 == val1)
- {
- /* we've found a frame, so the stack must have been good */
- db_printf("%x looks like a frame, accepting %x\n",val1,ptr);
- break;
- }
-
- if (val2 > val1 && (val2 & 3) == 0) {
- /* well, looks close enough to be another frame pointer */
- db_printf("*%x = %x looks like a stack frame pointer, accepting %x\n", val1, val2, ptr);
- break;
- }
+ && db_trace_get_val(val1-4, &val2) && val2 == val1
+ && db_trace_get_val(val1-8, &val2) && val2 == val1) {
+ /* we've found a frame, so the stack must have been good */
+ db_printf("%x looks like a frame, accepting %x\n",val1,ptr);
+ break;
+ }
+
+ if (val2 > val1 && (val2 & 3) == 0) {
+ /* well, looks close enough to be another frame pointer */
+ db_printf("*%x = %x looks like a stack frame pointer, accepting %x\n", val1, val2, ptr);
+ break;
+ }
+ }
+
+ frame.r[31] = ptr;
+ frame.epsr = 0x800003f0U;
+ frame.sxip = sxip | 2;
+ frame.snip = frame.sxip + 4;
+ frame.sfip = frame.snip + 4;
+ db_printf("[r31=%x, sxip=%x]\n", frame.r[31], frame.sxip);
+ regs = &frame;
+ }
}
- frame.r[31] = ptr;
- frame.epsr = 0x800003f0U;
- frame.sxip = sxip | 2;
- frame.snip = frame.sxip + 4;
- frame.sfip = frame.snip + 4;
- db_printf("[r31=%x, sxip=%x]\n", frame.r[31], frame.sxip);
- regs = &frame;
- }
- }
-
- db_stack_trace_cmd2(regs);
+ db_stack_trace_cmd2(regs);
}
+
diff --git a/sys/arch/mvme88k/dev/bugtty.c b/sys/arch/mvme88k/dev/bugtty.c
index 99750a59e81..b751d32d2e3 100644
--- a/sys/arch/mvme88k/dev/bugtty.c
+++ b/sys/arch/mvme88k/dev/bugtty.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: bugtty.c,v 1.7 2001/03/09 05:44:38 smurph Exp $ */
+/* $OpenBSD: bugtty.c,v 1.8 2001/12/13 08:55:51 smurph Exp $ */
/* Copyright (c) 1998 Steve Murphree, Jr.
* Copyright (c) 1995 Dale Rahn.
* All rights reserved.
@@ -476,21 +476,6 @@ bugttycnprobe(cp)
return (0);
}
-#if 0
- switch (cputyp) {
- case CPU_147:
- case CPU_162:
- cp->cn_pri = CN_NORMAL;
- return (0);
- default:
- break;
- }
-#endif
-#if 0
- cp->cn_pri = CN_NORMAL;
- return (0);
-#endif /* 0 */
-
/* locate the major number */
for (maj = 0; maj < nchrdev; maj++)
if (cdevsw[maj].d_open == bugttyopen)
diff --git a/sys/arch/mvme88k/dev/busswfunc.h b/sys/arch/mvme88k/dev/busswfunc.h
new file mode 100644
index 00000000000..9e298b4ddab
--- /dev/null
+++ b/sys/arch/mvme88k/dev/busswfunc.h
@@ -0,0 +1,9 @@
+/* $OpenBSD: busswfunc.h,v 1.1 2001/12/13 08:55:51 smurph Exp $ */
+
+#ifndef _MVME88K_BUSSWF_H_
+#define _MVME88K_BUSSWF_H_
+
+int busswintr_establish __P((int vec, struct intrhand *ih));
+
+#endif /* _MVME88K_PCCTWO_H_ */
+
diff --git a/sys/arch/mvme88k/dev/busswitch.c b/sys/arch/mvme88k/dev/busswitch.c
deleted file mode 100644
index 8be2af870e3..00000000000
--- a/sys/arch/mvme88k/dev/busswitch.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* $OpenBSD: busswitch.c,v 1.4 2001/03/09 05:44:38 smurph Exp $ */
-
-/*
- * Copyright (c) 1999 Steve Murphree, Jr.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed under OpenBSD by
- * Theo de Raadt for Willowglen Singapore.
- * 4. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/param.h>
-#include <sys/kernel.h>
-#include <sys/ioctl.h>
-#include <sys/device.h>
-#include <sys/systm.h>
-#include <sys/uio.h>
-#include <sys/malloc.h>
-#include <machine/psl.h>
-#include <machine/autoconf.h>
-#include <machine/bugio.h>
-#include <machine/cpu.h>
-#include <machine/mioctl.h>
-#include <machine/vmparam.h>
-
-#include <mvme88k/dev/busswitchreg.h>
-
-struct busswitchsoftc {
- struct device sc_dev;
- void * sc_paddr;
- void * sc_vaddr;
- int sc_len;
- struct busswitchreg * sc_busswitch;
-};
-
-void busswitchattach __P((struct device *, struct device *, void *));
-int busswitchmatch __P((struct device *, void *, void *));
-
-struct cfattach busswitch_ca = {
- sizeof(struct busswitchsoftc), busswitchmatch, busswitchattach
-};
-
-struct cfdriver busswitch_cd = {
- NULL, "busswitch", DV_DULL, 0
-};
-
-int busswitch_print __P((void *args, const char *bus));
-int busswitch_scan __P((struct device *parent, void *child, void *args));
-
-int
-busswitchmatch(parent, vcf, args)
- struct device *parent;
- void *vcf, *args;
-{
- struct confargs *ca = args;
- struct busswitchreg *busswitch;
- /* Don't match if wrong cpu */
- if (cputyp != CPU_197) return (0);
-
- busswitch = (struct busswitchreg *)(IIOV(ca->ca_paddr));
- if (badvaddr((vm_offset_t)busswitch, 4) <= 0){
- printf("==> busswitch: failed address check.\n");
- return (0);
- }
- return (1);
-}
-
-void
-busswitchattach(parent, self, args)
- struct device *parent, *self;
- void *args;
-{
- struct confargs *ca = args;
- struct busswitchsoftc *sc = (struct busswitchsoftc *)self;
-
- sc->sc_paddr = ca->ca_paddr;
- sc->sc_vaddr = ca->ca_vaddr;
-
- /*
- printf(": rev %d\n", sc->sc_busswitch->chiprev);
- */
- printf(": rev %d\n", 0);
-}
-
-int
-busswitch_print(args, bus)
- void *args;
- const char *bus;
-{
- struct confargs *ca = args;
-
- if (ca->ca_offset != -1)
- printf(" offset 0x%x", ca->ca_offset);
- if (ca->ca_ipl > 0)
- printf(" ipl %d", ca->ca_ipl);
- return (UNCONF);
-}
-
-int
-busswitch_scan(parent, child, args)
- struct device *parent;
- void *child, *args;
-{
- struct cfdata *cf = child;
- struct busswitchsoftc *sc = (struct busswitchsoftc *)parent;
- struct confargs oca;
-
- if (parent->dv_cfdata->cf_driver->cd_indirect) {
- printf(" indirect devices not supported\n");
- return 0;
- }
-
- bzero(&oca, sizeof oca);
- oca.ca_offset = cf->cf_loc[0];
- oca.ca_ipl = cf->cf_loc[1];
- if (((int)oca.ca_offset != -1) && ISIIOVA(sc->sc_vaddr + oca.ca_offset)) {
- oca.ca_vaddr = sc->sc_vaddr + oca.ca_offset;
- oca.ca_paddr = sc->sc_paddr + oca.ca_offset;
- } else {
- oca.ca_vaddr = (void *)-1;
- oca.ca_paddr = (void *)-1;
- }
- oca.ca_bustype = BUS_BUSSWITCH;
- oca.ca_master = (void *)sc->sc_busswitch;
- oca.ca_name = cf->cf_driver->cd_name;
- if ((*cf->cf_attach->ca_match)(parent, cf, &oca) == 0)
- return (0);
- config_attach(parent, cf, &oca, busswitch_print);
- return (1);
-}
-
diff --git a/sys/arch/mvme88k/dev/busswitchreg.h b/sys/arch/mvme88k/dev/busswitchreg.h
deleted file mode 100644
index d1f95c717a2..00000000000
--- a/sys/arch/mvme88k/dev/busswitchreg.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* $OpenBSD: busswitchreg.h,v 1.1 1999/09/27 18:43:22 smurph Exp $ */
-
-/*
- * Memory map for BusSwitch chip found in mvme197 boards.
- */
-
-struct busswitchreg {
- unsigned start;
-};
-
diff --git a/sys/arch/mvme88k/dev/cl.c b/sys/arch/mvme88k/dev/cl.c
index 8fbcb608af8..ec3152e3b33 100644
--- a/sys/arch/mvme88k/dev/cl.c
+++ b/sys/arch/mvme88k/dev/cl.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: cl.c,v 1.14 2001/08/31 01:05:44 miod Exp $ */
+/* $OpenBSD: cl.c,v 1.15 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1995 Dale Rahn. All rights reserved.
@@ -217,8 +217,6 @@ int dopoll = 1;
#define CL_CHANNEL(x) (minor(x) & 3)
#define CL_TTY(x) (minor(x))
-extern int cputyp;
-
struct tty *cltty __P((dev_t dev));
struct tty *cltty(dev)
@@ -247,20 +245,17 @@ clprobe(parent, self, aux)
*/
struct clreg *cl_reg;
struct confargs *ca = aux;
- int ret;
- if (cputyp != CPU_187)
+
+ if (brdtyp == BRD_188)
return 0;
ca->ca_ipl = IPL_TTY;
- ca->ca_paddr = (void *)CD2400_BASE_ADDR;
+ ca->ca_vaddr = ca->ca_paddr = (void *)CD2400_BASE_ADDR;
cl_reg = (struct clreg *)ca->ca_vaddr;
-#if 0
- ret = !badvaddr(&cl_reg->cl_gfrcr,1);
-#else
- ret = 1;
-#endif
- return ret;
+ if (badvaddr(&cl_reg->cl_gfrcr,1))
+ return 0;
+ return 1;
}
void
@@ -401,10 +396,10 @@ cl_initchannel(sc, channel)
cl_reg->cl_cor5 = 0xec;
cl_reg->cl_cor6 = 0x00;
cl_reg->cl_cor7 = 0x00;
- cl_reg->cl_schr1 = 0x00;
- cl_reg->cl_schr2 = 0x00;
- cl_reg->cl_schr3 = 0x00;
- cl_reg->cl_schr4 = 0x00;
+ cl_reg->cl_schr1 = 0x00;
+ cl_reg->cl_schr2 = 0x00;
+ cl_reg->cl_schr3 = 0x00;
+ cl_reg->cl_schr4 = 0x00;
cl_reg->cl_scrl = 0x00;
cl_reg->cl_scrh = 0x00;
cl_reg->cl_lnxt = 0x00;
@@ -413,10 +408,10 @@ cl_initchannel(sc, channel)
cl_reg->cl_tbpr = 0x40; /* 9600 */
cl_reg->cl_tcor = 0x01 << 5;
/* console port should be 0x88 already */
- cl_reg->cl_msvr_rts = 0x00;
- cl_reg->cl_msvr_dtr = 0x00;
- cl_reg->cl_rtprl = CL_RX_TIMEOUT;
- cl_reg->cl_rtprh = 0x00;
+ cl_reg->cl_msvr_rts = 0x00;
+ cl_reg->cl_msvr_dtr = 0x00;
+ cl_reg->cl_rtprl = CL_RX_TIMEOUT;
+ cl_reg->cl_rtprh = 0x00;
}
sc->cl_reg->cl_ccr = 0x20;
while (sc->cl_reg->cl_ccr != 0) {
@@ -928,7 +923,7 @@ clcnprobe(cp)
int maj;
/* bomb if it'a a MVME188 */
- if (cputyp == CPU_188) {
+ if (brdtyp == BRD_188) {
cp->cn_pri = CN_DEAD;
return 0;
}
@@ -938,7 +933,7 @@ clcnprobe(cp)
break;
cp->cn_dev = makedev (maj, 0);
cp->cn_pri = CN_NORMAL;
-
+
return 1;
}
@@ -948,7 +943,7 @@ clcninit(cp)
{
volatile struct clreg *cl_reg;
- cl_cons.cl_paddr = (void *)0xfff45000;
+ cl_cons.cl_paddr = (void *)CD2400_BASE_ADDR;
cl_cons.cl_vaddr = (struct clreg *)IIOV(cl_cons.cl_paddr);
cl_cons.pcctwoaddr = (void *)IIOV(0xfff42000);
cl_reg = cl_cons.cl_vaddr;
diff --git a/sys/arch/mvme88k/dev/clock.c b/sys/arch/mvme88k/dev/clock.c
index c6893fd14f0..9dd6150e516 100644
--- a/sys/arch/mvme88k/dev/clock.c
+++ b/sys/arch/mvme88k/dev/clock.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: clock.c,v 1.11 2001/10/28 00:57:20 miod Exp $ */
+/* $OpenBSD: clock.c,v 1.12 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* Copyright (c) 1995 Theo de Raadt
@@ -191,7 +191,7 @@ clockattach(parent, self, args)
sc->sc_profih.ih_ipl = ca->ca_ipl;
prof_reset = ca->ca_ipl | PCC2_IRQ_IEN | PCC2_IRQ_ICLR;
pcctwointr_establish(PCC2V_TIMER1, &sc->sc_profih);
- mdfp.clock_init_func = &sbc_initclock;
+ md.clock_init_func = sbc_initclock;
printf(": VME1x7");
break;
#endif /* NPCCTWO */
@@ -202,7 +202,7 @@ clockattach(parent, self, args)
sc->sc_profih.ih_wantframe = 1;
sc->sc_profih.ih_ipl = ca->ca_ipl;
sysconintr_establish(SYSCV_TIMER1, &sc->sc_profih);
- mdfp.clock_init_func = &m188_initclock;
+ md.clock_init_func = m188_initclock;
printf(": VME188");
break;
#endif /* NSYSCON */
@@ -264,7 +264,7 @@ delay(us)
* Do not go to the real timer until vme device is present.
* Or, in the case of MVME188, not at all.
*/
- if (sys_vme2 == NULL || cputyp == CPU_188) {
+ if (sys_vme2 == NULL || brdtyp == BRD_188) {
c = 3 * us;
while (--c > 0);
return (0);
diff --git a/sys/arch/mvme88k/dev/dart.c b/sys/arch/mvme88k/dev/dart.c
index e552e970f58..35c3df8dce2 100644
--- a/sys/arch/mvme88k/dev/dart.c
+++ b/sys/arch/mvme88k/dev/dart.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: dart.c,v 1.12 2001/08/31 08:18:24 miod Exp $ */
+/* $OpenBSD: dart.c,v 1.13 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
@@ -185,10 +185,11 @@ dartmatch(parent, vcf, args)
union dartreg *addr;
/* Don't match if wrong cpu */
- if (cputyp != CPU_188) return (0);
+ if (brdtyp != BRD_188) return (0);
ca->ca_vaddr = ca->ca_paddr; /* 1:1 */
addr = (union dartreg *)ca->ca_vaddr;
- if (badvaddr((vaddr_t)addr, 2) <= 0) {
+
+ if (badvaddr((vaddr_t)addr, 2)) {
printf("==> dart: failed address check.\n");
return (0);
}
@@ -1138,7 +1139,7 @@ dartcnprobe(cp)
{
int maj;
- if (cputyp != CPU_188) {
+ if (brdtyp != BRD_188) {
cp->cn_pri = CN_DEAD;
return 0;
}
diff --git a/sys/arch/mvme88k/dev/if_ie.c b/sys/arch/mvme88k/dev/if_ie.c
index 25b1e7a0422..43a1d46c71d 100644
--- a/sys/arch/mvme88k/dev/if_ie.c
+++ b/sys/arch/mvme88k/dev/if_ie.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_ie.c,v 1.16 2001/11/28 16:13:28 art Exp $ */
+/* $OpenBSD: if_ie.c,v 1.17 2001/12/13 08:55:51 smurph Exp $ */
/*-
* Copyright (c) 1998 Steve Murphree, Jr.
@@ -282,7 +282,7 @@ int in_ierint = 0;
int in_ietint = 0;
#endif
-int iematch __P((struct device *, void *, void *));
+int iematch __P((struct device *, void *, void *));
void ieattach __P((struct device *, struct device *, void *));
struct cfattach ie_ca = {
@@ -352,9 +352,8 @@ iematch(parent, vcf, args)
void *vcf, *args;
{
struct confargs *ca = args;
- int ret;
- if ((ret = badvaddr((unsigned)IIOV(ca->ca_vaddr), 1)) <=0){
+ if (badvaddr((unsigned)IIOV(ca->ca_vaddr), 1)){
return(0);
}
return(1);
@@ -540,7 +539,7 @@ ieintr(v)
register u_short status;
status = sc->scb->ie_status;
-/*printf("I");*/
+/* printf("I"); */
loop:
/* Ack interrupts FIRST in case we receive more during the ISR. */
@@ -889,11 +888,11 @@ iexmit(sc)
#endif
#if 0
-printf("iexmit base %x cmd %x bfd %x to %x\n",
-sc->sc_maddr,
-sc->xmit_cmds[sc->xctail],
-sc->xmit_buffs[sc->xctail],
-sc->xmit_cbuffs[sc->xctail]);
+ printf("iexmit base %x cmd %x bfd %x to %x\n",
+ sc->sc_maddr,
+ sc->xmit_cmds[sc->xctail],
+ sc->xmit_buffs[sc->xctail],
+ sc->xmit_cbuffs[sc->xctail]);
#endif
sc->xmit_buffs[sc->xctail]->ie_xmit_flags |= IE_XMIT_LAST;
sc->xmit_buffs[sc->xctail]->ie_xmit_next = 0xffffffff;
diff --git a/sys/arch/mvme88k/dev/if_ve.c b/sys/arch/mvme88k/dev/if_ve.c
index c075274a554..a90e89fcbcf 100644
--- a/sys/arch/mvme88k/dev/if_ve.c
+++ b/sys/arch/mvme88k/dev/if_ve.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_ve.c,v 1.11 2001/11/06 19:53:15 miod Exp $ */
+/* $OpenBSD: if_ve.c,v 1.12 2001/12/13 08:55:51 smurph Exp $ */
/*-
* Copyright (c) 1999 Steve Murphree, Jr.
* Copyright (c) 1982, 1992, 1993
@@ -71,7 +71,7 @@
#include <machine/autoconf.h>
#include <machine/cpu.h>
#include <machine/bugio.h>
-#include <machine/mmu.h> /* DMA_CACHE_SYNC, etc... */
+#include <machine/cmmu.h> /* DMA_CACHE_SYNC, etc... */
#include <mvme88k/dev/if_vereg.h>
#include <mvme88k/dev/if_vevar.h>
@@ -247,11 +247,9 @@ vematch(parent, vcf, args)
{
struct confargs *ca = args;
- if (!badvaddr((unsigned)ca->ca_vaddr, 1)) {
- return (1);
- } else {
+ if (badvaddr((unsigned)ca->ca_vaddr, 1))
return (0);
- }
+ return (1);
}
/*
diff --git a/sys/arch/mvme88k/dev/mainbus.c b/sys/arch/mvme88k/dev/mainbus.c
index ccda4910b1a..d8d08d2edfe 100644
--- a/sys/arch/mvme88k/dev/mainbus.c
+++ b/sys/arch/mvme88k/dev/mainbus.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: mainbus.c,v 1.4 2001/08/26 02:37:07 miod Exp $ */
+/* $OpenBSD: mainbus.c,v 1.5 2001/12/13 08:55:51 smurph Exp $ */
/* Copyright (c) 1998 Steve Murphree, Jr. */
#include <sys/param.h>
#include <sys/systm.h>
@@ -69,7 +69,7 @@ mainbus_attach(parent, self, args)
struct device *parent, *self;
void *args;
{
- printf (" machine type MVME%x\n", cputyp);
+ printf (" machine type MVME%x\n", brdtyp);
/* XXX
* should have a please-attach-first list for mainbus,
diff --git a/sys/arch/mvme88k/dev/nvram.c b/sys/arch/mvme88k/dev/nvram.c
index 0c75d10c2c8..ae3f4260206 100644
--- a/sys/arch/mvme88k/dev/nvram.c
+++ b/sys/arch/mvme88k/dev/nvram.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: nvram.c,v 1.13 2001/11/06 00:30:38 art Exp $ */
+/* $OpenBSD: nvram.c,v 1.14 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1995 Theo de Raadt
@@ -102,13 +102,7 @@ nvrammatch(parent, vcf, args)
#if 0
bugrtcrd(&rtc);
- ret = badvaddr(IIOV(ca->ca_vaddr), 1);
- if (ret != 0)
- ret = badvaddr(IIOV(ca->ca_vaddr), 2);
- if (ret != 0)
- ret = badvaddr(IIOV(ca->ca_vaddr), 4);
-
- if (ret != 0) {
+ if (badvaddr(IIOV(ca->ca_vaddr), 1)) {
printf("==> nvram: address 0x%x failed check\n", ca->ca_vaddr);
return (0);
} else
@@ -130,7 +124,7 @@ nvramattach(parent, self, args)
sc->sc_paddr = ca->ca_paddr;
sc->sc_vaddr = ca->ca_vaddr;
- if (cputyp == CPU_188) {
+ if (brdtyp == BRD_188) {
sc->sc_len = MK48T02_SIZE;
} else {
sc->sc_len = MK48T08_SIZE;
@@ -142,7 +136,7 @@ nvramattach(parent, self, args)
/*X*/ if (sc->sc_vaddr == NULL)
/*X*/ panic("failed to map!");
- if (cputyp != CPU_188) {
+ if (brdtyp != BRD_188) {
sc->sc_regs = (void *)(sc->sc_vaddr + sc->sc_len -
sizeof(struct clockreg));
} else {
@@ -322,7 +316,7 @@ inittodr(base)
base = 21*SECYR + 186*SECDAY + SECDAY/2;
badbase = 1;
}
- if (cputyp != CPU_188) {
+ if (brdtyp != BRD_188) {
register struct clockreg *cl = (struct clockreg *)sc->sc_regs;
cl->cl_csr |= CLK_READ; /* enable read (stop time) */
sec = cl->cl_sec;
@@ -378,7 +372,7 @@ void resettodr()
{
struct nvramsoftc *sc = (struct nvramsoftc *) nvram_cd.cd_devs[0];
struct chiptime c;
- if (cputyp != CPU_188) {
+ if (brdtyp != BRD_188) {
register struct clockreg *cl = (struct clockreg *)sc->sc_regs;
if (!time.tv_sec || cl == NULL)
diff --git a/sys/arch/mvme88k/dev/pcctwo.c b/sys/arch/mvme88k/dev/pcctwo.c
index 6cd485df2a2..6cf93f58b29 100644
--- a/sys/arch/mvme88k/dev/pcctwo.c
+++ b/sys/arch/mvme88k/dev/pcctwo.c
@@ -1,5 +1,5 @@
-/* $OpenBSD: pcctwo.c,v 1.10 2001/03/08 00:03:14 miod Exp $ */
+/* $OpenBSD: pcctwo.c,v 1.11 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1995 Theo de Raadt
@@ -56,6 +56,8 @@
#include <mvme88k/dev/pcctwofunc.h>
#include <mvme88k/dev/pcctworeg.h>
+#include "bussw.h"
+
struct pcctwosoftc {
struct device sc_dev;
void *sc_vaddr; /* PCC2 space */
@@ -76,6 +78,8 @@ struct cfdriver pcctwo_cd = {
struct pcctworeg *sys_pcc2 = NULL;
+int pcc2bus;
+
int pcctwo_print __P((void *args, const char *bus));
int pcctwo_scan __P((struct device *parent, void *child, void *args));
@@ -88,25 +92,25 @@ pcctwomatch(parent, vcf, args)
struct pcctworeg *pcc2;
/* Bomb if wrong cpu */
- switch (cputyp) {
- case CPU_187:
- pcc2 = (struct pcctworeg *)(IIOV(ca->ca_paddr) + PCC2_PCC2CHIP_OFF);
- break;
- case CPU_197: /* pcctwo is a child of buswitch XXX smurph */
- pcc2 = (struct pcctworeg *)(IIOV(ca->ca_paddr));
- break;
- default:
- /* Bomb if wrong cpu */
- return (0);
- }
+ switch (brdtyp) {
+ case BRD_187:
+ pcc2 = (struct pcctworeg *)(IIOV(ca->ca_paddr) + PCC2_PCC2CHIP_OFF);
+ break;
+ case BRD_197: /* pcctwo is a child of buswitch XXX smurph */
+ pcc2 = (struct pcctworeg *)(IIOV(ca->ca_paddr));
+ break;
+ default:
+ /* Bomb if wrong board */
+ return (0);
+ }
- if (badvaddr((vm_offset_t)pcc2, 4) <= 0){
- printf("==> pcctwo: failed address check.\n");
- return (0);
+ if (badvaddr((vm_offset_t)pcc2, 4)) {
+ printf("==> pcctwo: failed address check.\n");
+ return (0);
}
- if (pcc2->pcc2_chipid != PCC2_CHIPID){
- printf("==> pcctwo: wrong chip id %x.\n", pcc2->pcc2_chipid);
- return (0);
+ if (pcc2->pcc2_chipid != PCC2_CHIPID) {
+ printf("==> pcctwo: wrong chip id %x.\n", pcc2->pcc2_chipid);
+ return (0);
}
return (1);
}
@@ -175,14 +179,27 @@ pcctwoattach(parent, self, args)
*/
sc->sc_paddr = ca->ca_paddr;
sc->sc_vaddr = (void *)IIOV(sc->sc_paddr);
- switch (cputyp) {
- case CPU_187:
- sc->sc_pcc2 = (struct pcctworeg *)(sc->sc_vaddr + PCC2_PCC2CHIP_OFF);
- break;
- case CPU_197: /* pcctwo is a child of buswitch XXX smurph */
- sc->sc_pcc2 = (struct pcctworeg *)sc->sc_vaddr;
- break;
- }
+
+ pcc2bus = ca->ca_bustype;
+
+ switch (pcc2bus) {
+ case BUS_MAIN:
+ sc->sc_pcc2 = (struct pcctworeg *)(sc->sc_vaddr + PCC2_PCC2CHIP_OFF);
+ break;
+#if NBUSSW > 0
+ case BUS_BUSSWITCH:
+ sc->sc_pcc2 = (struct pcctworeg *)sc->sc_vaddr;
+ /*
+ * fake up our address so that pcc2 child devices
+ * are offeset of 0xFFF00000 - XXX smurph
+ */
+ sc->sc_paddr -= PCC2_PCC2CHIP_OFF;
+ sc->sc_vaddr -= PCC2_PCC2CHIP_OFF;
+ /* make sure the bus is mc68040 compatible */
+ sc->sc_pcc2->pcc2_genctl |= PCC2_GENCTL_C040;
+ break;
+#endif
+ }
sys_pcc2 = sc->sc_pcc2;
printf(": rev %d\n", sc->sc_pcc2->pcc2_chiprev);
@@ -193,8 +210,10 @@ pcctwoattach(parent, self, args)
/*
* Set pcc2intr_mask and pcc2intr_ipl.
*/
- pcc2intr_ipl = (u_char *)&(sc->sc_pcc2->pcc2_ipl);
- pcc2intr_mask = (u_char *)&(sc->sc_pcc2->pcc2_mask);
+#if 0
+ md.intr_mask = (u_char *)&(sc->sc_pcc2->pcc2_mask);
+ md.intr_ipl = (u_char *)&(sc->sc_pcc2->pcc2_ipl);
+#endif
config_search(pcctwo_scan, self, args);
}
diff --git a/sys/arch/mvme88k/dev/pcctwofunc.h b/sys/arch/mvme88k/dev/pcctwofunc.h
index dfb2a52cf2d..b41aad29b53 100644
--- a/sys/arch/mvme88k/dev/pcctwofunc.h
+++ b/sys/arch/mvme88k/dev/pcctwofunc.h
@@ -1,7 +1,7 @@
-/* $OpenBSD: pcctwofunc.h,v 1.1 2001/03/08 00:03:14 miod Exp $ */
+/* $OpenBSD: pcctwofunc.h,v 1.2 2001/12/13 08:55:51 smurph Exp $ */
-#ifndef _MVME88K_PCCTWO_H_
-#define _MVME88K_PCCTWO_H_
+#ifndef _MVME88K_PCCTWOF_H_
+#define _MVME88K_PCCTWOF_H_
int pcctwointr_establish __P((int vec, struct intrhand *ih));
diff --git a/sys/arch/mvme88k/dev/pcctworeg.h b/sys/arch/mvme88k/dev/pcctworeg.h
index 3a4cbbb1f2f..697a921b27a 100644
--- a/sys/arch/mvme88k/dev/pcctworeg.h
+++ b/sys/arch/mvme88k/dev/pcctworeg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pcctworeg.h,v 1.2 1998/12/15 05:52:30 smurph Exp $ */
+/* $OpenBSD: pcctworeg.h,v 1.3 2001/12/13 08:55:51 smurph Exp $ */
/*
* Memory map for PCC2 chip found in mvme1x7 boards.
@@ -55,6 +55,7 @@ struct pcctworeg {
volatile u_short pcc2_speed; /* DO NOT USE */
volatile u_short pcc2_prtdat;
volatile u_short :16;
+ /* The following regs are not valid on MVME197 */
volatile u_char pcc2_ipl;
volatile u_char pcc2_mask;
};
diff --git a/sys/arch/mvme88k/dev/sclock.c b/sys/arch/mvme88k/dev/sclock.c
index 1611102b33a..12936f62fc2 100644
--- a/sys/arch/mvme88k/dev/sclock.c
+++ b/sys/arch/mvme88k/dev/sclock.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: sclock.c,v 1.6 2001/08/26 02:37:07 miod Exp $ */
+/* $OpenBSD: sclock.c,v 1.7 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
*
@@ -191,7 +191,7 @@ sclockattach(parent, self, args)
sc->sc_statih.ih_ipl = ca->ca_ipl;
stat_reset = ca->ca_ipl | PCC2_IRQ_IEN | PCC2_IRQ_ICLR;
pcctwointr_establish(PCC2V_TIMER2, &sc->sc_statih);
- mdfp.statclock_init_func = &sbc_initstatclock;
+ md.statclock_init_func = &sbc_initstatclock;
printf(": VME1x7");
break;
#endif /* NPCCTWO */
@@ -202,7 +202,7 @@ sclockattach(parent, self, args)
sc->sc_statih.ih_wantframe = 1;
sc->sc_statih.ih_ipl = ca->ca_ipl;
sysconintr_establish(SYSCV_TIMER2, &sc->sc_statih);
- mdfp.statclock_init_func = &m188_initstatclock;
+ md.statclock_init_func = &m188_initstatclock;
printf(": VME188");
break;
#endif /* NSYSCON */
diff --git a/sys/arch/mvme88k/dev/sram.c b/sys/arch/mvme88k/dev/sram.c
index 5e8bc3b168b..7b36cbca3cc 100644
--- a/sys/arch/mvme88k/dev/sram.c
+++ b/sys/arch/mvme88k/dev/sram.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: sram.c,v 1.4 2001/11/06 19:53:15 miod Exp $ */
+/* $OpenBSD: sram.c,v 1.5 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1995 Theo de Raadt
@@ -72,7 +72,7 @@ srammatch(parent, vcf, args)
struct confargs *ca = args;
int ret;
- if (cputyp != CPU_187)
+ if (brdtyp != BRD_187) /* The only one... */
return (0);
ca->ca_paddr = (void *)0xffe00000;
@@ -101,20 +101,20 @@ sramattach(parent, self, args)
struct mcreg *mc;
int i;
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME167
- case CPU_167:
- case CPU_166:
+ case BRD_167:
+ case BRD_166:
sc->sc_len = 128*1024; /* always 128K */
break;
#endif
#ifdef MVME177
- case CPU_177:
+ case BRD_177:
sc->sc_len = 128*1024; /* always 128K */
break;
#endif
#ifdef MVME187
- case CPU_187:
+ case BRD_187:
sc->sc_len = 128*1024; /* always 128K */
break;
#endif
diff --git a/sys/arch/mvme88k/dev/ssh.c b/sys/arch/mvme88k/dev/ssh.c
index c89376326e6..0e39c96b16e 100644
--- a/sys/arch/mvme88k/dev/ssh.c
+++ b/sys/arch/mvme88k/dev/ssh.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: ssh.c,v 1.8 2001/11/06 19:53:15 miod Exp $ */
+/* $OpenBSD: ssh.c,v 1.9 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1994 Michael L. Hitch
@@ -55,7 +55,7 @@
#include <uvm/uvm_pmap.h>
#include <machine/autoconf.h>
-#include <machine/mmu.h>
+#include <machine/cmmu.h>
#include <machine/pmap.h>
#include <scsi/scsi_all.h>
diff --git a/sys/arch/mvme88k/dev/sshdma.c b/sys/arch/mvme88k/dev/sshdma.c
index 8a6b48604ee..a44cf025bad 100644
--- a/sys/arch/mvme88k/dev/sshdma.c
+++ b/sys/arch/mvme88k/dev/sshdma.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: sshdma.c,v 1.7 2001/11/06 19:53:15 miod Exp $ */
+/* $OpenBSD: sshdma.c,v 1.8 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
@@ -66,10 +66,10 @@
int afscmatch __P((struct device *, void *, void *));
void afscattach __P((struct device *, struct device *, void *));
-int afscprint __P((void *auxp, char *));
-int sshintr __P((struct ssh_softc *));
-int afsc_dmaintr __P((void *));
-void sshinitialize __P((struct ssh_softc *));
+int afscprint __P((void *auxp, char *));
+int sshintr __P((struct ssh_softc *));
+int afsc_dmaintr __P((void *));
+void sshinitialize __P((struct ssh_softc *));
struct scsi_adapter afsc_scsiswitch = {
ssh_scsicmd,
@@ -86,24 +86,22 @@ struct scsi_device afsc_scsidev = {
};
struct cfattach ssh_ca = {
- sizeof(struct ssh_softc), afscmatch, afscattach,
+ sizeof(struct ssh_softc), afscmatch, afscattach,
};
-
+
struct cfdriver ssh_cd = {
- NULL, "ssh", DV_DULL, 0
+ NULL, "ssh", DV_DULL, 0
};
int
afscmatch(pdp, vcf, args)
- struct device *pdp;
- void *vcf, *args;
+struct device *pdp;
+void *vcf, *args;
{
struct confargs *ca = args;
- int ret;
- if ((ret = badvaddr((vm_offset_t)IIOV(ca->ca_vaddr), 4)) <=0){
- printf("==> ssh: failed address check returning %ld.\n", ret);
- return(0);
+ if (badvaddr((vm_offset_t)IIOV(ca->ca_vaddr), 4)) {
+ return (0);
}
return (1);
@@ -111,8 +109,8 @@ afscmatch(pdp, vcf, args)
void
afscattach(parent, self, auxp)
- struct device *parent, *self;
- void *auxp;
+struct device *parent, *self;
+void *auxp;
{
struct ssh_softc *sc = (struct ssh_softc *)self;
struct confargs *ca = auxp;
@@ -128,14 +126,17 @@ afscattach(parent, self, auxp)
* XXX does the clock frequency change for the 33MHz processors?
*/
sc->sc_clock_freq = cpuspeed * 2;
- sc->sc_dcntl = SSH_DCNTL_EA;
+ sc->sc_dcntl = SSH_DCNTL_EA;
/*X*/ if (sc->sc_clock_freq <= 25)
/*X*/ sc->sc_dcntl |= (2 << 6);
-/*X*/ else if (sc->sc_clock_freq <= 37)
+/*X*/
+ else if (sc->sc_clock_freq <= 37)
/*X*/ sc->sc_dcntl |= (1 << 6);
-/*X*/ else if (sc->sc_clock_freq <= 50)
+/*X*/
+ else if (sc->sc_clock_freq <= 50)
/*X*/ sc->sc_dcntl |= (0 << 6);
-/*X*/ else
+/*X*/
+ else
/*X*/ sc->sc_dcntl |= (3 << 6);
sc->sc_ctest0 = SSH_CTEST0_BTD | SSH_CTEST0_EAN;
@@ -161,27 +162,25 @@ afscattach(parent, self, auxp)
switch (ca->ca_bustype) {
#if NPCCTWO > 0
case BUS_PCCTWO:
- {
- /*
- * Disable caching for the softc. Actually, I want
- * to disable cache for acb structures, but they are
- * part of softc, and I am disabling the entire softc
- * just in case.
- */
-
- struct pcctworeg *pcc2 = (struct pcctworeg *)ca->ca_master;
-
- pmap_cache_ctrl(pmap_kernel(), trunc_page((vm_offset_t)sc),
- round_page((vm_offset_t)sc + sizeof(*sc)),
- CACHE_INH);
-
- pcctwointr_establish(PCC2V_NCR, &sc->sc_ih);
-/* intr_establish(PCC2_VECT + SCSIIRQ, &sc->sc_ih);*/
- /* enable interrupts at ca_ipl */
- pcc2->pcc2_ncrirq = ca->ca_ipl | PCC2_IRQ_IEN;
-/* pcc2->pcc2_scsiirq = ca->ca_ipl | PCC2_SCSIIRQ_IEN;*/
- break;
- }
+ {
+ /*
+ * Disable caching for the softc. Actually, I want
+ * to disable cache for acb structures, but they are
+ * part of softc, and I am disabling the entire softc
+ * just in case.
+ */
+
+ struct pcctworeg *pcc2 = (struct pcctworeg *)ca->ca_master;
+
+ pmap_cache_ctrl(pmap_kernel(), trunc_page((vm_offset_t)sc),
+ round_page((vm_offset_t)sc + sizeof(*sc)),
+ CACHE_INH);
+
+ pcctwointr_establish(PCC2V_NCR, &sc->sc_ih);
+ /* enable interrupts at ca_ipl */
+ pcc2->pcc2_ncrirq = ca->ca_ipl | PCC2_IRQ_IEN;
+ break;
+ }
#endif
}
@@ -192,18 +191,18 @@ afscattach(parent, self, auxp)
* (see dk_establish).
*/
tmp = bootpart;
- if (ca->ca_paddr != bootaddr)
- bootpart = -1; /* invalid flag to dk_establish */
+ if (ca->ca_paddr != bootaddr)
+ bootpart = -1; /* invalid flag to dk_establish */
config_found(self, &sc->sc_link, scsiprint);
- bootpart = tmp; /* restore old value */
+ bootpart = tmp; /* restore old value */
}
/*
* print diag if pnp is NULL else just extra
*/
int
afscprint(auxp, pnp)
- void *auxp;
- char *pnp;
+void *auxp;
+char *pnp;
{
if (pnp == NULL)
return (UNCONF);
@@ -212,12 +211,12 @@ afscprint(auxp, pnp)
int
afsc_dmaintr(arg)
- void *arg;
+void *arg;
{
struct ssh_softc *sc = arg;
ssh_regmap_p rp;
- u_char istat;
+ u_char istat;
rp = sc->sc_sshp;
istat = rp->ssh_istat;
diff --git a/sys/arch/mvme88k/dev/syscon.c b/sys/arch/mvme88k/dev/syscon.c
index 8a00619e570..213d06d09e0 100644
--- a/sys/arch/mvme88k/dev/syscon.c
+++ b/sys/arch/mvme88k/dev/syscon.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: syscon.c,v 1.5 2001/03/09 05:44:39 smurph Exp $ */
+/* $OpenBSD: syscon.c,v 1.6 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* All rights reserved.
@@ -117,7 +117,7 @@ sysconmatch(parent, vcf, args)
struct sysconreg *syscon;
/* Don't match if wrong cpu */
- if (cputyp != CPU_188) return (0);
+ if (brdtyp != BRD_188) return (0); /* The only one... */
/* Uh, MVME188 better have on of these, so always match if it
* is a MVME188... */
syscon = (struct sysconreg *)(IIOV(ca->ca_paddr));
diff --git a/sys/arch/mvme88k/dev/vme.c b/sys/arch/mvme88k/dev/vme.c
index 3d797eb2919..967f6bafb11 100644
--- a/sys/arch/mvme88k/dev/vme.c
+++ b/sys/arch/mvme88k/dev/vme.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: vme.c,v 1.16 2001/11/07 22:31:57 miod Exp $ */
+/* $OpenBSD: vme.c,v 1.17 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* Copyright (c) 1995 Theo de Raadt
@@ -408,7 +408,6 @@ vme2chip_init(sc)
{
struct vme2reg *vme2 = (struct vme2reg *)sc->sc_vaddr;
u_long ctl;
-
/* turn off SYSFAIL LED */
vme2->vme2_tctl &= ~VME2_TCTL_SYSFAIL;
@@ -462,18 +461,18 @@ vme2chip_init(sc)
* Map the Software VME irq levels to the cpu level 7.
*/
vme2->vme2_irql3 = (7 << VME2_IRQL3_SW7SHIFT) | (7 << VME2_IRQL3_SW6SHIFT) |
- (7 << VME2_IRQL3_SW5SHIFT) | (7 << VME2_IRQL3_SW4SHIFT) |
- (7 << VME2_IRQL3_SW3SHIFT) | (7 << VME2_IRQL3_SW2SHIFT) |
- (7 << VME2_IRQL3_SW1SHIFT) | (7 << VME2_IRQL3_SW0SHIFT);
- /*
- * pseudo driver, abort interrupt handler
- */
- sc->sc_abih.ih_fn = vme2abort;
- sc->sc_abih.ih_arg = 0;
- sc->sc_abih.ih_wantframe = 1;
- sc->sc_abih.ih_ipl = IPL_NMI;
- intr_establish(110, &sc->sc_abih);
- vme2->vme2_irqen |= VME2_IRQ_AB;
+ (7 << VME2_IRQL3_SW5SHIFT) | (7 << VME2_IRQL3_SW4SHIFT) |
+ (7 << VME2_IRQL3_SW3SHIFT) | (7 << VME2_IRQL3_SW2SHIFT) |
+ (7 << VME2_IRQL3_SW1SHIFT) | (7 << VME2_IRQL3_SW0SHIFT);
+ /*
+ * pseudo driver, abort interrupt handler
+ */
+ sc->sc_abih.ih_fn = vme2abort;
+ sc->sc_abih.ih_arg = 0;
+ sc->sc_abih.ih_wantframe = 1;
+ sc->sc_abih.ih_ipl = IPL_NMI;
+ intr_establish(110, &sc->sc_abih);
+ vme2->vme2_irqen |= VME2_IRQ_AB;
vme2->vme2_irqen |= VME2_IRQ_ACF;
}
#endif /* NPCCTWO */
diff --git a/sys/arch/mvme88k/dev/vs.c b/sys/arch/mvme88k/dev/vs.c
index 0f5e21006a1..06ef4456540 100644
--- a/sys/arch/mvme88k/dev/vs.c
+++ b/sys/arch/mvme88k/dev/vs.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: vs.c,v 1.11 2001/11/06 00:30:38 art Exp $ */
+/* $OpenBSD: vs.c,v 1.12 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
@@ -56,6 +56,7 @@
#include <machine/autoconf.h>
#include <machine/param.h>
+#include <machine/cmmu.h>
#if defined(mvme88k)
#include <mvme88k/dev/vsreg.h>
diff --git a/sys/arch/mvme88k/dev/vsdma.c b/sys/arch/mvme88k/dev/vsdma.c
index e486117f1e1..dc36f93977b 100644
--- a/sys/arch/mvme88k/dev/vsdma.c
+++ b/sys/arch/mvme88k/dev/vsdma.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: vsdma.c,v 1.6 2001/03/27 01:16:25 miod Exp $ */
+/* $OpenBSD: vsdma.c,v 1.7 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* All rights reserved.
@@ -93,11 +93,9 @@ vsmatch(pdp, vcf, args)
void *vcf, *args;
{
struct confargs *ca = args;
- if (!badvaddr((unsigned)ca->ca_vaddr, 1)) {
- return (1);
- } else {
+ if (badvaddr((unsigned)ca->ca_vaddr, 1))
return (0);
- }
+ return (1);
}
void
diff --git a/sys/arch/mvme88k/dev/vx.c b/sys/arch/mvme88k/dev/vx.c
index 6fc4c3a4402..c93b92ab0c0 100644
--- a/sys/arch/mvme88k/dev/vx.c
+++ b/sys/arch/mvme88k/dev/vx.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: vx.c,v 1.12 2001/10/28 00:57:38 miod Exp $ */
+/* $OpenBSD: vx.c,v 1.13 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* All rights reserved.
@@ -197,8 +197,6 @@ vxmatch(parent, self, aux)
struct vxreg *vx_reg;
struct confargs *ca = aux;
- if (cputyp != CPU_187)
- return 0;
#ifdef OLD_MAPPINGS
ca->ca_vaddr = ca->ca_paddr;
#endif
@@ -207,15 +205,9 @@ vxmatch(parent, self, aux)
vx_reg = (struct vxreg *)ca->ca_vaddr;
board_addr = (unsigned int)ca->ca_vaddr;
- if (!badvaddr((unsigned)&vx_reg->ipc_cr, 1)) {
- if (ca->ca_vec & 0x03) {
- printf("xvt: bad vector 0x%x\n", ca->ca_vec);
- return (0);
- }
- return (1);
- } else {
+ if (badvaddr((unsigned)&vx_reg->ipc_cr, 1))
return (0);
- }
+ return (1);
}
void
diff --git a/sys/arch/mvme88k/include/asm.h b/sys/arch/mvme88k/include/asm.h
index 811acecee89..cb550dec00a 100644
--- a/sys/arch/mvme88k/include/asm.h
+++ b/sys/arch/mvme88k/include/asm.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: asm.h,v 1.16 2001/11/20 23:55:20 miod Exp $ */
+/* $OpenBSD: asm.h,v 1.17 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
@@ -36,6 +36,11 @@
#define _C_LABEL(name) _/**/name
#endif
+/* Define EH_DEBUG to be non-zero to compile-in various debugging things */
+#ifndef EH_DEBUG
+#define EH_DEBUG 0
+#endif EH_DEBUG
+
#define _ASM_LABEL(name) name
#define _ENTRY(name) \
@@ -209,6 +214,7 @@
#define FLAG_187 9 /* bit number 9 */
#define FLAG_188 10 /* bit number 10 */
#define FLAG_197 11 /* bit number 11 */
+#define FLAG_TBE 12 /* bit number 12 */
/* REGister OFFset into the E.F. (exception frame) */
#define REG_OFF(reg_num) ((reg_num) * 4) /* (num * sizeof(register int)) */
@@ -236,12 +242,21 @@
/*
* Info about the PSR
*/
-#define PSR_SHADOW_FREEZE_BIT 0
-#define PSR_INTERRUPT_DISABLE_BIT 1
-#define PSR_FPU_DISABLE_BIT 3
-#define PSR_BIG_ENDIAN_MODE 30
-#define PSR_SUPERVISOR_MODE_BIT 31
+#define PSR_SHADOW_FREEZE_BIT 0
+#define PSR_INTERRUPT_DISABLE_BIT 1
+#define PSR_FPU_DISABLE_BIT 3
+#define PSR_BIG_ENDIAN_MODE 30
+#define PSR_SUPERVISOR_MODE_BIT 31
+/*
+ * mc88110 PSR bit definitions (MVME197)
+ */
+#define PSR_GRAPHICS_DISABLE_BIT 4
+#define PSR_SERIAL_MODE_BIT 29
+#define PSR_CARRY_BIT 28
+#define PSR_SERIALIZE_BIT 25
+#define DSR_TBE 21
+#define DCTL_MEN 5
/*
* Status bits for an SXIP/SNIP/SFIP address.
*/
diff --git a/sys/arch/mvme88k/include/asm_macro.h b/sys/arch/mvme88k/include/asm_macro.h
index e6087420ef7..43921667f0d 100644
--- a/sys/arch/mvme88k/include/asm_macro.h
+++ b/sys/arch/mvme88k/include/asm_macro.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: asm_macro.h,v 1.16 2001/11/20 23:55:20 miod Exp $ */
+/* $OpenBSD: asm_macro.h,v 1.17 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -89,6 +89,16 @@ static __inline__ void set_psr(m88k_psr_type psr)
}
/*
+ * Gets the PSR. See comments above.
+ */
+static __inline__ m88k_psr_type get_psr(void)
+{
+ m88k_psr_type psr;
+ __asm__ __volatile__ ("ldcr %0, cr1" : "=r" (psr));
+ return psr;
+}
+
+/*
* Enables interrupts.
*/
static __inline__ m88k_psr_type enable_interrupts_return_psr(void)
diff --git a/sys/arch/mvme88k/include/board.h b/sys/arch/mvme88k/include/board.h
index f0f55c4039d..024c84ec304 100644
--- a/sys/arch/mvme88k/include/board.h
+++ b/sys/arch/mvme88k/include/board.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: board.h,v 1.11 2001/08/26 14:31:07 miod Exp $ */
+/* $OpenBSD: board.h,v 1.12 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
* All rights reserved.
@@ -108,13 +108,20 @@
#define FPUP_BIT 0x400 /* FPU precise exception */
#define FPUI_BIT 0x800 /* FPU imprecise exception */
+/* machine dependant definitions */
+
#if defined(MVME187) || defined(MVME197)
#include <machine/mvme1x7.h>
#endif
-
+#ifdef MVME187
+#include <machine/mvme187.h>
+#endif
#ifdef MVME188
#include <machine/mvme188.h>
#endif
+#ifdef MVME197
+#include <machine/mvme197.h>
+#endif
#endif /* __MACHINE_BOARD_H__ */
diff --git a/sys/arch/mvme88k/include/cmmu.h b/sys/arch/mvme88k/include/cmmu.h
index 37f6081b1ab..c12e8c16527 100644
--- a/sys/arch/mvme88k/include/cmmu.h
+++ b/sys/arch/mvme88k/include/cmmu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cmmu.h,v 1.6 2001/11/27 05:36:40 miod Exp $ */
+/* $OpenBSD: cmmu.h,v 1.7 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1992 Carnegie Mellon University
@@ -28,6 +28,8 @@
#ifndef _MACHINE_CMMU_H_
#define _MACHINE_CMMU_H_
+#include <machine/mmu.h>
+
/* Area Description */
#define AREA_D_WT 0x00000200 /* write through */
#define AREA_D_G 0x00000080 /* global */
@@ -58,70 +60,110 @@ extern unsigned cpu_sets[MAX_CPUS];
extern int cpu_cmmu_ratio;
extern unsigned number_cpus, master_cpu;
extern unsigned cache_policy;
-extern int max_cpus, max_cmmus;
-
-#ifdef CMMU_DEBUG
-void show_apr(unsigned value);
-void show_sctr(unsigned value);
-#endif
-
-#ifdef DDB
-void cmmu_show_translation(unsigned, unsigned, unsigned, int);
-void cmmu_cache_state(unsigned, unsigned);
-void show_cmmu_info(unsigned);
-#endif
+extern unsigned number_cpus;
+extern unsigned master_cpu;
+extern int max_cpus, max_cmmus;
-/*
- * Prototypes from "mvme88k/mvme88k/cmmu.c"
+/*
+ * This lock protects the cmmu SAR and SCR's; other ports
+ * can be accessed without locking it
+ *
+ * May be used from "db_interface.c".
*/
-
-unsigned cmmu_cpu_number(void);
-unsigned cmmu_remote_get(unsigned cpu, unsigned r, unsigned data);
-unsigned cmmu_get_idr(unsigned data);
-void cmmu_init(void);
-void cmmu_shutdown_now(void);
-void cmmu_parity_enable(void);
-void setup_board_config(void);
-void setup_cmmu_config(void);
-void cmmu_dump_config(void);
-unsigned cmmu_get_by_mode(int cpu, int mode);
-void cpu_configuration_print(int master);
-void dma_cachectl(vm_offset_t va, int size, int op);
-void cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x);
-void cmmu_set_sapr(unsigned ap);
-void cmmu_remote_set_sapr(unsigned cpu, unsigned ap);
-void cmmu_set_uapr(unsigned ap);
-void cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size);
-void cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size);
-void cmmu_flush_cache(vm_offset_t physaddr, int size);
-void cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size);
-void cmmu_flush_inst_cache(vm_offset_t physaddr, int size);
-void cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size);
-void cmmu_flush_data_cache(vm_offset_t physaddr, int size);
-
-void cmmu_pmap_activate(
- unsigned cpu,
- unsigned uapr,
- batc_template_t i_batc[BATC_MAX],
- batc_template_t d_batc[BATC_MAX]);
-
-void cmmu_flush_remote_tlb(
- unsigned cpu,
- unsigned kernel,
- vm_offset_t vaddr,
- int size);
-
-void cmmu_set_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned data, /* 1 = data, 0 = instruction */
- unsigned value); /* the value to stuff into the batc */
-
-void cmmu_set_pair_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned value); /* the value to stuff into the batc */
+extern struct simplelock cmmu_cpu_lock;
+
+#define CMMU_LOCK simple_lock(&cmmu_cpu_lock)
+#define CMMU_UNLOCK simple_unlock(&cmmu_cpu_lock)
+
+/* machine dependant cmmu function pointer structure */
+struct cmmu_p {
+ void (*cmmu_init_func) __P((void));
+ void (*show_apr_func) __P((unsigned));
+ void (*setup_board_config_func) __P((void));
+ void (*setup_cmmu_config_func) __P((void));
+ void (*cmmu_dump_config_func) __P((void));
+ void (*cpu_configuration_print_func) __P((int));
+ void (*cmmu_shutdown_now_func) __P((void));
+ void (*cmmu_parity_enable_func) __P((void));
+ unsigned (*cmmu_cpu_number_func) __P((void));
+ void (*cmmu_remote_set_func) __P((unsigned, unsigned, unsigned, unsigned));
+ unsigned (*cmmu_remote_get_func) __P((unsigned, unsigned, unsigned));
+ unsigned (*cmmu_get_idr_func) __P((unsigned));
+ void (*cmmu_set_sapr_func) __P((unsigned));
+ void (*cmmu_remote_set_sapr_func) __P((unsigned, unsigned));
+ void (*cmmu_set_uapr_func) __P((unsigned));
+ void (*cmmu_set_batc_entry_func) __P((unsigned, unsigned, unsigned, unsigned));
+ void (*cmmu_set_pair_batc_entry_func) __P((unsigned, unsigned, unsigned));
+ void (*cmmu_flush_remote_tlb_func) __P((unsigned, unsigned, vm_offset_t, int));
+ void (*cmmu_flush_tlb_func) __P((unsigned, vm_offset_t, int));
+ void (*cmmu_pmap_activate_func) __P((unsigned, unsigned,
+ batc_template_t i_batc[BATC_MAX],
+ batc_template_t d_batc[BATC_MAX]));
+ void (*cmmu_flush_remote_cache_func) __P((int, vm_offset_t, int));
+ void (*cmmu_flush_cache_func) __P((vm_offset_t, int));
+ void (*cmmu_flush_remote_inst_cache_func) __P((int, vm_offset_t, int));
+ void (*cmmu_flush_inst_cache_func) __P((vm_offset_t, int));
+ void (*cmmu_flush_remote_data_cache_func) __P((int, vm_offset_t, int));
+ void (*cmmu_flush_data_cache_func) __P((vm_offset_t, int));
+ void (*dma_cachectl_func) __P((vm_offset_t, int, int));
+#ifdef DDB
+ unsigned (*cmmu_get_by_mode_func) __P((int, int));
+ void (*cmmu_show_translation_func) __P((unsigned, unsigned, unsigned, int));
+ void (*cmmu_cache_state_func) __P((unsigned, unsigned));
+ void (*show_cmmu_info_func) __P((unsigned));
+#endif /* end if DDB */
+};
+
+/* THE pointer! */
+extern struct cmmu_p *cmmu;
+
+extern struct cmmu_p cmmu88110;
+extern struct cmmu_p cmmu8820x;
+
+/* The macros... */
+#define cmmu_init (cmmu->cmmu_init_func)
+#define show_apr(ap) (cmmu->show_apr_func)(ap)
+#define setup_board_config (cmmu->setup_board_config_func)
+#define setup_cmmu_config (cmmu->setup_cmmu_config_func)
+#define cmmu_dump_config (cmmu->cmmu_dump_config_func)
+#define cpu_configuration_print(a) (cmmu->cpu_configuration_print_func)(a)
+#define cmmu_shutdown_now (cmmu->cmmu_shutdown_now_func)
+#define cmmu_parity_enable (cmmu->cmmu_parity_enable_func)
+#define cmmu_cpu_number (cmmu->cmmu_cpu_number_func)
+#define cmmu_remote_set(a, b, c, d) (cmmu->cmmu_remote_set_func)(a, b, c, d)
+#define cmmu_remote_get(a, b, c) (cmmu->cmmu_remote_get_func)(a, b, c)
+#define cmmu_get_idr(a) (cmmu->cmmu_get_idr_func)(a)
+#define cmmu_set_sapr(a) (cmmu->cmmu_set_sapr_func)(a)
+#define cmmu_remote_set_sapr(a, b) (cmmu->cmmu_remote_set_sapr_func)(a, b)
+#define cmmu_set_uapr(a) (cmmu->cmmu_set_uapr_func)(a)
+#define cmmu_set_batc_entry(a, b, c, d) (cmmu->cmmu_set_batc_entry_func)(a, b, c, d)
+#define cmmu_set_pair_batc_entry(a, b, c) (cmmu->cmmu_set_pair_batc_entry_func)(a, b, c)
+#define cmmu_flush_remote_tlb(a, b, c, d) (cmmu->cmmu_flush_remote_tlb_func)(a, b, c, d)
+#define cmmu_flush_tlb(a, b, c) (cmmu->cmmu_flush_tlb_func)(a, b, c)
+#define cmmu_pmap_activate(a, b, c, d) (cmmu->cmmu_pmap_activate_func)(a, b, c, d)
+#define cmmu_flush_remote_cache(a, b, c) (cmmu->cmmu_flush_remote_cache_func)(a, b, c)
+#define cmmu_flush_cache(a, b) (cmmu->cmmu_flush_cache_func)(a, b)
+#define cmmu_flush_remote_inst_cache(a, b, c) (cmmu->cmmu_flush_remote_inst_cache_func)(a, b, c)
+#define cmmu_flush_inst_cache(a, b) (cmmu->cmmu_flush_inst_cache_func)(a, b)
+#define cmmu_flush_remote_data_cache(a, b, c) (cmmu->cmmu_flush_remote_data_cache_func)(a, b, c)
+#define cmmu_flush_data_cache(a, b) (cmmu->cmmu_flush_data_cache_func)(a, b)
+#define dma_cachectl(a, b, c) (cmmu->dma_cachectl_func)(a, b, c)
+#ifdef DDB
+#define cmmu_get_by_mode(a, b) (cmmu->cmmu_get_by_mode_func)(a, b)
+#define cmmu_show_translation(a, b, c, d) (cmmu->cmmu_show_translation_func)(a, b, c, d)
+#define cmmu_cache_state(a, b) (cmmu->cmmu_cache_state_func)(a, b)
+#define show_cmmu_info(a) (cmmu->show_cmmu_info_func)(a)
+#endif /* end if DDB */
#endif /* _LOCORE */
+#ifdef M88100
+#include <machine/m8820x.h>
+#endif /* M88100 */
+#ifdef M88110
+#include <machine/m88110.h>
+#include <machine/m88410.h>
+#endif /* M88110 */
+
#endif /* _MACHINE_CMMU_H_ */
+
diff --git a/sys/arch/mvme88k/include/cpu.h b/sys/arch/mvme88k/include/cpu.h
index 00a24f92194..333ed474c1b 100644
--- a/sys/arch/mvme88k/include/cpu.h
+++ b/sys/arch/mvme88k/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.13 2001/11/08 23:57:37 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.14 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
* Copyright (c) 1992, 1993
@@ -184,18 +184,23 @@ struct switchframe {
void *sf_proc; /* proc pointer */
};
-/* This struct defines the machine dependant function pointers */
-
-struct funcp {
+/* This struct defines the machine dependant pointers */
+struct md_p {
void (*clock_init_func) __P((void)); /* interval clock init function */
void (*statclock_init_func) __P((void)); /* statistics clock init function */
void (*delayclock_init_func) __P((void)); /* delay clock init function */
void (*delay_func) __P((void)); /* delay clock function */
- void (*interrupt_func) __P((u_int, struct m88100_saved_state *)); /* interrupt func */
- void (*fp_precise_func) __P((void)); /* floating point precise function */
+ void (*interrupt_func) __P((u_int, struct m88100_saved_state *)); /* interrupt func */
+ void (*fp_precise_func) __P((void)); /* floating point precise function */
+ void (*trap_func) __P((unsigned, struct m88100_saved_state *));
+ void (*syscall_func) __P((register_t, struct m88100_saved_state *));
+ volatile u_char *intr_mask;
+ volatile u_char *intr_ipl;
+ volatile u_char *intr_src;
};
-extern struct funcp mdfp;
+extern struct md_p md;
+
int badvaddr __P((vm_offset_t va, int size));
void nmihand __P((void *framep));
diff --git a/sys/arch/mvme88k/include/cpu_number.h b/sys/arch/mvme88k/include/cpu_number.h
index 6069dcaba1d..410e2614592 100644
--- a/sys/arch/mvme88k/include/cpu_number.h
+++ b/sys/arch/mvme88k/include/cpu_number.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu_number.h,v 1.6 2001/08/26 14:31:07 miod Exp $ */
+/* $OpenBSD: cpu_number.h,v 1.7 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
@@ -39,8 +39,7 @@ static unsigned cpu_number __P((void));
static __inline__ unsigned cpu_number(void)
{
register unsigned cpu;
-
- if (cputyp != CPU_188 || number_cpus == 1) return 0;
+ if (brdtyp != BRD_188 || number_cpus == 1) return 0;
__asm__ ("ldcr %0, cr18" : "=r" (cpu));
return (cpu & 3);
}
diff --git a/sys/arch/mvme88k/include/db_machdep.h b/sys/arch/mvme88k/include/db_machdep.h
index 2bcfa2410d8..aa6ba3669fd 100644
--- a/sys/arch/mvme88k/include/db_machdep.h
+++ b/sys/arch/mvme88k/include/db_machdep.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: db_machdep.h,v 1.16 2001/11/27 05:35:36 miod Exp $ */
+/* $OpenBSD: db_machdep.h,v 1.17 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -49,7 +49,8 @@
#include <uvm/uvm_param.h>
-#define BKPT_SIZE (4) /* number of bytes in bkpt inst. */
+#define INTERNAL_SSTEP /* Use local Single Step routines */
+#define BKPT_SIZE (4) /* number of bytes in bkpt inst. */
#define BKPT_INST (0xF000D000 | DDB_ENTRY_BKPT_NO) /* tb0, 0,r0, vector 130 */
#define BKPT_SET(inst) (BKPT_INST)
@@ -71,7 +72,9 @@ extern db_regs_t ddb_regs; /* register state */
({ \
int ret; \
\
- if (regs->sxip & 2) /* is valid */ \
+ if (cputyp == CPU_88110) \
+ ret = regs->sxip & ~3; \
+ else if (regs->sxip & 2) /* is valid */ \
ret = regs->sxip & ~3; \
else if (regs->snip & 2) \
ret = regs->snip & ~3; \
@@ -85,12 +88,15 @@ extern db_regs_t ddb_regs; /* register state */
* This is an actual function due to the fact that the sxip
* or snip could be nooped out due to a jmp or rte
*/
-#define PC_REGS(regs) ((regs->sxip & 2) ? regs->sxip & ~3 : \
+#define PC_REGS(regs) cputyp == CPU_88110 ? (regs->exip & ~3) :\
+ ((regs->sxip & 2) ? regs->sxip & ~3 : \
(regs->snip & 2 ? regs->snip & ~3 : regs->sfip & ~3))
-#define l_PC_REGS(regs) ((regs->sxip & 2) ? regs->sxip : \
+#define l_PC_REGS(regs) cputyp == CPU_88110 ? (regs->exip & ~3) :\
+ ((regs->sxip & 2) ? regs->sxip : \
(regs->snip & 2 ? regs->snip : regs->sfip ))
-#define pC_REGS(regs) (regs->sxip & 2) ? regs->sxip : (regs->snip & 2 ? \
+#define pC_REGS(regs) cputyp == CPU_88110 ? (regs->exip & ~3) :\
+ (regs->sxip & 2) ? regs->sxip : (regs->snip & 2 ? \
regs->snip : regs->sfip)
extern int db_noisy;
#define NOISY(x) if (db_noisy) x
@@ -124,8 +130,14 @@ int ddb_entry_trap __P((int level, db_regs_t *eframe));
/* we don't want coff support */
#define DB_NO_COFF 1
+#ifdef INTERNAL_SSTEP
+extern register_t getreg_val __P((db_regs_t *, int));
+void db_set_single_step __P((register db_regs_t *));
+void db_clear_single_step __P((register db_regs_t *));
+#else
/* need software single step */
-#define SOFTWARE_SSTEP 1 /* we need this XXX nivas */
+#define SOFTWARE_SSTEP 1 /* we need this for mc88100 */
+#endif
/*
* Debugger can get to any address space
diff --git a/sys/arch/mvme88k/include/exception_vectors2.h b/sys/arch/mvme88k/include/exception_vectors2.h
index 77c11b41956..d3bef68b320 100644
--- a/sys/arch/mvme88k/include/exception_vectors2.h
+++ b/sys/arch/mvme88k/include/exception_vectors2.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: exception_vectors2.h,v 1.3 2001/08/12 12:03:02 heko Exp $ */
+/* $OpenBSD: exception_vectors2.h,v 1.4 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1991, 1992 Carnegie Mellon University
@@ -25,143 +25,145 @@
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
-/*#define M197_UNDEFINED PREDEFINED_BY_ROM*/
+/*#define M88110_UNDEFINED PREDEFINED_BY_ROM*/
#ifndef __MACHINE_EXECPTION_VECTORS2_H__
#define __MACHINE_EXECPTION_VECTORS2_H__
-#ifndef M197_M197_UNDEFINED
-#define M197_UNDEFINED _m197_unknown_handler
+#ifndef M88110_UNDEFINED
+#define M88110_UNDEFINED _m88110_unknown_handler
#endif
-/* vector 0x00 (#0) */ word _m197_reset_handler
-/* vector 0x01 (#1) */ word _m197_interrupt_handler
-/* vector 0x02 (#2) */ word _m197_instruction_access_handler
-/* vector 0x03 (#3) */ word _m197_data_exception_handler
-/* vector 0x04 (#4) */ word _m197_misaligned_handler
-/* vector 0x05 (#5) */ word _m197_unimplemented_handler
-/* vector 0x06 (#6) */ word _m197_privilege_handler
-/* vector 0x07 (#7) */ word _m197_bounds_handler
-/* vector 0x08 (#8) */ word _m197_divide_handler
-/* vector 0x09 (#9) */ word _m197_overflow_handler
-/* vector 0x0a (#10) */ word _m197_error_handler
-/* vector 0x0b (#11) */ word _m197_nonmaskable
-/* vector 0x0c (#12) */ word _m197_data_read_miss
-/* vector 0x0d (#13) */ word _m197_data_write_miss
-/* vector 0x0e (#14) */ word _m197_inst_atc_miss
-/* vector 0x0f (#15) */ word _m197_trace
-/* vector 0x10 (#16) */ word M197_UNDEFINED
-/* vector 0x11 (#17) */ word M197_UNDEFINED
-/* vector 0x12 (#18) */ word M197_UNDEFINED
-/* vector 0x13 (#19) */ word M197_UNDEFINED
-/* vector 0x14 (#20) */ word M197_UNDEFINED
-/* vector 0x15 (#21) */ word M197_UNDEFINED
-/* vector 0x16 (#22) */ word M197_UNDEFINED
-/* vector 0x17 (#23) */ word M197_UNDEFINED
-/* vector 0x18 (#24) */ word M197_UNDEFINED
-/* vector 0x19 (#25) */ word M197_UNDEFINED
-/* vector 0x1a (#26) */ word M197_UNDEFINED
-/* vector 0x1b (#27) */ word M197_UNDEFINED
-/* vector 0x1c (#28) */ word M197_UNDEFINED
-/* vector 0x1d (#29) */ word M197_UNDEFINED
-/* vector 0x1e (#30) */ word M197_UNDEFINED
-/* vector 0x1f (#31) */ word M197_UNDEFINED
-/* vector 0x20 (#32) */ word M197_UNDEFINED
-/* vector 0x21 (#33) */ word M197_UNDEFINED
-/* vector 0x22 (#34) */ word M197_UNDEFINED
-/* vector 0x23 (#35) */ word M197_UNDEFINED
-/* vector 0x24 (#36) */ word M197_UNDEFINED
-/* vector 0x25 (#37) */ word M197_UNDEFINED
-/* vector 0x26 (#38) */ word M197_UNDEFINED
-/* vector 0x27 (#39) */ word M197_UNDEFINED
-/* vector 0x28 (#40) */ word M197_UNDEFINED
-/* vector 0x29 (#41) */ word M197_UNDEFINED
-/* vector 0x2a (#42) */ word M197_UNDEFINED
-/* vector 0x2b (#43) */ word M197_UNDEFINED
-/* vector 0x2c (#44) */ word M197_UNDEFINED
-/* vector 0x2d (#45) */ word M197_UNDEFINED
-/* vector 0x2e (#46) */ word M197_UNDEFINED
-/* vector 0x2f (#47) */ word M197_UNDEFINED
-/* vector 0x30 (#48) */ word M197_UNDEFINED
-/* vector 0x31 (#49) */ word M197_UNDEFINED
-/* vector 0x32 (#50) */ word M197_UNDEFINED
-/* vector 0x33 (#51) */ word M197_UNDEFINED
-/* vector 0x34 (#52) */ word M197_UNDEFINED
-/* vector 0x35 (#53) */ word M197_UNDEFINED
-/* vector 0x36 (#54) */ word M197_UNDEFINED
-/* vector 0x37 (#55) */ word M197_UNDEFINED
-/* vector 0x38 (#56) */ word M197_UNDEFINED
-/* vector 0x39 (#57) */ word M197_UNDEFINED
-/* vector 0x3a (#58) */ word M197_UNDEFINED
-/* vector 0x3b (#59) */ word M197_UNDEFINED
-/* vector 0x3c (#60) */ word M197_UNDEFINED
-/* vector 0x3d (#61) */ word M197_UNDEFINED
-/* vector 0x3e (#62) */ word M197_UNDEFINED
-/* vector 0x3f (#63) */ word M197_UNDEFINED
-/* vector 0x40 (#64) */ word M197_UNDEFINED
-/* vector 0x41 (#65) */ word M197_UNDEFINED
-/* vector 0x42 (#66) */ word M197_UNDEFINED
-/* vector 0x43 (#67) */ word M197_UNDEFINED
-/* vector 0x44 (#68) */ word M197_UNDEFINED
-/* vector 0x45 (#69) */ word M197_UNDEFINED
-/* vector 0x46 (#70) */ word M197_UNDEFINED
-/* vector 0x47 (#71) */ word M197_UNDEFINED
-/* vector 0x48 (#72) */ word M197_UNDEFINED
-/* vector 0x49 (#73) */ word M197_UNDEFINED
-/* vector 0x4a (#74) */ word M197_UNDEFINED
-/* vector 0x4b (#75) */ word M197_UNDEFINED
-/* vector 0x4c (#76) */ word M197_UNDEFINED
-/* vector 0x4d (#77) */ word M197_UNDEFINED
-/* vector 0x4e (#78) */ word M197_UNDEFINED
-/* vector 0x4f (#79) */ word M197_UNDEFINED
-/* vector 0x50 (#80) */ word M197_UNDEFINED
-/* vector 0x51 (#81) */ word M197_UNDEFINED
-/* vector 0x52 (#82) */ word M197_UNDEFINED
-/* vector 0x53 (#83) */ word M197_UNDEFINED
-/* vector 0x54 (#84) */ word M197_UNDEFINED
-/* vector 0x55 (#85) */ word M197_UNDEFINED
-/* vector 0x56 (#86) */ word M197_UNDEFINED
-/* vector 0x57 (#87) */ word M197_UNDEFINED
-/* vector 0x58 (#88) */ word M197_UNDEFINED
-/* vector 0x59 (#89) */ word M197_UNDEFINED
-/* vector 0x5a (#90) */ word M197_UNDEFINED
-/* vector 0x5b (#91) */ word M197_UNDEFINED
-/* vector 0x5c (#92) */ word M197_UNDEFINED
-/* vector 0x5d (#93) */ word M197_UNDEFINED
-/* vector 0x5e (#94) */ word M197_UNDEFINED
-/* vector 0x5f (#95) */ word M197_UNDEFINED
-/* vector 0x60 (#96) */ word M197_UNDEFINED
-/* vector 0x61 (#97) */ word M197_UNDEFINED
-/* vector 0x62 (#98) */ word M197_UNDEFINED
-/* vector 0x63 (#99) */ word M197_UNDEFINED
-/* vector 0x64 (#100) */ word M197_UNDEFINED
-/* vector 0x65 (#101) */ word M197_UNDEFINED
-/* vector 0x66 (#102) */ word M197_UNDEFINED
-/* vector 0x67 (#103) */ word M197_UNDEFINED
-/* vector 0x68 (#104) */ word M197_UNDEFINED
-/* vector 0x69 (#105) */ word M197_UNDEFINED
-/* vector 0x6a (#106) */ word M197_UNDEFINED
-/* vector 0x6b (#107) */ word M197_UNDEFINED
-/* vector 0x6c (#108) */ word M197_UNDEFINED
-/* vector 0x6d (#109) */ word M197_UNDEFINED
-/* vector 0x6e (#110) */ word M197_UNDEFINED
-/* vector 0x6f (#111) */ word M197_UNDEFINED
-/* vector 0x70 (#112) */ word M197_UNDEFINED
-/* vector 0x71 (#113) */ word M197_UNDEFINED
-/* vector 0x72 (#114) */ word _m197_fp_precise_handler
-/* vector 0x73 (#115) */ word M197_UNDEFINED
-/* vector 0x74 (#116) */ word _m197_unimplemented_handler
-/* vector 0x75 (#117) */ word M197_UNDEFINED
-/* vector 0x76 (#118) */ word _m197_unimplemented_handler
-/* vector 0x77 (#119) */ word M197_UNDEFINED
-/* vector 0x78 (#120) */ word _m197_unimplemented_handler
-/* vector 0x79 (#121) */ word M197_UNDEFINED
-/* vector 0x7a (#122) */ word _m197_unimplemented_handler
-/* vector 0x7b (#123) */ word M197_UNDEFINED
-/* vector 0x7c (#124) */ word _m197_unimplemented_handler
-/* vector 0x7d (#125) */ word M197_UNDEFINED
-/* vector 0x7e (#126) */ word _m197_unimplemented_handler
-/* vector 0x7f (#127) */ word M197_UNDEFINED
-/* vector 0x80 (#128) */ word _m197_syscall_handler
-/* vector 0x81 (#129) */ word _m197_syscall_handler
-/* vector 0x82 (#130) */ word _m197_break
-/* vector 0x83 (#131) */ word _m197_trace
-/* vector 0x84 (#132) */ word _m197_entry
+
+/* vector 0x00 (#0) */ word _m88110_reset_handler
+/* vector 0x01 (#1) */ word _m88110_interrupt_handler
+/* vector 0x02 (#2) */ word _m88110_instruction_access_handler
+/* vector 0x03 (#3) */ word _m88110_data_exception_handler
+/* vector 0x04 (#4) */ word _m88110_misaligned_handler
+/* vector 0x05 (#5) */ word _m88110_unimplemented_handler
+/* vector 0x06 (#6) */ word _m88110_privilege_handler
+/* vector 0x07 (#7) */ word _m88110_bounds_handler
+/* vector 0x08 (#8) */ word _m88110_divide_handler
+/* vector 0x09 (#9) */ word _m88110_overflow_handler
+/* vector 0x0a (#10) */ word _m88110_error_handler
+/* vector 0x0b (#11) */ word _m88110_nonmaskable
+/* vector 0x0c (#12) */ word _m88110_data_read_miss
+/* vector 0x0d (#13) */ word _m88110_data_write_miss
+/* vector 0x0e (#14) */ word _m88110_inst_atc_miss
+/* vector 0x0f (#15) */ word _m88110_trace
+/* vector 0x10 (#16) */ word M88110_UNDEFINED
+/* vector 0x11 (#17) */ word M88110_UNDEFINED
+/* vector 0x12 (#18) */ word M88110_UNDEFINED
+/* vector 0x13 (#19) */ word M88110_UNDEFINED
+/* vector 0x14 (#20) */ word M88110_UNDEFINED
+/* vector 0x15 (#21) */ word M88110_UNDEFINED
+/* vector 0x16 (#22) */ word M88110_UNDEFINED
+/* vector 0x17 (#23) */ word M88110_UNDEFINED
+/* vector 0x18 (#24) */ word M88110_UNDEFINED
+/* vector 0x19 (#25) */ word M88110_UNDEFINED
+/* vector 0x1a (#26) */ word M88110_UNDEFINED
+/* vector 0x1b (#27) */ word M88110_UNDEFINED
+/* vector 0x1c (#28) */ word M88110_UNDEFINED
+/* vector 0x1d (#29) */ word M88110_UNDEFINED
+/* vector 0x1e (#30) */ word M88110_UNDEFINED
+/* vector 0x1f (#31) */ word M88110_UNDEFINED
+/* vector 0x20 (#32) */ word M88110_UNDEFINED
+/* vector 0x21 (#33) */ word M88110_UNDEFINED
+/* vector 0x22 (#34) */ word M88110_UNDEFINED
+/* vector 0x23 (#35) */ word M88110_UNDEFINED
+/* vector 0x24 (#36) */ word M88110_UNDEFINED
+/* vector 0x25 (#37) */ word M88110_UNDEFINED
+/* vector 0x26 (#38) */ word M88110_UNDEFINED
+/* vector 0x27 (#39) */ word M88110_UNDEFINED
+/* vector 0x28 (#40) */ word M88110_UNDEFINED
+/* vector 0x29 (#41) */ word M88110_UNDEFINED
+/* vector 0x2a (#42) */ word M88110_UNDEFINED
+/* vector 0x2b (#43) */ word M88110_UNDEFINED
+/* vector 0x2c (#44) */ word M88110_UNDEFINED
+/* vector 0x2d (#45) */ word M88110_UNDEFINED
+/* vector 0x2e (#46) */ word M88110_UNDEFINED
+/* vector 0x2f (#47) */ word M88110_UNDEFINED
+/* vector 0x30 (#48) */ word M88110_UNDEFINED
+/* vector 0x31 (#49) */ word M88110_UNDEFINED
+/* vector 0x32 (#50) */ word M88110_UNDEFINED
+/* vector 0x33 (#51) */ word M88110_UNDEFINED
+/* vector 0x34 (#52) */ word M88110_UNDEFINED
+/* vector 0x35 (#53) */ word M88110_UNDEFINED
+/* vector 0x36 (#54) */ word M88110_UNDEFINED
+/* vector 0x37 (#55) */ word M88110_UNDEFINED
+/* vector 0x38 (#56) */ word M88110_UNDEFINED
+/* vector 0x39 (#57) */ word M88110_UNDEFINED
+/* vector 0x3a (#58) */ word M88110_UNDEFINED
+/* vector 0x3b (#59) */ word M88110_UNDEFINED
+/* vector 0x3c (#60) */ word M88110_UNDEFINED
+/* vector 0x3d (#61) */ word M88110_UNDEFINED
+/* vector 0x3e (#62) */ word M88110_UNDEFINED
+/* vector 0x3f (#63) */ word M88110_UNDEFINED
+/* vector 0x40 (#64) */ word M88110_UNDEFINED
+/* vector 0x41 (#65) */ word M88110_UNDEFINED
+/* vector 0x42 (#66) */ word M88110_UNDEFINED
+/* vector 0x43 (#67) */ word M88110_UNDEFINED
+/* vector 0x44 (#68) */ word M88110_UNDEFINED
+/* vector 0x45 (#69) */ word M88110_UNDEFINED
+/* vector 0x46 (#70) */ word M88110_UNDEFINED
+/* vector 0x47 (#71) */ word M88110_UNDEFINED
+/* vector 0x48 (#72) */ word M88110_UNDEFINED
+/* vector 0x49 (#73) */ word M88110_UNDEFINED
+/* vector 0x4a (#74) */ word M88110_UNDEFINED
+/* vector 0x4b (#75) */ word M88110_UNDEFINED
+/* vector 0x4c (#76) */ word M88110_UNDEFINED
+/* vector 0x4d (#77) */ word M88110_UNDEFINED
+/* vector 0x4e (#78) */ word M88110_UNDEFINED
+/* vector 0x4f (#79) */ word M88110_UNDEFINED
+/* vector 0x50 (#80) */ word M88110_UNDEFINED
+/* vector 0x51 (#81) */ word M88110_UNDEFINED
+/* vector 0x52 (#82) */ word M88110_UNDEFINED
+/* vector 0x53 (#83) */ word M88110_UNDEFINED
+/* vector 0x54 (#84) */ word M88110_UNDEFINED
+/* vector 0x55 (#85) */ word M88110_UNDEFINED
+/* vector 0x56 (#86) */ word M88110_UNDEFINED
+/* vector 0x57 (#87) */ word M88110_UNDEFINED
+/* vector 0x58 (#88) */ word M88110_UNDEFINED
+/* vector 0x59 (#89) */ word M88110_UNDEFINED
+/* vector 0x5a (#90) */ word M88110_UNDEFINED
+/* vector 0x5b (#91) */ word M88110_UNDEFINED
+/* vector 0x5c (#92) */ word M88110_UNDEFINED
+/* vector 0x5d (#93) */ word M88110_UNDEFINED
+/* vector 0x5e (#94) */ word M88110_UNDEFINED
+/* vector 0x5f (#95) */ word M88110_UNDEFINED
+/* vector 0x60 (#96) */ word M88110_UNDEFINED
+/* vector 0x61 (#97) */ word M88110_UNDEFINED
+/* vector 0x62 (#98) */ word M88110_UNDEFINED
+/* vector 0x63 (#99) */ word M88110_UNDEFINED
+/* vector 0x64 (#100) */ word M88110_UNDEFINED
+/* vector 0x65 (#101) */ word M88110_UNDEFINED
+/* vector 0x66 (#102) */ word M88110_UNDEFINED
+/* vector 0x67 (#103) */ word M88110_UNDEFINED
+/* vector 0x68 (#104) */ word M88110_UNDEFINED
+/* vector 0x69 (#105) */ word M88110_UNDEFINED
+/* vector 0x6a (#106) */ word M88110_UNDEFINED
+/* vector 0x6b (#107) */ word M88110_UNDEFINED
+/* vector 0x6c (#108) */ word M88110_UNDEFINED
+/* vector 0x6d (#109) */ word M88110_UNDEFINED
+/* vector 0x6e (#110) */ word M88110_UNDEFINED
+/* vector 0x6f (#111) */ word M88110_UNDEFINED
+/* vector 0x70 (#112) */ word M88110_UNDEFINED
+/* vector 0x71 (#113) */ word M88110_UNDEFINED
+/* vector 0x72 (#114) */ word _m88110_fp_precise_handler
+/* vector 0x73 (#115) */ word M88110_UNDEFINED
+/* vector 0x74 (#116) */ word _m88110_unimplemented_handler
+/* vector 0x75 (#117) */ word M88110_UNDEFINED
+/* vector 0x76 (#118) */ word _m88110_unimplemented_handler
+/* vector 0x77 (#119) */ word M88110_UNDEFINED
+/* vector 0x78 (#120) */ word _m88110_unimplemented_handler
+/* vector 0x79 (#121) */ word M88110_UNDEFINED
+/* vector 0x7a (#122) */ word _m88110_unimplemented_handler
+/* vector 0x7b (#123) */ word M88110_UNDEFINED
+/* vector 0x7c (#124) */ word _m88110_unimplemented_handler
+/* vector 0x7d (#125) */ word M88110_UNDEFINED
+/* vector 0x7e (#126) */ word _m88110_unimplemented_handler
+/* vector 0x7f (#127) */ word M88110_UNDEFINED
+/* vector 0x80 (#128) */ word _m88110_syscall_handler
+/* vector 0x81 (#129) */ word _m88110_syscall_handler
+/* vector 0x82 (#130) */ word _m88110_break
+/* vector 0x83 (#131) */ word _m88110_trace
+/* vector 0x84 (#132) */ word _m88110_entry
#endif /* __MACHINE_EXECPTION_VECTORS2_H__ */
+
diff --git a/sys/arch/mvme88k/include/intr.h b/sys/arch/mvme88k/include/intr.h
index 940b2fc36e0..ca550ab6de9 100644
--- a/sys/arch/mvme88k/include/intr.h
+++ b/sys/arch/mvme88k/include/intr.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: intr.h,v 1.4 2001/11/21 19:04:52 miod Exp $ */
+/* $OpenBSD: intr.h,v 1.5 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (C) 2000 Steve Murphree, Jr.
* All rights reserved.
@@ -71,9 +71,8 @@ extern int intrcnt[M88K_NIRQ];
#define IPL_SOFTNET 1
#define IPL_BIO 2
#define IPL_NET 3
-#define IPL_IMP 3
#define IPL_TTY 3
-#define IPL_VM 3
+#define IPL_IMP 4
#define IPL_CLOCK 5
#define IPL_STATCLOCK 5
#define IPL_HIGH 6
@@ -114,7 +113,7 @@ above...
#define splclock() setipl(IPL_CLOCK)
#define splstatclock() setipl(IPL_STATCLOCK)
#define splimp() setipl(IPL_IMP)
-#define splvm() setipl(IPL_VM)
+#define splvm() setipl(IPL_IMP)
#define splhigh() setipl(IPL_HIGH)
#define splx(x) ((x) ? setipl((x)) : spl0())
diff --git a/sys/arch/mvme88k/include/locore.h b/sys/arch/mvme88k/include/locore.h
index 4e1888c13d5..1ac3656a9dc 100644
--- a/sys/arch/mvme88k/include/locore.h
+++ b/sys/arch/mvme88k/include/locore.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.h,v 1.11 2001/11/06 00:30:38 art Exp $ */
+/* $OpenBSD: locore.h,v 1.12 2001/12/13 08:55:51 smurph Exp $ */
#ifndef _MACHINE_LOCORE_H_
#define _MACHINE_LOCORE_H_
@@ -40,25 +40,16 @@ int db_are_interrupts_disabled __P((void));
void fubail __P((void));
void subail __P((void));
-#if defined(MVME187) || defined(MVME188)
int guarded_access __P((volatile unsigned char *address,
unsigned len, u_char *vec));
-#endif
-
/* locore_c_routines.c */
-#if defined(MVME187) || defined(MVME188)
+#ifdef M88100
void dae_print __P((unsigned *eframe));
void data_access_emulation __P((unsigned *eframe));
#endif
-#ifdef MVME188
-unsigned int safe_level __P((unsigned mask, unsigned curlevel));
-#if 0
-void block_obio_interrupt __P((unsigned mask));
-void unblock_obio_interrupt __P((unsigned mask));
-#endif
-#endif
+
unsigned spl __P((void));
unsigned getipl __P((void));
#ifdef DDB
@@ -80,32 +71,35 @@ void dosoftint __P((void));
void MY_info __P((struct trapframe *f, caddr_t p, int flags, char *s));
void MY_info_done __P((struct trapframe *f, int flags));
void mvme_bootstrap __P((void));
+#ifdef MVME187
+void m187_ext_int __P((u_int v, struct m88100_saved_state *eframe));
+#endif
#ifdef MVME188
void m188_reset __P((void));
void m188_ext_int __P((u_int v, struct m88100_saved_state *eframe));
+unsigned int safe_level __P((unsigned mask, unsigned curlevel));
#endif
-#if defined(MVME187) || defined(MVME197)
-void sbc_ext_int __P((u_int v, struct m88100_saved_state *eframe));
+#ifdef MVME197
+void m197_ext_int __P((u_int v, struct m88100_saved_state *eframe));
#endif
-
/* eh.S */
struct proc;
void proc_do_uret __P((struct proc *));
-#if defined(MVME187) || defined(MVME188)
+#ifdef M88100
void sigsys __P((void));
void sigtrap __P((void));
void stepbpt __P((void));
void userbpt __P((void));
void syscall_handler __P((void));
#endif
-#if defined(MVME197)
-void m197_sigsys __P((void));
-void m197_sigtrap __P((void));
-void m197_stepbpt __P((void));
-void m197_userbpt __P((void));
-void m197_syscall_handler __P((void));
+#ifdef M88110
+void m88110_sigsys __P((void));
+void m88110_sigtrap __P((void));
+void m88110_stepbpt __P((void));
+void m88110_userbpt __P((void));
+void m88110_syscall_handler __P((void));
#endif
/* process.S */
diff --git a/sys/arch/mvme88k/include/m88110.h b/sys/arch/mvme88k/include/m88110.h
index 285c339735d..fd02ec455fe 100644
--- a/sys/arch/mvme88k/include/m88110.h
+++ b/sys/arch/mvme88k/include/m88110.h
@@ -1,16 +1,13 @@
-/* $OpenBSD: m88110.h,v 1.7 2001/11/06 19:53:15 miod Exp $ */
+/* $OpenBSD: m88110.h,v 1.8 2001/12/13 08:55:51 smurph Exp $ */
#ifndef __MACHINE_M88110_H__
#define __MACHINE_M88110_H__
+#include <uvm/uvm_extern.h>
#ifndef _LOCORE
-# include <machine/mmu.h> /* batc_template_t */
+#include <machine/mmu.h> /* batc_template_t */
#endif
-#include <machine/board.h>
-#include <machine/cmmu.h>
-#include <uvm/uvm_extern.h>
-
/*
* 88110 CMMU definitions
*/
@@ -79,6 +76,11 @@
#define CMMU_DCMD_INV_SATC 0x00A /* Invalidate All Supervisor ATCs */
#define CMMU_DCMD_INV_UATC 0x00B /* Invalidate All User ATCs */
+#define CMMU_DCTL_RSVD7 0x40000 /* Reserved */
+#define CMMU_DCTL_RSVD6 0x20000 /* Reserved */
+#define CMMU_DCTL_RSVD5 0x10000 /* Reserved */
+#define CMMU_DCTL_RSVD4 0x8000 /* Reserved */
+#define CMMU_DCTL_RSVD3 0x4000 /* Reserved */
#define CMMU_DCTL_XMEM 0x2000 /* store -> load sequence */
#define CMMU_DCTL_DEN 0x1000 /* Decoupled Cache Access Enable */
#define CMMU_DCTL_FWT 0x0800 /* Force Write Through */
@@ -88,6 +90,9 @@
#define CMMU_DCTL_FRZ1 0x0080 /* Data Cache Freeze Bank 1 */
#define CMMU_DCTL_HTEN 0x0040 /* Hardware Table Search Enable */
#define CMMU_DCTL_MEN 0x0020 /* Data MMU Enable */
+#define CMMU_DCTL_RSVD2 0x0010 /* Reserved */
+#define CMMU_DCTL_ADS 0x0008 /* Allocat Disable */
+#define CMMU_DCTL_RSVD1 0x0004 /* Reserved */
#define CMMU_DCTL_SEN 0x0002 /* Data Cache Snoop Enable */
#define CMMU_DCTL_CEN 0x0001 /* Data Cache Enable */
@@ -110,126 +115,207 @@
#define CMMU_DATA 1
#define CMMU_INST 0
+/* definitions for use of the BATC */
+#define BATC_512K (0x00 << 19)
+#define BATC_1M (0x01 << 19)
+#define BATC_2M (0x03 << 19)
+#define BATC_4M (0x07 << 19)
+#define BATC_8M (0x0F << 19)
+#define BATC_16M (0x1F << 19)
+#define BATC_32M (0x3F << 19)
+#define BATC_64M (0x7F << 19)
+#define BATC_ADDR_MASK 0xFFF80000
+#define BATC_ADDR_SHIFT 13
+#define BATC_LBA_SHIFT 19
+#define BATC_PBA_SHIFT 6
+#define BATC_SU 0x20
+#define BATC_WT 0x10
+#define BATC_G 0x08
+#define BATC_CI 0x04
+#define BATC_WP 0x02
+#define BATC_V 0x01
+
+#define CLINE_MASK 0x1F
+#define CLINE_SIZE (8 * 32)
+
#ifndef _LOCORE
+
/*
- * Prototypes from "mvme88k/mvme88k/m197_cmmu.c"
+ * Prototypes from "mvme88k/mvme88k/m88110_cmmu.c"
*/
+void m88110_show_apr __P((unsigned));
+void m88110_show_sctr __P((unsigned));
+void m88110_setup_board_config __P((void));
+void m88110_setup_cmmu_config __P((void));
+void m88110_cmmu_dump_config __P((void));
+void m88110_cpu_configuration_print __P((int));
+void m88110_cmmu_shutdown_now __P((void));
+void m88110_cmmu_parity_enable __P((void));
+unsigned m88110_cmmu_cpu_number __P((void));
+void m88110_cmmu_remote_set __P((unsigned, unsigned, unsigned, unsigned));
+unsigned m88110_cmmu_remote_get __P((unsigned, unsigned, unsigned));
+unsigned m88110_cmmu_get_idr __P((unsigned));
+void m88110_cmmu_set_sapr __P((unsigned));
+void m88110_cmmu_remote_set_sapr __P((unsigned, unsigned));
+void m88110_cmmu_set_uapr __P((unsigned));
+void m88110_cmmu_set_batc_entry __P((unsigned, unsigned, unsigned, unsigned));
+void m88110_cmmu_set_pair_batc_entry __P((unsigned, unsigned, unsigned));
+void m88110_cmmu_flush_remote_tlb __P((unsigned, unsigned, vm_offset_t, int));
+void m88110_cmmu_flush_tlb __P((unsigned, vm_offset_t, int));
+void m88110_cmmu_pmap_activate __P((unsigned, unsigned,
+ batc_template_t i_batc[BATC_MAX],
+ batc_template_t d_batc[BATC_MAX]));
+void m88110_cmmu_flush_remote_cache __P((int, vm_offset_t, int));
+void m88110_cmmu_flush_cache __P((vm_offset_t, int));
+void m88110_cmmu_flush_remote_inst_cache __P((int, vm_offset_t, int));
+void m88110_cmmu_flush_inst_cache __P((vm_offset_t, int));
+void m88110_cmmu_flush_remote_data_cache __P((int, vm_offset_t, int));
+void m88110_cmmu_flush_data_cache __P((vm_offset_t, int));
+void m88110_dma_cachectl __P((vm_offset_t, int, int));
-#ifdef DDB
-void m197_cmmu_show_translation(unsigned, unsigned, unsigned, int);
-void m197_cmmu_cache_state(unsigned, unsigned);
-void m197_show_cmmu_info(unsigned);
-#endif
+#if DDB
+unsigned m88110_cmmu_get_by_mode __P((int, int));
+void m88110_cmmu_show_translation __P((unsigned, unsigned, unsigned, int));
+void m88110_cmmu_cache_state __P((unsigned, unsigned));
+void m88110_show_cmmu_info __P((unsigned));
+#endif
-#ifdef CMMU_DEBUG
-void m197_show_apr(unsigned value);
-void m197_show_sctr(unsigned value);
-#endif
+void m88110_cmmu_init __P((void));
+int m88110_table_search __P((pmap_t, vm_offset_t, int, int, int));
-unsigned m197_cmmu_cpu_number(void);
-unsigned m197_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data);
-unsigned m197_cmmu_get_idr(unsigned data);
-void m197_cmmu_init(void);
-void m197_cmmu_shutdown_now(void);
-void m197_cmmu_parity_enable(void);
-void m197_setup_board_config(void);
-void m197_setup_cmmu_config(void);
-void m197_cmmu_dump_config(void);
-unsigned m197_cmmu_get_by_mode(int cpu, int mode);
-void m197_cpu_configuration_print(int master);
-void m197_dma_cachectl(vm_offset_t va, int size, int op);
-void m197_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x);
-void m197_cmmu_set_sapr(unsigned ap);
-void m197_cmmu_remote_set_sapr(unsigned cpu, unsigned ap);
-void m197_cmmu_set_uapr(unsigned ap);
-void m197_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size);
-void m197_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size);
-void m197_cmmu_flush_cache(vm_offset_t physaddr, int size);
-void m197_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size);
-void m197_cmmu_flush_inst_cache(vm_offset_t physaddr, int size);
-void m197_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size);
-void m197_cmmu_flush_data_cache(vm_offset_t physaddr, int size);
-
-void m197_cmmu_pmap_activate(
- unsigned cpu,
- unsigned uapr,
- batc_template_t i_batc[BATC_MAX],
- batc_template_t d_batc[BATC_MAX]);
-
-void m197_cmmu_flush_remote_tlb(
- unsigned cpu,
- unsigned kernel,
- vm_offset_t vaddr,
- int size);
-
-void m197_cmmu_set_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned data, /* 1 = data, 0 = instruction */
- unsigned value); /* the value to stuff into the batc */
-
-void m197_cmmu_set_pair_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned value); /* the value to stuff into the batc */
-
-int m197_table_search(
- pmap_t map,
- vm_offset_t virt,
- int write,
- int user, int data);
-
-void set_icmd (unsigned value);
-void set_ictl (unsigned value);
-void set_isar (unsigned value);
-void set_isap (unsigned value);
-void set_iuap (unsigned value);
-void set_iir (unsigned value);
-void set_ibp (unsigned value);
-void set_ippu (unsigned value);
-void set_ippl (unsigned value);
-void set_isr (unsigned value);
-void set_ilar (unsigned value);
-void set_ipar (unsigned value);
-void set_dcmd (unsigned value);
-void set_dctl (unsigned value);
-void set_dsar (unsigned value);
-void set_dsap (unsigned value);
-void set_duap (unsigned value);
-void set_dir (unsigned value);
-void set_dbp (unsigned value);
-void set_dppu (unsigned value);
-void set_dppl (unsigned value);
-void set_dsr (unsigned value);
-void set_dlar (unsigned value);
-void set_dpar (unsigned value);
+void set_icmd __P((unsigned value));
+void set_ictl __P((unsigned value));
+void set_isar __P((unsigned value));
+void set_isap __P((unsigned value));
+void set_iuap __P((unsigned value));
+void set_iir __P((unsigned value));
+void set_ibp __P((unsigned value));
+void set_ippu __P((unsigned value));
+void set_ippl __P((unsigned value));
+void set_isr __P((unsigned value));
+void set_ilar __P((unsigned value));
+void set_ipar __P((unsigned value));
+void set_dcmd __P((unsigned value));
+void set_dctl __P((unsigned value));
+void set_dsar __P((unsigned value));
+void set_dsap __P((unsigned value));
+void set_duap __P((unsigned value));
+void set_dir __P((unsigned value));
+void set_dbp __P((unsigned value));
+void set_dppu __P((unsigned value));
+void set_dppl __P((unsigned value));
+void set_dsr __P((unsigned value));
+void set_dlar __P((unsigned value));
+void set_dpar __P((unsigned value));
/* get routines */
-unsigned get_icmd (void);
-unsigned get_ictl (void);
-unsigned get_isar (void);
-unsigned get_isap (void);
-unsigned get_iuap (void);
-unsigned get_iir (void);
-unsigned get_ibp (void);
-unsigned get_ippu (void);
-unsigned get_ippl (void);
-unsigned get_isr (void);
-unsigned get_ilar (void);
-unsigned get_ipar (void);
-unsigned get_dcmd (void);
-unsigned get_dctl (void);
-unsigned get_dsar (void);
-unsigned get_dsap (void);
-unsigned get_duap (void);
-unsigned get_dir (void);
-unsigned get_dbp (void);
-unsigned get_dppu (void);
-unsigned get_dppl (void);
-unsigned get_dsr (void);
-unsigned get_dlar (void);
-unsigned get_dpar (void);
+unsigned get_icmd __P((void));
+unsigned get_ictl __P((void));
+unsigned get_isar __P((void));
+unsigned get_isap __P((void));
+unsigned get_iuap __P((void));
+unsigned get_iir __P((void));
+unsigned get_ibp __P((void));
+unsigned get_ippu __P((void));
+unsigned get_ippl __P((void));
+unsigned get_isr __P((void));
+unsigned get_ilar __P((void));
+unsigned get_ipar __P((void));
+unsigned get_dcmd __P((void));
+unsigned get_dctl __P((void));
+unsigned get_dsar __P((void));
+unsigned get_dsap __P((void));
+unsigned get_duap __P((void));
+unsigned get_dir __P((void));
+unsigned get_dbp __P((void));
+unsigned get_dppu __P((void));
+unsigned get_dppl __P((void));
+unsigned get_dsr __P((void));
+unsigned get_dlar __P((void));
+unsigned get_dpar __P((void));
-#endif /* _LOCORE */
+/* Cache inlines */
+
+#define line_addr(x) (vm_offset_t)((x) & ~CLINE_MASK)
+#define page_addr(x) (vm_offset_t)((x) & ~PAGE_MASK)
+
+static __inline__ void mc88110_flush_data_line(vm_offset_t x)
+{
+ unsigned dctl = get_dctl();
+ if (dctl & CMMU_DCTL_CEN){
+ set_dsar(line_addr(x));
+ set_dcmd(CMMU_DCMD_FLUSH_LINE);
+ }
+}
+static __inline__ void mc88110_flush_data_page(vm_offset_t x)
+{
+ unsigned dctl = get_dctl();
+ if (dctl & CMMU_DCTL_CEN){
+ set_dsar(page_addr(x));
+ set_dcmd(CMMU_DCMD_FLUSH_PG);
+ }
+}
+
+static __inline__ void mc88110_flush_data(void)
+{
+ unsigned dctl = get_dctl();
+ if (dctl & CMMU_DCTL_CEN){
+ set_dsar(0x00);
+ set_dcmd(CMMU_DCMD_FLUSH_ALL);
+ }
+}
+
+static __inline__ void mc88110_inval_data_line(vm_offset_t x)
+{
+ set_dsar(line_addr(x));
+ set_dcmd(CMMU_DCMD_INV_LINE);
+}
+
+static __inline__ void mc88110_inval_data(void)
+{
+ set_dsar(0x00);
+ set_dcmd(CMMU_DCMD_INV_ALL);
+}
+
+static __inline__ void mc88110_sync_data_line(vm_offset_t x)
+{
+ unsigned dctl = get_dctl();
+ if (dctl & CMMU_DCTL_CEN){
+ set_dsar(line_addr(x));
+ set_dcmd(CMMU_DCMD_FLUSH_LINE_INV);
+ }
+}
+
+static __inline__ void mc88110_sync_data_page(vm_offset_t x)
+{
+ unsigned dctl = get_dctl();
+ if (dctl & CMMU_DCTL_CEN){
+ set_dsar(page_addr(x));
+ set_dcmd(CMMU_DCMD_FLUSH_PG_INV);
+ }
+}
+
+static __inline__ void mc88110_sync_data(void)
+{
+ unsigned dctl = get_dctl();
+ if (dctl & CMMU_DCTL_CEN){
+ set_dsar(0x00);
+ set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
+ }
+}
+
+static __inline__ void mc88110_inval_inst_line(vm_offset_t x)
+{
+ set_isar(line_addr(x));
+ set_icmd(CMMU_ICMD_INV_LINE);
+}
+
+static __inline__ void mc88110_inval_inst(void)
+{
+ set_isar(0x00);
+ set_icmd(CMMU_ICMD_INV_ITIC);
+}
+
+#endif /* _LOCORE */
#endif /* __MACHINE_M88110_H__ */
diff --git a/sys/arch/mvme88k/include/m882xx.h b/sys/arch/mvme88k/include/m8820x.h
index 0bfc832e338..d69c807fb7a 100644
--- a/sys/arch/mvme88k/include/m882xx.h
+++ b/sys/arch/mvme88k/include/m8820x.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: m882xx.h,v 1.8 2001/08/26 14:31:07 miod Exp $ */
+/* $OpenBSD: m8820x.h,v 1.1 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1992 Carnegie Mellon University
@@ -30,15 +30,8 @@
*/
-#ifndef __MACHINE_M882XX_H__
-#define __MACHINE_M882XX_H__
-
-#ifndef _LOCORE
-# include <machine/mmu.h> /* batc_template_t */
-#endif
-
-#include <machine/board.h>
-#include <machine/cmmu.h>
+#ifndef __MACHINE_M8820X_H__
+#define __MACHINE_M8820X_H__
/*
* 88200 CMMU definitions
@@ -133,65 +126,45 @@
#ifndef _LOCORE
/*
- * Prototypes from "mvme88k/mvme88k/m18x_cmmu.c"
+ * Prototypes from "mvme88k/mvme88k/m8820x.c"
*/
-#ifdef DDB
-void m18x_cmmu_show_translation(unsigned, unsigned, unsigned, int);
-void m18x_cmmu_cache_state(unsigned, unsigned);
-void m18x_show_cmmu_info(unsigned);
+void m8820x_show_apr __P((unsigned));
+void m8820x_setup_board_config __P((void));
+void m8820x_setup_cmmu_config __P((void));
+void m8820x_cmmu_dump_config __P((void));
+void m8820x_cpu_configuration_print __P((int));
+void m8820x_cmmu_shutdown_now __P((void));
+void m8820x_cmmu_parity_enable __P((void));
+unsigned m8820x_cmmu_cpu_number __P((void));
+void m8820x_cmmu_remote_set __P((unsigned, unsigned, unsigned, unsigned));
+unsigned m8820x_cmmu_remote_get __P((unsigned, unsigned, unsigned));
+unsigned m8820x_cmmu_get_idr __P((unsigned));
+void m8820x_cmmu_set_sapr __P((unsigned));
+void m8820x_cmmu_remote_set_sapr __P((unsigned, unsigned));
+void m8820x_cmmu_set_uapr __P((unsigned));
+void m8820x_cmmu_set_batc_entry __P((unsigned, unsigned, unsigned, unsigned));
+void m8820x_cmmu_set_pair_batc_entry __P((unsigned, unsigned, unsigned));
+void m8820x_cmmu_flush_remote_tlb __P((unsigned, unsigned, vm_offset_t, int));
+void m8820x_cmmu_flush_tlb __P((unsigned, vm_offset_t, int));
+void m8820x_cmmu_pmap_activate __P((unsigned, unsigned,
+ batc_template_t i_batc[BATC_MAX],
+ batc_template_t d_batc[BATC_MAX]));
+void m8820x_cmmu_flush_remote_cache __P((int, vm_offset_t, int));
+void m8820x_cmmu_flush_cache __P((vm_offset_t, int));
+void m8820x_cmmu_flush_remote_inst_cache __P((int, vm_offset_t, int));
+void m8820x_cmmu_flush_inst_cache __P((vm_offset_t, int));
+void m8820x_cmmu_flush_remote_data_cache __P((int, vm_offset_t, int));
+void m8820x_cmmu_flush_data_cache __P((vm_offset_t, int));
+void m8820x_dma_cachectl __P((vm_offset_t, int, int));
+
+#if DDB
+unsigned m8820x_cmmu_get_by_mode __P((int, int));
+void m8820x_cmmu_show_translation __P((unsigned, unsigned, unsigned, int));
+void m8820x_cmmu_cache_state __P((unsigned, unsigned));
+void m8820x_show_cmmu_info __P((unsigned));
#endif
-#ifdef CMMU_DEBUG
-void m18x_show_apr(unsigned value);
-void m18x_show_sctr(unsigned value);
-#endif
-
-unsigned m18x_cmmu_cpu_number(void);
-unsigned m18x_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data);
-unsigned m18x_cmmu_get_idr(unsigned data);
-void m18x_cmmu_init(void);
-void m18x_cmmu_shutdown_now(void);
-void m18x_cmmu_parity_enable(void);
-void m18x_setup_board_config(void);
-void m18x_setup_cmmu_config(void);
-void m18x_cmmu_dump_config(void);
-unsigned m18x_cmmu_get_by_mode(int cpu, int mode);
-void m18x_cpu_configuration_print(int master);
-void m18x_dma_cachectl(vm_offset_t va, int size, int op);
-void m18x_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x);
-void m18x_cmmu_set_sapr(unsigned ap);
-void m18x_cmmu_remote_set_sapr(unsigned cpu, unsigned ap);
-void m18x_cmmu_set_uapr(unsigned ap);
-void m18x_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size);
-void m18x_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size);
-void m18x_cmmu_flush_cache(vm_offset_t physaddr, int size);
-void m18x_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size);
-void m18x_cmmu_flush_inst_cache(vm_offset_t physaddr, int size);
-void m18x_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size);
-void m18x_cmmu_flush_data_cache(vm_offset_t physaddr, int size);
-
-void m18x_cmmu_pmap_activate(
- unsigned cpu,
- unsigned uapr,
- batc_template_t i_batc[BATC_MAX],
- batc_template_t d_batc[BATC_MAX]);
-
-void m18x_cmmu_flush_remote_tlb(
- unsigned cpu,
- unsigned kernel,
- vm_offset_t vaddr,
- int size);
-
-void m18x_cmmu_set_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned data, /* 1 = data, 0 = instruction */
- unsigned value); /* the value to stuff into the batc */
-
-void m18x_cmmu_set_pair_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned value); /* the value to stuff into the batc */
+void m8820x_cmmu_init __P((void));
#endif /* _LOCORE */
@@ -245,4 +218,4 @@ void m18x_cmmu_set_pair_batc_entry(
#define NBSG (4*1024*1024) /* segment size */
-#endif /* __MACHINE_M882XX_H__ */
+#endif /* __MACHINE_M8820X_H__ */
diff --git a/sys/arch/mvme88k/include/m88410.h b/sys/arch/mvme88k/include/m88410.h
new file mode 100644
index 00000000000..9857c0f8f39
--- /dev/null
+++ b/sys/arch/mvme88k/include/m88410.h
@@ -0,0 +1,142 @@
+/* $OpenBSD: m88410.h,v 1.1 2001/12/13 08:55:51 smurph Exp $ */
+
+#ifndef __MACHINE_M88410_H__
+#define __MACHINE_M88410_H__
+
+/*
+ * mc88410 External Cache Controller definitions
+ * This is only available on MVME197DP/SP models.
+ */
+
+#ifndef _LOCORE
+
+#include <machine/asm_macro.h>
+#include <machine/psl.h>
+#ifdef _KERNEL
+#include <mvme88k/dev/busswreg.h>
+#endif
+
+#define XCC_NOP "0x0"
+#define XCC_FLUSH_PAGE "0x1"
+#define XCC_FLUSH_ALL "0x2"
+#define XCC_INVAL_ALL "0x3"
+#define XCC_ADDR 0xFF800000
+
+static __inline__ void mc88410_flush_page(vm_offset_t physaddr)
+{
+ vm_offset_t xccaddr = XCC_ADDR | (physaddr >> PGSHIFT);
+ m88k_psr_type psr;
+ struct bussw_reg *bs = (struct bussw_reg *)BS_BASE;
+ u_short bs_gcsr = bs->bs_gcsr;
+ u_short bs_romcr = bs->bs_romcr;
+
+ psr = get_psr();
+ /* mask misaligned exceptions */
+ set_psr(psr | PSR_MXM);
+ /* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
+ bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN0) ;
+ /* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */
+ bs->bs_gcsr |= BS_GCSR_XCC;
+
+ /* load the value of upper32 into r2 */
+ __asm__ __volatile__("or r2,r0," XCC_FLUSH_PAGE);
+ /* load the value of lower32 into r3 (always 0) */
+ __asm__ __volatile__("or r3,r0,r0");
+ /* load the value of xccaddr into r4 */
+ __asm__ __volatile__("or.u r5,r0,hi16(%0)" : : "r" (xccaddr));
+ __asm__ __volatile__("ld r4,r5,lo16(%0)" : : "r" (xccaddr));
+ /* make the double write. bang! */
+ __asm__ __volatile__("st.d r2,r4,0");
+
+ /* spin until the operation starts */
+ while (!bs->bs_xccr & BS_XCC_FBSY)
+ ;
+
+ /* restore PSR and friends */
+ set_psr(psr);
+ flush_pipeline();
+ bs->bs_gcsr = bs_gcsr;
+ bs->bs_romcr = bs_romcr;
+}
+
+static __inline__ void mc88410_flush(void)
+{
+ m88k_psr_type psr;
+ struct bussw_reg *bs = (struct bussw_reg *)BS_BASE;
+ u_short bs_gcsr = bs->bs_gcsr;
+ u_short bs_romcr = bs->bs_romcr;
+
+ psr = get_psr();
+ /* mask misaligned exceptions */
+ set_psr(psr | PSR_MXM);
+ /* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
+ bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN0) ;
+ /* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */
+ bs->bs_gcsr |= BS_GCSR_XCC;
+
+ /* load the value of upper32 into r2 */
+ __asm__ __volatile__("or r2,r0," XCC_FLUSH_ALL);
+ /* load the value of lower32 into r3 (always 0) */
+ __asm__ __volatile__("or r3,r0,r0");
+ /* load the value of xccaddr into r4 */
+ __asm__ __volatile__("or.u r5,r0,hi16(0xFF800000)");
+ __asm__ __volatile__("or r4,r5,r0"); /* r4 is now 0xFF800000 */
+ /* make the double write. bang! */
+ __asm__ __volatile__("st.d r2,r4,0");
+
+ /* spin until the operation starts */
+ while (!bs->bs_xccr & BS_XCC_FBSY)
+ ;
+
+ /* restore PSR and friends */
+ set_psr(psr);
+ flush_pipeline();
+ bs->bs_gcsr = bs_gcsr;
+ bs->bs_romcr = bs_romcr;
+}
+
+static __inline__ void mc88410_inval(void)
+{
+ m88k_psr_type psr;
+ struct bussw_reg *bs = (struct bussw_reg *)BS_BASE;
+ u_short bs_gcsr = bs->bs_gcsr;
+ u_short bs_romcr = bs->bs_romcr;
+
+ psr = get_psr();
+ /* mask misaligned exceptions */
+ set_psr(psr | PSR_MXM);
+ /* clear WEN0 and WEN1 in ROMCR (disables writes to FLASH) */
+ bs->bs_romcr &= ~(BS_ROMCR_WEN0 | BS_ROMCR_WEN0) ;
+ /* set XCC bit in GCSR (0xFF8xxxxx now decodes to mc88410) */
+ bs->bs_gcsr |= BS_GCSR_XCC;
+
+ /* load the value of upper32 into r2 */
+ __asm__ __volatile__("or r2,r0," XCC_INVAL_ALL);
+ /* load the value of lower32 into r3 (always 0) */
+ __asm__ __volatile__("or r3,r0,r0");
+ /* load the value of xccaddr into r4 */
+ __asm__ __volatile__("or.u r5,r0,hi16(0xFF800000)");
+ __asm__ __volatile__("or r4,r5,r0"); /* r4 is now 0xFF800000 */
+ /* make the double write. bang! */
+ __asm__ __volatile__("st.d r2,r4,0");
+
+ /* spin until the operation starts */
+ while (!bs->bs_xccr & BS_XCC_FBSY)
+ ;
+
+ /* restore PSR and friends */
+ set_psr(psr);
+ flush_pipeline();
+ bs->bs_gcsr = bs_gcsr;
+ bs->bs_romcr = bs_romcr;
+}
+
+static __inline__ void mc88410_sync(void)
+{
+ mc88410_flush();
+ mc88410_inval();
+}
+
+#endif /* _LOCORE */
+
+#endif __MACHINE_M88410_H__
diff --git a/sys/arch/mvme88k/include/mmu.h b/sys/arch/mvme88k/include/mmu.h
index b8d38a941db..dfa6bb9a219 100644
--- a/sys/arch/mvme88k/include/mmu.h
+++ b/sys/arch/mvme88k/include/mmu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: mmu.h,v 1.12 2001/08/24 22:47:18 miod Exp $ */
+/* $OpenBSD: mmu.h,v 1.13 2001/12/13 08:55:51 smurph Exp $ */
#ifndef __MACHINE_MMU_H__
#define __MACHINE_MMU_H__
@@ -60,7 +60,7 @@ typedef union sdt_entry_template {
typedef struct pt_entry {
unsigned long
pfn:20, /* page frame address */
- rsvA:1, /* reserved */
+ rsvA:1, /* reserved (U1 on mc88110) */
wired:1, /* wired bit <<software>> */
wt:1, /* writethrough (cache control) */
sup:1, /* supervisor protection */
@@ -70,10 +70,16 @@ typedef struct pt_entry {
modified:1, /* modified */
pg_used:1, /* used (referenced) */
prot:1, /* write protect */
- rsvC:1, /* reserved */
- dtype:1; /* valid */
+ dtype:2; /* descriptor type (bit 2 only on mc88110) */
} pt_entry_t;
+/* mc88110 indirect descriptors */
+typedef struct pt_ind_entry {
+ unsigned long
+ pda:30, /* page descriptor address */
+ dtype:2; /* valid */
+} pt_ind_entry_t;
+
typedef union pte_template {
pt_entry_t pte;
unsigned long bits;
@@ -137,6 +143,8 @@ typedef union batc_template {
*/
#define DT_INVALID 0
#define DT_VALID 1
+#define DT_IND_MASKED 2
+#define DT_IND_UMASKED 3
/*
* Number of entries in a page table.
@@ -243,7 +251,6 @@ extern u_int kvtop __P((vm_offset_t));
#define DMA_CACHE_SYNC 0x1
#define DMA_CACHE_SYNC_INVAL 0x2
#define DMA_CACHE_INV 0x3
-extern void dma_cachectl(vm_offset_t, int, int);
#endif /* __MACHINE_MMU_H__ */
diff --git a/sys/arch/mvme88k/include/mvme187.h b/sys/arch/mvme88k/include/mvme187.h
new file mode 100644
index 00000000000..a9200b05cac
--- /dev/null
+++ b/sys/arch/mvme88k/include/mvme187.h
@@ -0,0 +1,74 @@
+/* $OpenBSD: mvme187.h,v 1.1 2001/12/13 08:55:51 smurph Exp $ */
+/*
+ * Copyright (c) 1996 Nivas Madhur
+ * Copyright (c) 1999 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Nivas Madhur.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1991 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ */
+#ifndef __MACHINE_MVME187_H__
+#define __MACHINE_MVME187_H__
+/*
+ * VME187 CPU board constants - derived from Luna88k
+ * This file is include from <machine/board.h>
+ */
+
+/*
+ * Something to put append a 'U' to a long constant if it's C so that
+ * it'll be unsigned in both ANSI and traditional.
+ */
+#ifndef UDEFINED
+#if defined(_LOCORE)
+# define U(num) num
+#else
+# if defined(__STDC__)
+# define U(num) num ## U
+# else
+# define U(num) num/**/U
+# endif
+#endif
+#endif
+
+#define M187_ILEVEL U(0xFFF4203E) /* interrupt priority level */
+#define M187_IMASK U(0xFFF4203F) /* interrupt mask level */
+#define M187_ISRC U(0x00000000) /* interrupt mask src (NULL) */
+#define M187_IACK U(0xFFFE0000) /* interrupt ACK base */
+
+#endif __MACHINE_MVME187_H__
diff --git a/sys/arch/mvme88k/include/mvme197.h b/sys/arch/mvme88k/include/mvme197.h
new file mode 100644
index 00000000000..dd98facbde8
--- /dev/null
+++ b/sys/arch/mvme88k/include/mvme197.h
@@ -0,0 +1,74 @@
+/* $OpenBSD: mvme197.h,v 1.1 2001/12/13 08:55:51 smurph Exp $ */
+/*
+ * Copyright (c) 1996 Nivas Madhur
+ * Copyright (c) 1999 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Nivas Madhur.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1991 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ */
+#ifndef __MACHINE_MVME197_H__
+#define __MACHINE_MVME197_H__
+/*
+ * VME187 CPU board constants - derived from Luna88k
+ * This file is include from <machine/board.h>
+ */
+
+/*
+ * Something to put append a 'U' to a long constant if it's C so that
+ * it'll be unsigned in both ANSI and traditional.
+ */
+#ifndef UDEFINED
+#if defined(_LOCORE)
+# define U(num) num
+#else
+# if defined(__STDC__)
+# define U(num) num ## U
+# else
+# define U(num) num/**/U
+# endif
+#endif
+#endif
+
+#define M197_ILEVEL U(0xFFF00064) /* interrupt priority level */
+#define M197_IMASK U(0xFFF00065) /* interrupt mask level */
+#define M197_ISRC U(0xFFF0006F) /* interrupt SRC */
+#define M197_IACK U(0xFFF00100) /* interrupt ACK base */
+
+#endif __MACHINE_MVME197_H__
diff --git a/sys/arch/mvme88k/include/mvme1x7.h b/sys/arch/mvme88k/include/mvme1x7.h
index 330520895f1..7a131177bac 100644
--- a/sys/arch/mvme88k/include/mvme1x7.h
+++ b/sys/arch/mvme88k/include/mvme1x7.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: mvme1x7.h,v 1.6 2001/08/26 14:31:07 miod Exp $ */
+/* $OpenBSD: mvme1x7.h,v 1.7 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
* Copyright (c) 1999 Steve Murphree, Jr.
@@ -79,7 +79,6 @@
#define LOCAL_IO_DEVS U(0xFFF00000) /* local IO devices */
-#define PCC2_ADDR U(0xFFF42000) /* PCCchip2 Regs */
#define UTIL_ADDR U(0xFFC02000) /* PCCchip2 Regs */
#define MEM_CTLR U(0xFFF43000) /* MEMC040 mem controller */
#define SCC_ADDR U(0xFFF45000) /* Cirrus Chip */
@@ -97,7 +96,5 @@
#define TOD_CAL_MON U(0xFFFC1FFE) /* months */
#define TOD_CAL_YEAR U(0xFFFC1FFF) /* years */
-#define M187_IACK U(0xFFFE0000)
-#define M197_IACK U(0xFFF00100)
+#endif __MACHINE_MVME1X7_H__
-#endif /* __MACHINE_MVME1X7_H__ */
diff --git a/sys/arch/mvme88k/include/param.h b/sys/arch/mvme88k/include/param.h
index 128d5301cf4..d666d83b04f 100644
--- a/sys/arch/mvme88k/include/param.h
+++ b/sys/arch/mvme88k/include/param.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: param.h,v 1.23 2001/12/05 01:57:15 provos Exp $ */
+/* $OpenBSD: param.h,v 1.24 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* Copyright (c) 1988 University of Utah.
@@ -173,16 +173,30 @@ extern int delay __P((int));
#define DELAY(x) delay(x)
extern int cputyp;
+extern int brdtyp;
extern int cpumod;
#endif
/*
+ * Values for the brdtyp variable.
+ */
+#define BRD_187 0x187
+#define BRD_188 0x188
+#define BRD_197 0x197
+#define BRD_8120 0x8120
+
+/*
* Values for the cputyp variable.
*/
-#define CPU_187 0x187
-#define CPU_188 0x188
-#define CPU_197 0x197
-#define CPU_8120 0x8120
+#define CPU_88100 0x100
+#define CPU_88110 0x110
+
+/*
+ * Values for the cpumod variable.
+ */
+#define MOD_LE 0x01
+#define MOD_SP 0x02
+#define MOD_DP 0x03
#endif /* !_MACHINE_PARAM_H_ */
diff --git a/sys/arch/mvme88k/include/psl.h b/sys/arch/mvme88k/include/psl.h
index 3e2ab76a503..46220d9fab0 100644
--- a/sys/arch/mvme88k/include/psl.h
+++ b/sys/arch/mvme88k/include/psl.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: psl.h,v 1.9 2001/07/01 23:26:35 miod Exp $ */
+/* $OpenBSD: psl.h,v 1.10 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
* All rights reserved.
@@ -59,11 +59,16 @@
/*
* processor status register
*/
+
#define PSR_MODE 0x80000000U /* supervisor/user mode */
#define PSR_BO 0x40000000U /* byte-ordering 0:big 1:little */
-#define PSR_SER 0x20000000U /* serial mode */
+#define PSR_SER 0x20000000U /* 88110 serial mode */
#define PSR_C 0x10000000U /* carry */
-#define PSR_SFD 0x000003F0U /* SFU disable */
+#define PSR_SGN 0x04000000U /* 88110 Signed Immediate mode */
+#define PSR_SRM 0x02000000U /* 88110 Serialize Memory */
+#define PSR_TRACE 0x00800000U /* 88110 hardware trace */
+#define PSR_SFD 0x000003E0U /* SFU disable */
+#define PSR_SFD2 0x00000010U /* 88110 SFU2 (Graphics) disable */
#define PSR_SFD1 0x00000008U /* SFU1 (FPU) disable */
#define PSR_MXM 0x00000004U /* misaligned access enable */
#define PSR_IND 0x00000002U /* interrupt disable */
@@ -82,10 +87,16 @@ struct psr {
unsigned
psr_mode: 1,
psr_bo : 1,
- psr_ser : 1,
+ psr_ser : 1, /* mc88110 */
psr_c : 1,
- :18,
- psr_sfd : 6,
+ : 1,
+ psr_sgn : 1, /* mc88110 */
+ psr_srm : 1, /* mc88110 */
+ : 1,
+ psr_trc : 1, /* mc88110 */
+ :13,
+ psr_sfd : 5,
+ psr_sfd2: 1, /* mc88110 */
psr_sfd1: 1,
psr_mxm : 1,
psr_ind : 1,
diff --git a/sys/arch/mvme88k/include/reg.h b/sys/arch/mvme88k/include/reg.h
index a627ba4a5b6..a695b1fbdcc 100644
--- a/sys/arch/mvme88k/include/reg.h
+++ b/sys/arch/mvme88k/include/reg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: reg.h,v 1.8 2001/08/24 22:47:34 miod Exp $ */
+/* $OpenBSD: reg.h,v 1.9 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* Copyright (c) 1996 Nivas Madhur
@@ -41,20 +41,30 @@ struct reg {
unsigned fpsr;
unsigned fpcr;
unsigned sxip;
-#define exip sxip
+#define exip sxip /* mc88110 */
unsigned snip;
-#define enip snip
+#define enip snip /* mc88110 */
unsigned sfip;
unsigned ssbr;
+#define duap ssbr /* mc88110 */
unsigned dmt0;
+#define dsr dmt0 /* mc88110 */
unsigned dmd0;
+#define dlar dmd0 /* mc88110 */
unsigned dma0;
+#define dpar dma0 /* mc88110 */
unsigned dmt1;
+#define isr dmt1 /* mc88110 */
unsigned dmd1;
+#define ilar dmd1 /* mc88110 */
unsigned dma1;
+#define ipar dma1 /* mc88110 */
unsigned dmt2;
+#define isap dmt2 /* mc88110 */
unsigned dmd2;
+#define dsap dmd2 /* mc88110 */
unsigned dma2;
+#define iuap dma2 /* mc88110 */
unsigned fpecr;
unsigned fphs1;
unsigned fpls1;
@@ -70,12 +80,6 @@ struct reg {
unsigned scratch1; /* used by locore trap handling code */
unsigned ipfsr; /* P BUS status - used in inst fault handling */
unsigned dpfsr; /* P BUS status - used in data fault handling */
- unsigned dsr; /* MVME197 */
- unsigned dlar; /* MVME197 */
- unsigned dpar; /* MVME197 */
- unsigned isr; /* MVME197 */
- unsigned ilar; /* MVME197 */
- unsigned ipar; /* MVME197 */
unsigned cpu; /* cpu number */
};
diff --git a/sys/arch/mvme88k/include/signal.h b/sys/arch/mvme88k/include/signal.h
index 817828f11de..618f3a694c8 100644
--- a/sys/arch/mvme88k/include/signal.h
+++ b/sys/arch/mvme88k/include/signal.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: signal.h,v 1.6 2001/08/12 12:03:02 heko Exp $ */
+/* $OpenBSD: signal.h,v 1.7 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
* All rights reserved.
@@ -55,15 +55,25 @@ struct sigcontext {
int sc_fpsr;
int sc_fpcr;
int sc_ssbr;
+#define sc_duap sc_ssbr /* mc88110 */
int sc_dmt0;
+#define sc_dsr sc_dmt0 /* mc88110 */
int sc_dmd0;
+#define sc_dlar sc_dmd0 /* mc88110 */
int sc_dma0;
+#define sc_dpar sc_dma0 /* mc88110 */
int sc_dmt1;
+#define sc_isr sc_dmt1 /* mc88110 */
int sc_dmd1;
+#define sc_ilar sc_dmd1 /* mc88110 */
int sc_dma1;
+#define sc_ipar sc_dma1 /* mc88110 */
int sc_dmt2;
+#define sc_isap sc_dmt2 /* mc88110 */
int sc_dmd2;
+#define sc_dsap sc_dmd2 /* mc88110 */
int sc_dma2;
+#define sc_iuap sc_dma2 /* mc88110 */
int sc_fpecr;
int sc_fphs1;
int sc_fpls1;
@@ -73,6 +83,6 @@ struct sigcontext {
int sc_fprh;
int sc_fprl;
int sc_fpit;
- int sc_xxxx; /* padd to double word boundary */
+ int sc_xxxx; /* pad to double word boundary */
};
#endif /* __MACHINE_SIGNAL_H__ */
diff --git a/sys/arch/mvme88k/include/trap.h b/sys/arch/mvme88k/include/trap.h
index 0da0e54175d..475c9e8ab99 100644
--- a/sys/arch/mvme88k/include/trap.h
+++ b/sys/arch/mvme88k/include/trap.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: trap.h,v 1.12 2001/11/06 18:41:10 art Exp $ */
+/* $OpenBSD: trap.h,v 1.13 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1992 Carnegie Mellon University
@@ -88,14 +88,19 @@ int ss_inst_delayed(unsigned ins);
unsigned ss_next_instr_address(struct proc *p, unsigned pc, unsigned delay_slot);
int cpu_singlestep(register struct proc *p);
-#if defined(MVME187) || defined(MVME188)
-void syscall(register_t code, struct m88100_saved_state *tf);
-void trap18x(unsigned type, struct m88100_saved_state *frame);
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
-void m197_syscall(register_t code, struct m88100_saved_state *tf);
-void trap197(unsigned type, struct m88100_saved_state *frame);
-#endif /* MVME197 */
+#ifdef M88100
+void m88100_trap __P((unsigned, struct m88100_saved_state *));
+void m88100_syscall __P((register_t, struct m88100_saved_state *));
+#endif /* M88100 */
+
+#ifdef M88110
+void m88110_trap __P((unsigned, struct m88100_saved_state *));
+void m88110_syscall __P((register_t, struct m88100_saved_state *));
+#endif /* M88110 */
+
+/* machine dependant trap and syscall macros */
+#define trap(type, frame) (*md.interrupt_func)(type, frame)
+#define syscall(code, frame) (*md.syscall_func)(code, frame)
#endif /* _LOCORE */
diff --git a/sys/arch/mvme88k/mvme88k/cmmu.c b/sys/arch/mvme88k/mvme88k/cmmu.c
index 2fd5cd97bb1..5d296dfd559 100644
--- a/sys/arch/mvme88k/mvme88k/cmmu.c
+++ b/sys/arch/mvme88k/mvme88k/cmmu.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: cmmu.c,v 1.14 2001/11/27 05:37:02 miod Exp $ */
+/* $OpenBSD: cmmu.c,v 1.15 2001/12/13 08:55:51 smurph Exp $ */
/*
* Copyright (c) 1998 Steve Murphree, Jr.
* Copyright (c) 1996 Nivas Madhur
@@ -60,18 +60,9 @@
#include <sys/param.h>
#include <sys/types.h>
#include <sys/simplelock.h>
-
-#include <machine/mmu.h>
-#include <machine/board.h>
#include <machine/cmmu.h>
#include <machine/cpus.h>
#include <machine/cpu_number.h>
-#if defined(MVME187) || defined(MVME188)
-#include <machine/m882xx.h>
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
-#include <machine/m88110.h>
-#endif /* MVME197 */
/*
* This lock protects the cmmu SAR and SCR's; other ports
@@ -80,10 +71,6 @@
* May be used from "db_interface.c".
*/
struct simplelock cmmu_cpu_lock;
-
-#define CMMU_LOCK simple_lock(&cmmu_cpu_lock)
-#define CMMU_UNLOCK simple_unlock(&cmmu_cpu_lock)
-
unsigned cache_policy = /*CACHE_INH*/ 0;
unsigned cpu_sets[MAX_CPUS];
unsigned number_cpus = 0;
@@ -91,782 +78,14 @@ unsigned master_cpu = 0;
int max_cpus, max_cmmus;
int cpu_cmmu_ratio;
-#ifdef CMMU_DEBUG
-void
-show_apr(unsigned value)
-{
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_show_apr(value);
- break;
-#endif
-#ifdef MVME197
- case CPU_197:
- m197_show_apr(value);
- break;
-#endif
- }
-}
-
-void
-show_sctr(unsigned value)
-{
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_show_sctr(value);
- break;
-#endif
-#ifdef MVME197
- case CPU_197:
- m197_show_sctr(value);
- break;
-#endif
- }
-}
-#endif /* CMMU_DEBUG */
-
-void
-setup_board_config(void)
-{
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_setup_board_config();
- break;
-#endif
-#ifdef MVME197
- case CPU_197:
- m197_setup_board_config();
- break;
-#endif
- }
-}
-
-void
-setup_cmmu_config(void)
-{
- int cpu;
-
- for (cpu = 0; cpu < MAX_CPUS; cpu++)
- cpu_sets[cpu] = 0;
-
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_setup_cmmu_config();
- break;
-#endif
-#ifdef MVME197
- case CPU_197:
- m197_setup_cmmu_config();
- break;
-#endif
- }
-}
-
-void
-cmmu_dump_config(void)
-{
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_dump_config();
- break;
-#endif
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_dump_config();
- break;
-#endif
- }
-}
+struct cmmu_p *cmmu;
-#ifdef DDB
-/*
- * Used by DDB for cache probe functions
- */
-unsigned
-cmmu_get_by_mode(int cpu, int mode)
-{
- unsigned retval;
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- retval = m18x_cmmu_get_by_mode(cpu, mode);
- break;
-#endif
-#ifdef MVME197
- case CPU_197:
- retval = m197_cmmu_get_by_mode(cpu, mode);
- break;
-#endif
- }
- CMMU_UNLOCK;
- return retval;
-}
-#endif
+void md_cmmu_flush_tlb __P((unsigned kernel, vm_offset_t vaddr, int size));
-/*
- * Should only be called after the calling cpus knows its cpu
- * number and master/slave status . Should be called first
- * by the master, before the slaves are started.
-*/
+/* This is here so that process.S doesn't have to decide the CPU type */
void
-cpu_configuration_print(int master)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cpu_configuration_print(master);
- break;
-#endif
-#ifdef MVME197
- case CPU_197:
- m197_cpu_configuration_print(master);
- break;
-#endif
- }
- CMMU_UNLOCK;
-}
-
-/*
- * CMMU initialization routine
- */
-void
-cmmu_init(void)
-{
- /* init the lock */
- simple_lock_init(&cmmu_cpu_lock);
-
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_init();
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_init();
- break;
-#endif /* MVME197 */
- }
-}
-
-/*
- * Just before poweroff or reset....
- */
-void
-cmmu_shutdown_now(void)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_shutdown_now();
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_shutdown_now();
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-#define PARITY_ENABLE
-
-/*
- * enable parity
- */
-void
-cmmu_parity_enable(void)
-{
-#ifdef PARITY_ENABLE
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_parity_enable();
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_parity_enable();
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-#endif /* PARITY_ENABLE */
-}
-
-/*
- * Find out the CPU number from accessing CMMU
- * Better be at splhigh, or even better, with interrupts
- * disabled.
- */
-unsigned
-cmmu_cpu_number(void)
-{
- unsigned retval;
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- retval = m18x_cmmu_cpu_number();
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- retval = m197_cmmu_cpu_number();
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
- return retval;
-}
-
-/**
- ** Functions that actually modify CMMU registers.
- **/
-
-void
-cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_remote_set(cpu, r, data, x);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_remote_set(cpu, r, data, x);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-/*
- * cmmu_cpu_lock should be held when called if read
- * the CMMU_SCR or CMMU_SAR.
- */
-unsigned
-cmmu_remote_get(unsigned cpu, unsigned r, unsigned data)
-{
- unsigned retval;
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- retval = m18x_cmmu_remote_get(cpu, r, data);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- retval = m197_cmmu_remote_get(cpu, r, data);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
- return retval;
-}
-
-/* Needs no locking - read only registers */
-unsigned
-cmmu_get_idr(unsigned data)
-{
- unsigned retval;
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- retval = m18x_cmmu_get_idr(data);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- retval = m197_cmmu_get_idr(data);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
- return retval;
-}
-
-void
-cmmu_set_sapr(unsigned ap)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_set_sapr(ap);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_set_sapr(ap);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-void
-cmmu_remote_set_sapr(unsigned cpu, unsigned ap)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_remote_set_sapr(cpu, ap);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_remote_set_sapr(cpu, ap);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-void
-cmmu_set_uapr(unsigned ap)
-{
- register int s = splhigh();
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_set_uapr(ap);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_set_uapr(ap);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
- splx(s);
-}
-
-/*
- * Set batc entry number entry_no to value in
- * the data or instruction cache depending on data.
- *
- * Except for the cmmu_init, this function, cmmu_set_pair_batc_entry,
- * and cmmu_pmap_activate are the only functions which may set the
- * batc values.
- */
-void
-cmmu_set_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned data, /* 1 = data, 0 = instruction */
- unsigned value) /* the value to stuff into the batc */
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_set_batc_entry(cpu, entry_no, data, value);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_set_batc_entry(cpu, entry_no, data, value);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-/*
- * Set batc entry number entry_no to value in
- * the data and instruction cache for the named CPU.
- */
-void
-cmmu_set_pair_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned value) /* the value to stuff into the batc */
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_set_pair_batc_entry(cpu, entry_no, value);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-/**
- ** Functions that invalidate TLB entries.
- **/
-
-/*
- * flush any tlb
- * Some functionality mimiced in cmmu_pmap_activate.
- */
-void
-cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-/*
- * flush my personal tlb
- */
-void
-cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size)
+md_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size)
{
- int cpu;
- cpu = cpu_number();
- cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
+ cmmu_flush_tlb(kernel, vaddr, size);
}
-/*
- * New fast stuff for pmap_activate.
- * Does what a few calls used to do.
- * Only called from pmap.c's _pmap_activate().
- */
-void
-cmmu_pmap_activate(
- unsigned cpu,
- unsigned uapr,
- batc_template_t i_batc[BATC_MAX],
- batc_template_t d_batc[BATC_MAX])
-{
- register int s = splhigh();
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
- splx(s);
-}
-
-/**
- ** Functions that invalidate caches.
- **
- ** Cache invalidates require physical addresses. Care must be exercised when
- ** using segment invalidates. This implies that the starting physical address
- ** plus the segment length should be invalidated. A typical mistake is to
- ** extract the first physical page of a segment from a virtual address, and
- ** then expecting to invalidate when the pages are not physically contiguous.
- **
- ** We don't push Instruction Caches prior to invalidate because they are not
- ** snooped and never modified (I guess it doesn't matter then which form
- ** of the command we use then).
- **/
-/*
- * flush both Instruction and Data caches
- */
-void
-cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_flush_remote_cache(cpu, physaddr, size);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_flush_remote_cache(cpu, physaddr, size);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-/*
- * flush both Instruction and Data caches
- */
-void
-cmmu_flush_cache(vm_offset_t physaddr, int size)
-{
- int cpu = cpu_number();
- cmmu_flush_remote_cache(cpu, physaddr, size);
-}
-
-/*
- * flush Instruction caches
- */
-void
-cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_flush_remote_inst_cache(cpu, physaddr, size);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-/*
- * flush Instruction caches
- */
-void
-cmmu_flush_inst_cache(vm_offset_t physaddr, int size)
-{
- int cpu;
- cpu = cpu_number();
- cmmu_flush_remote_inst_cache(cpu, physaddr, size);
-}
-
-void
-cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_flush_remote_data_cache(cpu, physaddr, size);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-/*
- * flush data cache
- */
-void
-cmmu_flush_data_cache(vm_offset_t physaddr, int size)
-{
- int cpu;
- cpu = cpu_number();
- cmmu_flush_remote_data_cache(cpu, physaddr, size);
-}
-
-#if 0
-/*
- * sync dcache (and icache too)
- */
-void
-cmmu_sync_cache(vm_offset_t physaddr, int size)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_sync_cache(physaddr, size);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_sync_cache(physaddr, size);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-void
-cmmu_sync_inval_cache(vm_offset_t physaddr, int size)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_sync_inval_cache(physaddr, size);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_sync_inval_cache(physaddr, size);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-void
-cmmu_inval_cache(vm_offset_t physaddr, int size)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_inval_cache(physaddr, size);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_inval_cache(physaddr, size);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-#endif
-
-void
-dma_cachectl(vm_offset_t va, int size, int op)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_dma_cachectl(va, size, op);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_dma_cachectl(va, size, op);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-#ifdef DDB
-
-/*
- * Show (for debugging) how the given CMMU translates the given ADDRESS.
- * If cmmu == -1, the data cmmu for the current cpu is used.
- */
-void
-cmmu_show_translation(
- unsigned address,
- unsigned supervisor_flag,
- unsigned verbose_flag,
- int cmmu_num)
-{
- CMMU_LOCK;
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_show_translation(address, supervisor_flag,
- verbose_flag, cmmu_num);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_show_translation(address, supervisor_flag,
- verbose_flag, cmmu_num);
- break;
-#endif /* MVME197 */
- }
- CMMU_UNLOCK;
-}
-
-
-void
-cmmu_cache_state(unsigned addr, unsigned supervisor_flag)
-{
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_cmmu_cache_state(addr, supervisor_flag);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_cmmu_cache_state(addr, supervisor_flag);
- break;
-#endif /* MVME197 */
- }
-}
-
-void
-show_cmmu_info(unsigned addr)
-{
- switch (cputyp) {
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
- m18x_show_cmmu_info(addr);
- break;
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- case CPU_197:
- m197_show_cmmu_info(addr);
- break;
-#endif /* MVME197 */
- }
-}
-#endif /* end if DDB */
diff --git a/sys/arch/mvme88k/mvme88k/eh.S b/sys/arch/mvme88k/mvme88k/eh.S
index 719d85dabf4..ff71fa44563 100644
--- a/sys/arch/mvme88k/mvme88k/eh.S
+++ b/sys/arch/mvme88k/mvme88k/eh.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: eh.S,v 1.18 2001/11/27 05:26:36 miod Exp $ */
+/* $OpenBSD: eh.S,v 1.19 2001/12/13 08:55:51 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -215,7 +215,7 @@
#include "assym.h"
#include <machine/asm.h>
-#include <machine/board.h>
+#include <machine/param.h> /* CPU_ and BRD_ defines */
#include <machine/trap.h> /* for T_ defines */
#ifdef MVME188
#include <machine/mvme188.h>
@@ -237,8 +237,7 @@
#define EF_SR3 (EF_R0 + 5)
#define EF_FLAGS EF_MODE
-#define INTSTACK 0 /* To make interupts use their own stack */
-
+#define INTSTACK 0 /* To make interupts use their own stack */
data
align 4
sbadcpupanic:
@@ -254,6 +253,74 @@ Lbadcpupanic:
align 8
+#define OFF_VEC 0
+#define OFF_EPSR 4
+#define OFF_EXIP 8
+#define OFF_ENIP 12
+#define OFF_DSR 16
+#define OFF_DLAR 20
+#define OFF_DPAR 24
+#define OFF_ISR 28
+#define OFF_ILAR 32
+#define OFF_IPAR 36
+#define OFF_TMP 40
+
+/*
+ * This define is used to save exception register in case of
+ * the error exception XXX smurph
+ */
+#define SAVE_CR(CREG, OFF) ; \
+ /* free r13 */ ; \
+ stcr r13, SRX ; \
+ /* save address of _savereg to r13 */ ; \
+ or.u r13, r0, hi16(_savereg) ; \
+ or r13, r13, lo16(_savereg) ; \
+ /* store r1 to _temp_r1 */ ; \
+ st r1, r13, OFF_TMP ; \
+ /* r1 now free */ ; \
+ ldcr r1, CREG ; \
+ st r1, r13, OFF ; \
+ /* restore r1 */ ; \
+ ld r1, r13, OFF_TMP ; \
+ /* restore r13 */ ; \
+ ldcr r13, SRX
+
+#define SAVE_R(REG, OFF) ; \
+ /* free r13 */ ; \
+ stcr r13, SRX ; \
+ /* save address of _savereg to r13 */ ; \
+ or.u r13, r0, hi16(_savereg) ; \
+ or r13, r13, lo16(_savereg) ; \
+ /* store reg */ ; \
+ st REG, r13, OFF ; \
+ /* restore r13 */ ; \
+ ldcr r13, SRX
+
+#define GET_R(REG, OFF) ; \
+ /* free r13 */ ; \
+ stcr r13, SRX ; \
+ /* save r1 to _tmpreg */ ; \
+ /* save address of _savereg to r13 */ ; \
+ or.u r13, r0, hi16(_savereg) ; \
+ or r13, r13, lo16(_savereg) ; \
+ /* store reg */ ; \
+ ld REG, r13, OFF ; \
+ /* restore r13 */ ; \
+ ldcr r13, SRX
+
+_savereg:
+ word 0x00000063 /* 0 vector */
+ word 0x00000000 /* 4 EXIP */
+ word 0x00000000 /* 8 ENIP */
+ word 0x00000000 /* 12 DSR */
+ word 0x00000000 /* 16 DLAR */
+ word 0x00000000 /* 20 DPAR */
+ word 0x00000000 /* 24 ISR */
+ word 0x00000000 /* 28 ILAR */
+ word 0x00000000 /* 32 IPAR */
+ word 0x00000000 /* 36 EPSR */
+ word 0x00000000 /* 36 TMP */
+
/***************************************************************************
***************************************************************************
**
@@ -286,7 +353,7 @@ Lbadcpupanic:
** (which is pointed-to by r31).
**/
-#if defined(MVME187) || defined (MVME188)
+#ifdef M88100
#define PREP(NAME, NUM, BIT, SSBR_STUFF, FLAG_PRECHECK) ; \
xcr FLAGS, FLAGS, SR1 ; \
FLAG_PRECHECK ; \
@@ -319,39 +386,60 @@ Lbadcpupanic:
; \
/* All general regs free -- do any debugging */ ; \
PREP_DEBUG(BIT, NAME)
-#endif /* defined(MVME187) || defined (MVME188) */
+#endif /* m88100 */
-#ifdef MVME197
+#ifdef M88110
#define PREP2(NAME, NUM, BIT, SSBR_STUFF, FLAG_PRECHECK); \
xcr FLAGS, FLAGS, SR1 ; \
FLAG_PRECHECK ; \
; \
/* the bsr later clobbers r1, so save now */ ; \
- stcr r1, SR2 /* r1 now free */ ; \
+ stcr r1, SR2 /* r1 now free */ ; \
+/* stcr r3, SRX ; \
+ ldcr r1, DCTL ; \
+ or r3, r0, NUM ; \
+ cmp r3, r3, 3 ; \
+ bb1.n ne, r3, 1f ; \
+ set r1, r1, 1<DCTL_MEN> ; \
+ clr r1, r1, 1<DCTL_MEN> ; \
+ set FLAGS, FLAGS, 1<FLAG_TBE> ; \
+ 1:stcr r1, DCTL ; \
+ ldcr r3, SRX */ ; \
+ /* save exception time regs */ ; \
+ or r1, r0, NUM ; \
+ cmp r1, r1, 132 ; \
+ bb1 eq, r1, 1f ; \
+ SAVE_CR(EPSR, OFF_EPSR) ; \
+ SAVE_CR(EXIP, OFF_EXIP) ; \
+ SAVE_CR(ENIP, OFF_ENIP) ; \
+ SAVE_CR(DSR, OFF_DSR) ; \
+ SAVE_CR(DLAR, OFF_DLAR) ; \
+ SAVE_CR(DPAR, OFF_DPAR) ; \
+ SAVE_CR(ISR, OFF_ISR) ; \
+ SAVE_CR(ILAR, OFF_ILAR) ; \
+ SAVE_CR(IPAR, OFF_IPAR) ; \
+ or r1, r0, NUM ; \
+ SAVE_R(r1, OFF_VEC) ; \
/* set or clear the FLAG_FROM_KERNEL bit */ ; \
- ldcr r1, EPSR ; \
- bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f ; \
- clr FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \
- set FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \
+1: ldcr r1, EPSR ; \
+ bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f ; \
+ clr FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \
+ set FLAGS, FLAGS, 1<FLAG_FROM_KERNEL> ; \
; \
/* get a stack (exception frame) */ ; \
- 1: bsr m197_setup_phase_one ; \
+ 1: bsr m88110_setup_phase_one ; \
; \
/* TMP2 now free -- use to set EF_VECTOR */ ; \
or TMP2, r0, NUM ; \
st TMP2, r31, REG_OFF(EF_VECTOR) ; \
; \
- /* Clear any bits in the SSBR (held in TMP) */ ; \
- /* SSBR_STUFF may be empty, though. */ ; \
- SSBR_STUFF ; \
- ; \
/* call setup_phase_two to restart the FPU */ ; \
/* and to save all general registers. */ ; \
- bsr m197_setup_phase_two ; \
+ bsr m88110_setup_phase_two ; \
; \
/* All general regs free -- do any debugging */ ; \
PREP_DEBUG(BIT, NAME)
-#endif /* MVME197 */
+#endif /* M88110 */
/* Some defines for use with PREP() */
#define No_SSBR_Stuff /* empty */
@@ -359,8 +447,8 @@ Lbadcpupanic:
#define No_Precheck /* empty */
#define Data_Precheck \
bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, ignore_data_exception
-#define M197_Data_Precheck \
- bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, m197_ignore_data_exception
+#define M88110_Data_Precheck \
+ bb1.n FLAG_IGNORE_DATA_EXCEPTION, FLAGS, m88110_ignore_data_exception
#ifdef EH_DEBUG
/*
@@ -371,8 +459,9 @@ Lbadcpupanic:
*
* The bits are defined in "asm.h"
*/
-GLOBAL(eh_debug) word 0x00000000
+GLOBAL(eh_debug) word 0x00000000
+
/*
* additional pre-servicing preparation to be done when
* debugging... check eh_debug and make the call if
@@ -423,50 +512,50 @@ GLOBAL(eh_debug) word 0x00000000
#define DONE(num) br return_from_exception_handler
#endif
-#if defined(MVME187) || defined (MVME188)
+#ifdef M88100
/*#########################################################################*/
/*#### THE ACTUAL EXCEPTION HANDLER ENTRY POINTS for MVME18x ##############*/
/*#########################################################################*/
/* unknown exception handler */
GLOBAL(unknown_handler)
- PREP("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)
- DONE(DEBUG_UNKNOWN_BIT)
+ PREP("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_UNKNOWNFLT, r30)
+ DONE(DEBUG_UNKNOWN_BIT)
/* interrupt exception handler */
GLOBAL(interrupt_handler)
- PREP("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)
- /* interrupt_func is set in mvme_bootstrap() */
- CALL(_C_LABEL(trap18x), T_INT, r30)
- /*CALLP(_interrupt_func, 1, r30) */
- DONE(DEBUG_INTERRUPT_BIT)
+ PREP("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)
+ /* interrupt_func is set in mvme_bootstrap() */
+ CALL(_m88100_trap, T_INT, r30)
+ /*CALLP(_interrupt_func, 1, r30) */
+ DONE(DEBUG_INTERRUPT_BIT)
/* instruction access exception handler */
GLOBAL(instruction_access_handler)
- PREP("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_INSTFLT, r30)
- DONE(DEBUG_INSTRUCTION_BIT)
+ PREP("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_INSTFLT, r30)
+ DONE(DEBUG_INSTRUCTION_BIT)
/*
* data access exception handler --
* See badaddr() below for info about Data_Precheck.
*/
GLOBAL(data_exception_handler)
- PREP("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, Data_Precheck)
- DONE(DEBUG_DATA_BIT)
+ PREP("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, Data_Precheck)
+ DONE(DEBUG_DATA_BIT)
/* misaligned access exception handler */
GLOBAL(misaligned_handler)
- PREP("misalign", 4, DEBUG_MISALIGN_BIT, Clear_SSBR_Dest, No_Precheck)
- CALL(_C_LABEL(trap18x), T_MISALGNFLT, r30)
- DONE(DEBUG_MISALIGN_BIT)
+ PREP("misalign", 4, DEBUG_MISALIGN_BIT, Clear_SSBR_Dest, No_Precheck)
+ CALL(_m88100_trap, T_MISALGNFLT, r30)
+ DONE(DEBUG_MISALIGN_BIT)
/* unimplemented opcode exception handler */
GLOBAL(unimplemented_handler)
- PREP("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_ILLFLT, r30)
- DONE(DEBUG_UNIMPLEMENTED_BIT)
+ PREP("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_ILLFLT, r30)
+ DONE(DEBUG_UNIMPLEMENTED_BIT)
/*
* Some versions of the chip have a bug whereby false privilege
@@ -474,112 +563,114 @@ GLOBAL(unimplemented_handler)
* it is false. If so, just return. The code before PREP handles this....
*/
GLOBAL(privilege_handler)
- stcr r1, SR2 /* hold r1 for a moment */
- ldcr r1, SXIP /* look at the sxip... valid bit set? */
- bb1.n RTE_VALID_BIT, r1, 1f /*skip over return if a valid exception*/
- ldcr r1, SR2 /* restore r1 */
- RTE
-1: PREP("privilege", 6, DEBUG_PRIVILEGE_BIT, Clear_SSBR_Dest, No_Precheck)
- CALL(_C_LABEL(trap18x), T_PRIVINFLT, r30)
- DONE(DEBUG_PRIVILEGE_BIT)
+ stcr r1, SR2 /* hold r1 for a moment */
+ ldcr r1, SXIP /* look at the sxip... valid bit set? */
+ bb1.n RTE_VALID_BIT, r1, 1f /*skip over return if a valid exception*/
+ ldcr r1, SR2 /* restore r1 */
+ RTE
+1: PREP("privilege", 6, DEBUG_PRIVILEGE_BIT, Clear_SSBR_Dest, No_Precheck)
+ CALL(_m88100_trap, T_PRIVINFLT, r30) DONE(DEBUG_PRIVILEGE_BIT)
/*
* I'm not sure what the trap(T_BNDFLT,...) does, but it doesn't send
* a signal to the process...
*/
GLOBAL(bounds_handler)
- PREP("bounds", 7, DEBUG_BOUNDS_BIT, Clear_SSBR_Dest, No_Precheck)
- CALL(_C_LABEL(trap18x), T_BNDFLT, r30)
- DONE(DEBUG_BOUNDS_BIT)
+ PREP("bounds", 7, DEBUG_BOUNDS_BIT, Clear_SSBR_Dest, No_Precheck)
+ CALL(_m88100_trap, T_BNDFLT, r30)
+ DONE(DEBUG_BOUNDS_BIT)
/* integer divide-by-zero exception handler */
GLOBAL(divide_handler)
- PREP("divide", 8, DEBUG_DIVIDE_BIT, Clear_SSBR_Dest, No_Precheck)
- CALL(_C_LABEL(trap18x), T_ZERODIV, r30)
- DONE(DEBUG_DIVIDE_BIT)
+ PREP("divide", 8, DEBUG_DIVIDE_BIT, Clear_SSBR_Dest, No_Precheck)
+ CALL(_m88100_trap, T_ZERODIV, r30)
+ DONE(DEBUG_DIVIDE_BIT)
/* integer overflow exception handelr */
GLOBAL(overflow_handler)
- PREP("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_OVFFLT, r30)
- DONE(DEBUG_OVERFLOW_BIT)
+ PREP("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_OVFFLT, r30)
+ DONE(DEBUG_OVERFLOW_BIT)
/* Floating-point precise handler */
#define FPp_SSBR_STUFF bsr clear_FPp_ssbr_bit
ASGLOBAL(fp_precise_handler)
- PREP("FPU precise", 114, DEBUG_FPp_BIT, FPp_SSBR_STUFF, No_Precheck)
- CALL(_m88100_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/
- DONE(DEBUG_FPp_BIT)
+ PREP("FPU precise", 114, DEBUG_FPp_BIT, FPp_SSBR_STUFF, No_Precheck)
+ CALL(_m88100_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/
+ DONE(DEBUG_FPp_BIT)
/* Floating-point imprecise handler */
#define FPi_SSBR_STUFF bsr clear_FPi_ssbr_bit
ASGLOBAL(fp_imprecise_handler)
- PREP("FPU imprecise", 115, DEBUG_FPi_BIT, FPi_SSBR_STUFF, No_Precheck)
- CALL(_Xfp_imprecise, r0, r30) /*call fp_imprecise(??,exception_frame)*/
- DONE(DEBUG_FPi_BIT)
+ PREP("FPU imprecise", 115, DEBUG_FPi_BIT, FPi_SSBR_STUFF, No_Precheck)
+ CALL(_Xfp_imprecise, r0, r30) /*call fp_imprecise(??,exception_frame)*/
+ DONE(DEBUG_FPi_BIT)
/* All standard system calls. */
GLOBAL(syscall_handler)
- PREP("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)
- ld r13, r30, GENREG_OFF(13)
- CALL(_syscall, r13, r30) /* system call no. is in r13 */
- DONE(DEBUG_SYSCALL_BIT)
+ PREP("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)
+ ld r13, r30, GENREG_OFF(13)
+ CALL(_m18x_syscall, r13, r30) /* system call no. is in r13 */
+ DONE(DEBUG_SYSCALL_BIT)
/* trap 496 comes here */
GLOBAL(bugtrap)
- PREP("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)
- ld r9, r30, GENREG_OFF(9)
- CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */
- DONE(DEBUG_SYSCALL_BIT)
+ PREP("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)
+ ld r9, r30, GENREG_OFF(9)
+ CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */
+ DONE(DEBUG_BUGCALL_BIT)
GLOBAL(sigsys)
- PREP("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_SIGSYS, r30)
- DONE(DEBUG_SIGSYS_BIT)
+ PREP("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_SIGSYS, r30)
+ DONE(DEBUG_SIGSYS_BIT)
GLOBAL(sigtrap)
- PREP("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_SIGTRAP, r30)
- DONE(DEBUG_SIGTRAP_BIT)
+ PREP("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_SIGTRAP, r30)
+ DONE(DEBUG_SIGTRAP_BIT)
GLOBAL(stepbpt)
- PREP("stepbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_STEPBPT, r30)
- DONE(DEBUG_SIGTRAP_BIT)
+ PREP("stepbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_STEPBPT, r30)
+ DONE(DEBUG_SIGTRAP_BIT)
GLOBAL(userbpt)
- PREP("userbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_USERBPT, r30)
- DONE(DEBUG_SIGTRAP_BIT)
+ PREP("userbpt", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_USERBPT, r30)
+ DONE(DEBUG_SIGTRAP_BIT)
#if DDB
- ASGLOBAL(break)
- PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_KDB_BREAK, r30)
- DONE(DEBUG_BREAK_BIT)
- ASGLOBAL(trace)
- PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_KDB_TRACE, r30)
- DONE(DEBUG_TRACE_BIT)
-
- GLOBAL(entry)
- PREP("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_KDB_ENTRY, r30)
- DONE(DEBUG_KDB_BIT)
+ASGLOBAL(break)
+ PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_KDB_BREAK, r30)
+ DONE(DEBUG_BREAK_BIT)
+
+ASGLOBAL(trace)
+ PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_KDB_TRACE, r30)
+ DONE(DEBUG_TRACE_BIT)
+
+GLOBAL(entry)
+ PREP("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_KDB_ENTRY, r30)
+ DONE(DEBUG_KDB_BIT)
#else /* else not DDB */
- ASGLOBAL(break)
- PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)
- DONE(DEBUG_BREAK_BIT)
- ASGLOBAL(trace)
- PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)
- DONE(DEBUG_TRACE_BIT)
- GLOBAL(entry)
- PREP("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap18x), T_UNKNOWNFLT, r30)
- DONE(DEBUG_KDB_BIT)
+ASGLOBAL(break)
+ PREP("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_UNKNOWNFLT, r30)
+ DONE(DEBUG_BREAK_BIT)
+
+ASGLOBAL(trace)
+ PREP("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_UNKNOWNFLT, r30)
+ DONE(DEBUG_TRACE_BIT)
+
+GLOBAL(entry)
+ PREP("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88100_trap, T_UNKNOWNFLT, r30)
+ DONE(DEBUG_KDB_BIT)
#endif /* DDB */
/*--------------------------------------------------------------------------*/
@@ -684,13 +775,13 @@ GLOBAL(error_handler)
#if 0 /* MVME188 */
#define IST_REG 0xfff84040 /* interrupt status addr */
/* check if it's a mvme188 */
- or.u r10, r0, hi16(_cputyp)
- ld r11, r10, lo16(_cputyp)
- cmp r10, r11, 0x188
+ or.u r10, r0, hi16(_brdtyp)
+ ld r11, r10, lo16(_brdtyp)
+ cmp r10, r11, BRD_188
bb1 ne, r10, 3f
or.u r10, r0, hi16(IST_REG) /* interrupt status register */
ld r11, r10, lo16(IST_REG)
- st r11, r31, REG_OFF(EF_MASK) /* put in EF_MASK for regdump */
+ st r11, r31, REG_OFF(EF_MASK) /* put in EF_MASK for regdump */
#endif /* MVME188 */
/*
* Cheap way to enable FPU and start shadowing again.
@@ -896,18 +987,18 @@ ASGLOBAL(ignore_data_exception)
/* the following jumps to "badaddr__return_nonzero" in below */
RTE
-#endif /* defined(MVME187) || defined (MVME188) */
+#endif /* m88100 */
-#ifdef MVME197
+#ifdef M88110
/*
* This is part of baddadr (below).
*/
-ASGLOBAL(m197_ignore_data_exception)
+ASGLOBAL(m88110_ignore_data_exception)
/******************************************************\
* SR0: pointer to the current thread structure *
- * SR1: previous FLAGS reg *
+ * SR1: previous FLAGS reg *
* SR2: free *
- * SR3: must presere *
+ * SR3: must preserve *
* FLAGS: CPU status flags *
\******************************************************/
xcr FLAGS, FLAGS, SR1 /* replace SR1, FLAGS */
@@ -915,21 +1006,21 @@ ASGLOBAL(m197_ignore_data_exception)
/*
* For more info, see badaddr() below.
*
- * We just want to jump to "badaddr__return_nonzero" below.
+ * We just want to jump to "m88110_badaddr__return_nonzero" below.
*
* We don't worry about trashing R2 here because we're
* jumping back to the function badaddr() where we're allowd
* to blast r2..r9 as we see fit.
*/
- or.u r2, r0, hi16(badaddr__return_nonzero)
- or r2, r2, lo16(badaddr__return_nonzero)
- stcr r2, SXIP /* Make it the next instruction to execute */
+ or.u r2, r0, hi16(m88110_badaddr__return_nonzero)
+ or r2, r2, lo16(m88110_badaddr__return_nonzero)
+ stcr r2, EXIP /* Make it the next instruction to execute */
- /* the following jumps to "badaddr__return_nonzero" in below */
+ /* the following jumps to "m88110_badaddr__return_nonzero" below */
NOP
RTE
-#endif /* MVME197 */
+#endif /* M88110 */
/*
@@ -954,10 +1045,10 @@ ASGLOBAL(m197_ignore_data_exception)
*/
GLOBAL(badaddr)
- /*
- * Disable interrupts ... don't want a context switch while we're
- * doing this! Also, save the old PSR in R8 to restore later.
- */
+ /*
+ * Disable interrupts ... don't want a context switch while we're
+ * doing this! Also, save the old PSR in R8 to restore later.
+ */
ldcr r8, PSR
set r4, r8, 1<PSR_INTERRUPT_DISABLE_BIT>
FLUSH_PIPELINE
@@ -1053,31 +1144,43 @@ ASGLOBAL(badaddr__return)
stcr r8, PSR
jmp r1
+ASGLOBAL(m88110_badaddr__return_nonzero)
+ /*
+ * On mc88110, we possibly took an exception
+ * and we have to clear DSR after the rte
+ * instruction clears the EFRZ bit in
+ * the PSR.
+ */
+ stcr r0, DSR /* Clear DSR reg on mc88110 */
+ stcr r0, DLAR /* Clear DLAR reg on mc88110 */
+ br.n badaddr__return_nonzero
+ stcr r0, DPAR /* Clear DPAR reg on mc88110 */
+
/*
******************************************************************************
******************************************************************************
******************************************************************************
*/
-#if defined(MVME187) || defined (MVME188)
+#ifdef M88100
ASGLOBAL(setup_phase_one)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread (if any, null if not) *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: saved copy of exception-time r1 *
- * SR3: must be preserved .. may be the exception-time stack *
- * r1: return address to calling exception handler *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * Decide where we're going to put the exception frame. *
- * Might be at the end of R31, SR3, or the thread's *
- * pcb. *
- \***************************************************************/
-
- /* Check if we are coming in from a FPU restart exception.
- If so, the pcb will be in SR3 */
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread (if any, null if not) *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: saved copy of exception-time r1 *
+ * SR3: must be preserved .. may be the exception-time stack *
+ * r1: return address to calling exception handler *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * Decide where we're going to put the exception frame. *
+ * Might be at the end of R31, SR3, or the thread's *
+ * pcb. *
+ \***************************************************************/
+
+ /* Check if we are coming in from a FPU restart exception.
+ If so, the pcb will be in SR3 */
NOP
xcr r1, r1, SR2
NOP
@@ -1085,23 +1188,23 @@ ASGLOBAL(setup_phase_one)
NOP
bb1 FLAG_ENABLING_FPU, FLAGS, use_SR3_pcb
- /* are we coming in from user mode? If so, pick up thread pcb */
+ /* are we coming in from user mode? If so, pick up thread pcb */
bb0 FLAG_FROM_KERNEL, FLAGS, pickup_stack
- /* Interrupt in kernel mode, not FPU restart */
+ /* Interrupt in kernel mode, not FPU restart */
ASGLOBAL(already_on_kernel_stack)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread (if any, null if not) *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: must be preserved; may be important for other exceptions *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * We're already on the kernel stack, but not having *
- * needed to use SR3. We can just make room on the *
- * stack (r31) for our exception frame. *
- \***************************************************************/
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread (if any, null if not) *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: must be preserved; may be important for other exceptions *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * We're already on the kernel stack, but not having *
+ * needed to use SR3. We can just make room on the *
+ * stack (r31) for our exception frame. *
+ \***************************************************************/
subu r31, r31, SIZEOF_EF /* r31 now our E.F. */
st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */
st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/
@@ -1115,35 +1218,35 @@ ASGLOBAL(already_on_kernel_stack)
ASGLOBAL(use_SR3_pcb)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread (if any, null if not) *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: must be preserved; exception-time stack pointer *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * An exception occurred while enabling the FPU. Since r31 *
- * is the user's r31 while enabling the FPU, we had put *
- * our pcb pointer into SR3, so make room from *
- * there for our stack pointer. *
- * We need to check if SR3 is the old stack pointer or the *
- * pointer off to the user pcb. If it pointing to the user *
- * pcb, we need to pick up the kernel stack. Otherwise *
- * we need to allocate a frame upon it. *
- * We look at the EPSR to see if it was from user mode *
- * Unfortunately, we have no registers free at the moment *
- * But we know register 0 in the pcb frame will always be *
- * zero, so we can use it as scratch storage. *
- * *
- * *
- \***************************************************************/
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread (if any, null if not) *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: must be preserved; exception-time stack pointer *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * An exception occured while enabling the FPU. Since r31 *
+ * is the user's r31 while enabling the FPU, we had put *
+ * our pcb pointer into SR3, so make room from *
+ * there for our stack pointer. *
+ * We need to check if SR3 is the old stack pointer or the *
+ * pointer off to the user pcb. If it pointing to the user *
+ * pcb, we need to pick up the kernel stack. Otherwise *
+ * we need to allocate a frame upon it. *
+ * We look at the EPSR to see if it was from user mode *
+ * Unfortunately, we have no registers free at the moment *
+ * But we know register 0 in the pcb frame will always be *
+ * zero, so we can use it as scratch storage. *
+ * *
+ * *
+ \***************************************************************/
xcr r30, r30, SR3 /* r30 = old exception frame */
st r1, r30, GENREG_OFF(0) /* free up r1 */
ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */
bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */
ld r1, r30, GENREG_OFF(0) /* restore r1 */
- /* we were in kernel mode - dump frame upon the stack */
+ /* we were in kernel mode - dump frame upon the stack */
st r0, r30, GENREG_OFF(0) /* repair old frame */
subu r30, r30, SIZEOF_EF /* r30 now our E.F. */
st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */
@@ -1156,10 +1259,10 @@ ASGLOBAL(use_SR3_pcb)
br.n have_pcb
xcr r30, r30, SR3 /* restore r30 */
1:
- /* we took an exception while restarting the FPU from user space.
- * Consequently, we never picked up a stack. Do so now.
- * R1 is currently free (saved in the exception frame pointed at by
- * r30) */
+ /* we took an exception while restarting the FPU from user space.
+ * Consequently, we never picked up a stack. Do so now.
+ * R1 is currently free (saved in the exception frame pointed at by
+ * r30) */
or.u r1, r0, hi16(_kstack)
ld r1, r1, lo16(_kstack)
addu r1, r1, USIZE-SIZEOF_EF
@@ -1174,21 +1277,21 @@ ASGLOBAL(use_SR3_pcb)
xcr r30, r30, SR3 /* restore r30 */
ASGLOBAL(pickup_stack)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: free *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * Since we're servicing an exception from user mode, we *
- * know that SR3 is free. We use it to free up a temp. *
- * register to be used in getting the thread's pcb *
- \***************************************************************/
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: free *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * Since we're servicing an exception from user mode, we *
+ * know that SR3 is free. We use it to free up a temp. *
+ * register to be used in getting the thread's pcb *
+ \***************************************************************/
stcr r31, SR3 /* save previous r31 */
- /* switch to the thread's kernel stack. */
+ /* switch to the thread's kernel stack. */
or.u r31, r0, hi16(_curpcb)
ld r31, r31, lo16(_curpcb)
addu r31, r31, PCB_USER_STATE /* point to user save area */
@@ -1196,7 +1299,7 @@ ASGLOBAL(pickup_stack)
st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/
ldcr r1, SR3 /* save previous r31 */
st r1, r31, GENREG_OFF(31)
- /*FALLTHROUGH */
+ /*FALLTHROUGH */
ASGLOBAL(have_pcb)
/***************** REGISTER STATUS BLOCK ***********************\
@@ -1235,9 +1338,9 @@ ASGLOBAL(have_pcb)
*/
#ifdef MVME188
/* check if it's a mvme188 */
- or.u TMP, r0, hi16(_cputyp)
- ld TMP2, TMP, lo16(_cputyp)
- cmp TMP, TMP2, 0x188
+ or.u TMP, r0, hi16(_brdtyp)
+ ld TMP2, TMP, lo16(_brdtyp)
+ cmp TMP, TMP2, BRD_188
bb1 ne, TMP, 5f
extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */
@@ -1397,43 +1500,43 @@ ASGLOBAL(do_DMT2_double)
1: clr TMP, TMP, TMP2
ASGLOBAL(DMT_check_finished)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: saved TMP *
- * r1: free *
- * TMP: possibly revised SSBR *
- * TMP2: free *
- * TMP3: free *
- * FLAGS: CPU status flags *
- * r31: exception frame *
- * Valid in the exception frame: *
- * Exception-time r1, r31, FLAGS. *
- * Exception-time TMP2, TMP3. *
- * Exception-time espr, sfip, snip, sxip. *
- * Dmt0. *
- * Other data pipeline control registers, if appropriate. *
- * Exception SR3, if appropriate. *
- \***************************************************************/
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: saved TMP *
+ * r1: free *
+ * TMP: possibly revised SSBR *
+ * TMP2: free *
+ * TMP3: free *
+ * FLAGS: CPU status flags *
+ * r31: exception frame *
+ * Valid in the exception frame: *
+ * Exception-time r1, r31, FLAGS. *
+ * Exception-time TMP2, TMP3. *
+ * Exception-time espr, sfip, snip, sxip. *
+ * Dmt0. *
+ * Other data pipeline control registers, if appropriate. *
+ * Exception SR3, if appropriate. *
+ \***************************************************************/
ldcr r1, SR2
jmp r1 /* return to allow the handler to clear more SSBR bits */
-#endif /* defined(MVME187) || defined (MVME188) */
+#endif /* m88100 */
/************************************************************************/
/************************************************************************/
ASGLOBAL(clear_FPi_ssbr_bit)
- /*
- * Clear floatingpont-imprecise ssbr bits.
- * Also, save appropriate FPU control registers to the E.F.
- *
- * r1: return address to calling exception handler
- * TMP : (possibly) revised ssbr
- * TMP2 : free
- * TMP3 : free
- */
+ /*
+ * Clear floatingpont-imprecise ssbr bits.
+ * Also, save appropriate FPU control registers to the E.F.
+ *
+ * r1: return address to calling exception handler
+ * TMP : (possibly) revised ssbr
+ * TMP2 : free
+ * TMP3 : free
+ */
fldcr TMP2, FPSR
fldcr TMP3, FPCR
st TMP2, r31, REG_OFF(EF_FPSR)
@@ -1449,10 +1552,10 @@ ASGLOBAL(clear_FPi_ssbr_bit)
st TMP2, r31, REG_OFF(EF_FPIT)
st TMP3, r31, REG_OFF(EF_FPRL)
- /*
- * We only need clear the bit in the SSBR for the
- * 2nd reg of a double result [see section 6.8.5]
- */
+ /*
+ * We only need clear the bit in the SSBR for the
+ * 2nd reg of a double result [see section 6.8.5]
+ */
#define FPIT_SIZE_BIT 10
bb0 FPIT_SIZE_BIT, TMP2, not_double_fpi
extu TMP2, TMP2, 5<0> /* get the reg. */
@@ -1468,407 +1571,404 @@ ASGLOBAL(not_double_fpi)
ASGLOBAL(clear_FPp_ssbr_bit)
- /*
- * Clear floating pont precise ssbr bits.
- * Also, save appropriate FPU control registers to the E.F.
- *
- * r1: return address to calling exception handler
- * TMP : (possibly) revised ssbr
- * TMP2 : free
- * TMP3 : free
- */
- fldcr TMP2, FPSR
- fldcr TMP3, FPCR
- st TMP2, r31, REG_OFF(EF_FPSR)
- st TMP3, r31, REG_OFF(EF_FPCR)
-
- fldcr TMP3, FPECR
- st TMP3, r31, REG_OFF(EF_FPECR)
- fldcr TMP2, FPHS1
- fldcr TMP3, FPHS2
- st TMP2, r31, REG_OFF(EF_FPHS1)
- st TMP3, r31, REG_OFF(EF_FPHS2)
-
- fldcr TMP2, FPLS1
- fldcr TMP3, FPLS2
- st TMP2, r31, REG_OFF(EF_FPLS1)
- st TMP3, r31, REG_OFF(EF_FPLS2)
-
- fldcr TMP2, FPPT
- st TMP2, r31, REG_OFF(EF_FPPT)
+ /*
+ * Clear floating pont precise ssbr bits.
+ * Also, save appropriate FPU control registers to the E.F.
+ *
+ * r1: return address to calling exception handler
+ * TMP : (possibly) revised ssbr
+ * TMP2 : free
+ * TMP3 : free
+ */
+ fldcr TMP2, FPSR
+ fldcr TMP3, FPCR
+ st TMP2, r31, REG_OFF(EF_FPSR)
+ st TMP3, r31, REG_OFF(EF_FPCR)
+
+ fldcr TMP3, FPECR
+ st TMP3, r31, REG_OFF(EF_FPECR)
+ fldcr TMP2, FPHS1
+ fldcr TMP3, FPHS2
+ st TMP2, r31, REG_OFF(EF_FPHS1)
+ st TMP3, r31, REG_OFF(EF_FPHS2)
+
+ fldcr TMP2, FPLS1
+ fldcr TMP3, FPLS2
+ st TMP2, r31, REG_OFF(EF_FPLS1)
+ st TMP3, r31, REG_OFF(EF_FPLS2)
+
+ fldcr TMP2, FPPT
+ st TMP2, r31, REG_OFF(EF_FPPT)
1:
#define FPPT_SIZE_BIT 5
- bb1.n FPPT_SIZE_BIT, TMP2, 2f
- extu TMP3, TMP2, 5<0> /* get FP operation dest reg */
- br.n 3f
- set TMP3, TMP3, 1<5> /* set size=1 -- clear one bit for "float" */
-2: set TMP3, TMP3, 1<6> /* set size=2 -- clear two bit for "double" */
-3:
- clr TMP, TMP, TMP3 /* clear bit(s) in ssbr. */
-4:
- jmp r1
+ bb1.n FPPT_SIZE_BIT, TMP2, 2f
+ extu TMP3, TMP2, 5<0> /* get FP operation dest reg */
+ br.n 3f
+ set TMP3, TMP3, 1<5> /* set size=1 -- clear one bit for "float" */
+2: set TMP3, TMP3, 1<6> /* set size=2 -- clear two bit for "double" */
+3: clr TMP, TMP, TMP3 /* clear bit(s) in ssbr. */
+4: jmp r1
/************************************************************************/
/************************************************************************/
-
ASGLOBAL(clear_dest_ssbr_bit)
- /*
- * There are various cases where an exception can leave the
- * destination register's bit in the SB set.
- * Examples:
- * misaligned or privilege exception on a LD or XMEM
- * DIV or DIVU by zero.
- *
- * I think that if the instruction is LD.D, then two bits must
- * be cleared.
- *
- * Even though there are a number of instructions/exception
- * combinations that could fire this code up, it's only required
- * to be run for the above cases. However, I don't think it'll
- * ever be a problem to run this in other cases (ST instructions,
- * for example), so I don't bother checking. If we had to check
- * for every possible instruction, this code would be much larger.
- *
- * The only checking, then, is to see if it's a LD.D or not.
- *
- * At the moment....
- * r1: return address to calling exception handler
- * TMP : (possibly) revised ssbr
- * TMP2 : free
- * TMP3 : free
- */
-
- ldcr TMP3, EPSR /* going to check: user or system memory? */
- ldcr TMP2, SXIP /* get the instruction's address */
- bb1.n PSR_SUPERVISOR_MODE_BIT, TMP3, 2f
- clr TMP2, TMP2, 2<0> /* get rid of valid and error bits. */
-
-1: /* user space load here */
+ /*
+ * There are various cases where an exception can leave the
+ * destination register's bit in the SB set.
+ * Examples:
+ * misaligned or privilege exception on a LD or XMEM
+ * DIV or DIVU by zero.
+ *
+ * I think that if the instruction is LD.D, then two bits must
+ * be cleared.
+ *
+ * Even though there are a number of instructions/exception
+ * combinations that could fire this code up, it's only required
+ * to be run for the above cases. However, I don't think it'll
+ * ever be a problem to run this in other cases (ST instructions,
+ * for example), so I don't bother checking. If we had to check
+ * for every possible instruction, this code would be much larger.
+ *
+ * The only checking, then, is to see if it's a LD.D or not.
+ *
+ * At the moment....
+ * r1: return address to calling exception handler
+ * TMP : (possibly) revised ssbr
+ * TMP2 : free
+ * TMP3 : free
+ */
+
+ ldcr TMP3, EPSR /* going to check: user or system memory? */
+ ldcr TMP2, SXIP /* get the instruction's address */
+ bb1.n PSR_SUPERVISOR_MODE_BIT, TMP3, 2f
+ clr TMP2, TMP2, 2<0> /* get rid of valid and error bits. */
+
+1: /* user space load here */
#if ERRATA__XXX_USR
- NOP
- ld.usr TMP2,TMP2, r0 /* get the instruction itself */
- NOP
- NOP
- NOP
- br 3f
+ NOP
+ ld.usr TMP2,TMP2, r0 /* get the instruction itself */
+ NOP
+ NOP
+ NOP
+ br 3f
#else
- br.n 3f
- ld.usr TMP2,TMP2, r0 /* get the instruction itself */
+ br.n 3f
+ ld.usr TMP2,TMP2, r0 /* get the instruction itself */
#endif
-2: /* system space load here */
- ld TMP2, TMP2, r0 /* get the instruction itself */
-
-3: /* now have the instruction..... */
- /*
- * Now see if it's a double load
- * There are three forms of double load [IMM16, scaled, unscaled],
- * which can be checked by matching against two templates:
- * -- 77776666555544443333222211110000 --
- * if (((instruction & 11111100000000000000000000000000) ==
- * 00010000000000000000000000000000) ;;
- * ((instruction & 11111100000000001111110011100000) ==
- * 11110100000000000001000000000000))
- * {
- * It's a load double, so
- * clear two SSBR bits.
- * } else {
- * It's not a load double.
- * Must be a load single, xmem, or st
- * Thus, clear one SSBR bit.
- * }
- */
- /* check the first pattern for ld.d */
- extu TMP3, TMP2, 16<16> /* get the upper 16 bits */
- mask TMP3, TMP3, 0xFC00 /* apply the mask */
- cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */
- bb1 eq, TMP3, misaligned_double
-
- /* still could be -- check the second pattern for ld.d */
- /* look at the upper 16 bits first */
- extu TMP3, TMP2, 16<16> /* get the upper 16 bits */
- mask TMP3, TMP3, 0xFC00 /* apply the mask */
- cmp TMP3, TMP3, 0xF400 /* if equal, it might be a load double */
- bb1 ne, TMP3, misaligned_single /* not equal, so must be single */
-
- /* now look at the lower 16 bits */
- extu TMP3, TMP2, 16<0> /* get the lower 16 bits */
- mask TMP3, TMP3, 0xFCE0 /* apply the mask */
- cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */
- bb1 eq, TMP3, misaligned_double
+2: /* system space load here */
+ ld TMP2, TMP2, r0 /* get the instruction itself */
+3: /* now have the instruction..... */
+ /*
+ * Now see if it's a double load
+ * There are three forms of double load [IMM16, scaled, unscaled],
+ * which can be checked by matching against two templates:
+ * -- 77776666555544443333222211110000 --
+ * if (((instruction & 11111100000000000000000000000000) ==
+ * 00010000000000000000000000000000) ;;
+ * ((instruction & 11111100000000001111110011100000) ==
+ * 11110100000000000001000000000000))
+ * {
+ * It's a load double, so
+ * clear two SSBR bits.
+ * } else {
+ * It's not a load double.
+ * Must be a load single, xmem, or st
+ * Thus, clear one SSBR bit.
+ * }
+ */
+ /* check the first pattern for ld.d */
+ extu TMP3, TMP2, 16<16> /* get the upper 16 bits */
+ mask TMP3, TMP3, 0xFC00 /* apply the mask */
+ cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */
+ bb1 eq, TMP3, misaligned_double
+
+ /* still could be -- check the second pattern for ld.d */
+ /* look at the upper 16 bits first */
+ extu TMP3, TMP2, 16<16> /* get the upper 16 bits */
+ mask TMP3, TMP3, 0xFC00 /* apply the mask */
+ cmp TMP3, TMP3, 0xF400 /* if equal, it might be a load double */
+ bb1 ne, TMP3, misaligned_single /* not equal, so must be single */
+
+ /* now look at the lower 16 bits */
+ extu TMP3, TMP2, 16<0> /* get the lower 16 bits */
+ mask TMP3, TMP3, 0xFCE0 /* apply the mask */
+ cmp TMP3, TMP3, 0x1000 /* if this is equal, it's a load double */
+ bb1 eq, TMP3, misaligned_double
+
ASGLOBAL(misaligned_single)
- extu TMP2, TMP2, 5<21> /* get the destination register */
- br.n 1f
- set TMP2, TMP2, 1<5> /* set size=1 */
+ extu TMP2, TMP2, 5<21> /* get the destination register */
+ br.n 1f
+ set TMP2, TMP2, 1<5> /* set size=1 */
ASGLOBAL(misaligned_double)
- extu TMP2, TMP2, 5<21> /* get the destination register */
- set TMP2, TMP2, 1<6> /* set size=2 -- clear two bit for "ld.d" */
+ extu TMP2, TMP2, 5<21> /* get the destination register */
+ set TMP2, TMP2, 1<6> /* set size=2 -- clear two bit for "ld.d" */
-1: jmp.n r1
- clr TMP, TMP, TMP2 /* clear bit(s) in ssbr. */
+1: jmp.n r1
+ clr TMP, TMP, TMP2 /* clear bit(s) in ssbr. */
/************************************************************************/
/************************************************************************/
-#if defined(MVME187) || defined (MVME188)
+#ifdef M88100
ASGLOBAL(setup_phase_two)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: saved return address to calling exception handler *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: free *
- * SR3: saved TMP *
- * r1: return address to calling exception handler *
- * TMP: possibly revised SSBR *
- * TMP2: free *
- * TMP3: free *
- * FLAGS: CPU status flags *
- * r31: our exception frame *
- * Valid in the exception frame: *
- * Exception-time r1, r31, FLAGS. *
- * Exception-time TMP2, TMP3. *
- * Exception-time espr, sfip, snip, sxip. *
- * Exception number (EF_VECTOR). *
- * Dmt0 *
- * Other data pipeline control registers, if appropriate. *
- * FPU control registers, if appropriate. *
- * Exception SR3, if appropriate. *
- *************************************************** *
- * immediate goal: *
- * restore the system to the exception-time state (except *
- * SR3 will be OUR stack pointer) so that we may resart the FPU. *
- \***************************************************************/
- /*stcr r1, SR0*/ /* save return address */
-
- stcr TMP, SSBR /* done with SSBR, TMP now free */
- RESTORE_TMP2 /* done with extra temp regs */
- RESTORE_TMP3 /* done with extra temp regs */
-
- /* Get the current PSR and modify for the rte to enable the FPU */
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: saved return address to calling exception handler *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: free *
+ * SR3: saved TMP *
+ * r1: return address to calling exception handler *
+ * TMP: possibly revised SSBR *
+ * TMP2: free *
+ * TMP3: free *
+ * FLAGS: CPU status flags *
+ * r31: our exception frame *
+ * Valid in the exception frame: *
+ * Exception-time r1, r31, FLAGS. *
+ * Exception-time TMP2, TMP3. *
+ * Exception-time espr, sfip, snip, sxip. *
+ * Exception number (EF_VECTOR). *
+ * Dmt0 *
+ * Other data pipeline control registers, if appropriate. *
+ * FPU control registers, if appropriate. *
+ * Exception SR3, if appropriate. *
+ *************************************************** *
+ * immediate goal: *
+ * restore the system to the exception-time state (except *
+ * SR3 will be OUR stack pointer) so that we may resart the FPU. *
+ \***************************************************************/
+ /*stcr r1, SR0*/ /* save return address */
+
+ stcr TMP, SSBR /* done with SSBR, TMP now free */
+ RESTORE_TMP2 /* done with extra temp regs */
+ RESTORE_TMP3 /* done with extra temp regs */
+
+ /* Get the current PSR and modify for the rte to enable the FPU */
#if 1
- ldcr TMP, PSR
- clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */
- clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */
- stcr TMP, EPSR
-
- /* the "+2" below is to set the VALID_BIT */
- or.u TMP, r0, hi16(fpu_enable +2)
- or TMP, TMP, lo16(fpu_enable +2)
- stcr TMP, SNIP /* jump to here fpu_enable */
- addu TMP, TMP, 4
- stcr TMP, SFIP /* and then continue after that */
+ ldcr TMP, PSR
+ clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */
+ clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */
+ stcr TMP, EPSR
+
+ /* the "+2" below is to set the VALID_BIT */
+ or.u TMP, r0, hi16(fpu_enable +2)
+ or TMP, TMP, lo16(fpu_enable +2)
+ stcr TMP, SNIP /* jump to here fpu_enable */
+ addu TMP, TMP, 4
+ stcr TMP, SFIP /* and then continue after that */
#else
- ldcr TMP, PSR
- or.u TMP, TMP, 0x8000 /* set supervisor mode */
- and TMP, TMP, 0xfff7 /* also enable shadowing */
- stcr TMP, EPSR
- stcr r0, SXIP /* clear valid bit */
- stcr r0, SNIP /* clear valid bit */
- or.u TMP, r0, hi16(fpu_enable)
- or TMP, TMP, lo16(fpu_enable)
- or TMP, TMP, 0x2 /* set the VALID_BIT and clear Exception bit */
- stcr TMP, SFIP /* jump to here fpu_enable */
+ ldcr TMP, PSR
+ or.u TMP, TMP, 0x8000 /* set supervisor mode */
+ and TMP, TMP, 0xfff7 /* also enable shadowing */
+ stcr TMP, EPSR
+ stcr r0, SXIP /* clear valid bit */
+ stcr r0, SNIP /* clear valid bit */
+ or.u TMP, r0, hi16(fpu_enable)
+ or TMP, TMP, lo16(fpu_enable)
+ or TMP, TMP, 0x2 /* set the VALID_BIT and clear Exception bit */
+ stcr TMP, SFIP /* jump to here fpu_enable */
#endif
setup_phase_two_cont:
- set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/
- xcr FLAGS, FLAGS, SR1
- st r1, r31, REG_OFF(EF_RET) /* save the return address */
- ld r1, r31, GENREG_OFF(1) /* get original r1 */
-
- xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */
- ld r31, r31, GENREG_OFF(31) /* get original r31 */
-
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: CPU flags *
- * SR2: free *
- * SR3: pointer to our exception frame (our stack pointer) *
- * r1 through r31: original exception-time values *
- * *
- * Valid in the exception frame: *
- * Exception-time FLAGS. *
- * Exception-time espr, sfip, snip, sxip. *
- * Exception number (EF_VECTOR). *
- * Dmt0 *
- * Other data pipeline control registers, if appropriate. *
- * FPU control registers, if appropriate. *
- * Exception SR3, if appropriate. *
- * Held temporarly in the exception frame: *
- * Return address to the calling excption handler. *
- *************************************************** *
- * immediate goal: *
- * Do an RTE to restart the fpu and jump to "fpu_enable" *
- * Another exception (or exceptions) may be raised in *
- * this, which is why FLAG_ENABLING_FPU is set in SR1. *
- \***************************************************************/
-
- RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */
-
+ set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/
+ xcr FLAGS, FLAGS, SR1
+ st r1, r31, REG_OFF(EF_RET) /* save the return address */
+ ld r1, r31, GENREG_OFF(1) /* get original r1 */
+
+ xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */
+ ld r31, r31, GENREG_OFF(31) /* get original r31 */
+
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: CPU flags *
+ * SR2: free *
+ * SR3: pointer to our exception frame (our stack pointer) *
+ * r1 through r31: original exception-time values *
+ * *
+ * Valid in the exception frame: *
+ * Exception-time FLAGS. *
+ * Exception-time espr, sfip, snip, sxip. *
+ * Exception number (EF_VECTOR). *
+ * Dmt0 *
+ * Other data pipeline control registers, if appropriate. *
+ * FPU control registers, if appropriate. *
+ * Exception SR3, if appropriate. *
+ * Held temporarly in the exception frame: *
+ * Return address to the calling excption handler. *
+ *************************************************** *
+ * immediate goal: *
+ * Do an RTE to restart the fpu and jump to "fpu_enable" *
+ * Another exception (or exceptions) may be raised in *
+ * this, which is why FLAG_ENABLING_FPU is set in SR1. *
+ \***************************************************************/
+
+ RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */
+
ASGLOBAL(fpu_enable)
- FLUSH_PIPELINE
- xcr TMP, TMP, SR3 /* get E.F. pointer */
- st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */
- or r31, TMP, r0 /* transfer E.F. pointer to r31 */
- ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/
-
- /* make sure that the FLAG_ENABLING_FPU bit is off */
- xcr FLAGS,FLAGS,SR1
- clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>
- xcr FLAGS,FLAGS,SR1
-
- xcr TMP, TMP, SR3 /* replace TMP, SR3 */
-
- /* now save all regs to the exception frame. */
- st.d r0 , r31, GENREG_OFF(0)
- st.d r2 , r31, GENREG_OFF(2)
- st.d r4 , r31, GENREG_OFF(4)
- st.d r6 , r31, GENREG_OFF(6)
- st.d r8 , r31, GENREG_OFF(8)
- st.d r10, r31, GENREG_OFF(10)
- st.d r12, r31, GENREG_OFF(12)
- st.d r14, r31, GENREG_OFF(14)
- st.d r16, r31, GENREG_OFF(16)
- st.d r18, r31, GENREG_OFF(18)
- st.d r20, r31, GENREG_OFF(20)
- st.d r22, r31, GENREG_OFF(22)
- st.d r24, r31, GENREG_OFF(24)
- st.d r26, r31, GENREG_OFF(26)
- st.d r28, r31, GENREG_OFF(28)
+ FLUSH_PIPELINE
+ xcr TMP, TMP, SR3 /* get E.F. pointer */
+ st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */
+ or r31, TMP, r0 /* transfer E.F. pointer to r31 */
+ ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/
+
+ /* make sure that the FLAG_ENABLING_FPU bit is off */
+ xcr FLAGS,FLAGS,SR1
+ clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>
+ xcr FLAGS,FLAGS,SR1
+
+ xcr TMP, TMP, SR3 /* replace TMP, SR3 */
+
+ /* now save all regs to the exception frame. */
+ st.d r0 , r31, GENREG_OFF(0)
+ st.d r2 , r31, GENREG_OFF(2)
+ st.d r4 , r31, GENREG_OFF(4)
+ st.d r6 , r31, GENREG_OFF(6)
+ st.d r8 , r31, GENREG_OFF(8)
+ st.d r10, r31, GENREG_OFF(10)
+ st.d r12, r31, GENREG_OFF(12)
+ st.d r14, r31, GENREG_OFF(14)
+ st.d r16, r31, GENREG_OFF(16)
+ st.d r18, r31, GENREG_OFF(18)
+ st.d r20, r31, GENREG_OFF(20)
+ st.d r22, r31, GENREG_OFF(22)
+ st.d r24, r31, GENREG_OFF(24)
+ st.d r26, r31, GENREG_OFF(26)
+ st.d r28, r31, GENREG_OFF(28)
#ifdef JEFF_DEBUG
- /* mark beginning of frame with notable value */
- or.u r20, r0, hi16(0x12345678)
- or r20, r20, lo16(0x12345678)
- st r20, r31, GENREG_OFF(0)
+ /* mark beginning of frame with notable value */
+ or.u r20, r0, hi16(0x12345678)
+ or r20, r20, lo16(0x12345678)
+ st r20, r31, GENREG_OFF(0)
#endif
-
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: free *
- * SR2: free *
- * SR3: previous exception-time SR3 *
- * r1: return address to the calling exception handler *
- * r2 through r30: free *
- * r31: our exception frame *
- * *
- * Valid in the exception frame: *
- * Exception-time r0 through r31. *
- * Exception-time FLAGS. *
- * Exception-time espr, sfip, snip, sxip. *
- * Exception number (EF_VECTOR). *
- * Dmt0 *
- * Other data pipeline control registers, if appropriate. *
- * FPU control registers, if appropriate. *
- * Exception SR3, if appropriate. *
- *************************************************** *
- * immediate goal: *
- * Pick up a stack if we came in from user mode. Put *
- * A copy of the exception frame pointer into r30 *
- * bump the stack a doubleword and write the exception *
- * frame pointer. *
- * if not an interrupt exception, *
- * Turn on interrupts and service any outstanding *
- * data access exceptions. *
- * Return to calling exception handler to *
- * service the exception. *
- \***************************************************************/
-
- /*
- * If it's not the interrupt exception, enable interrupts and
- * take care of any data access exceptions......
- *
+
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: free *
+ * SR2: free *
+ * SR3: previous exception-time SR3 *
+ * r1: return address to the calling exception handler *
+ * r2 through r30: free *
+ * r31: our exception frame *
+ * *
+ * Valid in the exception frame: *
+ * Exception-time r0 through r31. *
+ * Exception-time FLAGS. *
+ * Exception-time espr, sfip, snip, sxip. *
+ * Exception number (EF_VECTOR). *
+ * Dmt0 *
+ * Other data pipeline control registers, if appropriate. *
+ * FPU control registers, if appropriate. *
+ * Exception SR3, if appropriate. *
+ *************************************************** *
+ * immediate goal: *
+ * Pick up a stack if we came in from user mode. Put *
+ * A copy of the exception frame pointer into r30 *
+ * bump the stack a doubleword and write the exception *
+ * frame pointer. *
+ * if not an interrupt exception, *
+ * Turn on interrupts and service any outstanding *
+ * data access exceptions. *
+ * Return to calling exception handler to *
+ * service the exception. *
+ \***************************************************************/
+
+ /*
+ * If it's not the interrupt exception, enable interrupts and
+ * take care of any data access exceptions......
+ */
#if INTSTACK
- * If interrupt exception, switch to interrupt stack if not
- * already there. Else, switch to kernel stack.
+ /*
+ * If interrupt exception, switch to interrupt stack if not
+ * already there. Else, switch to kernel stack.
+ */
#endif
- */
- or r30, r0, r31 /* get a copy of the e.f. pointer */
- ld r2, r31, REG_OFF(EF_EPSR)
- bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */
+ or r30, r0, r31 /* get a copy of the e.f. pointer */
+ ld r2, r31, REG_OFF(EF_EPSR)
+ bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */
#if INTSTACK
- ld r3, r31, REG_OFF(EF_VECTOR)
- cmp r3, r3, 1 /* is interrupt ? */
- bb0 eq, r3, 2f
- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
- or r31, r31, lo16(_intstack_end)
- br 3f
+ ld r3, r31, REG_OFF(EF_VECTOR)
+ cmp r3, r3, 1 /* is interrupt ? */
+ bb0 eq, r3, 2f
+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
+ or r31, r31, lo16(_intstack_end)
+ br 3f
2:
#endif
- or.u r31, r0, hi16(_kstack)
- ld r31, r31, lo16(_kstack)
- addu r31, r31, USIZE /* point at proper end */
- br 3f
+ or.u r31, r0, hi16(_kstack)
+ ld r31, r31, lo16(_kstack)
+ addu r31, r31, USIZE /* point at proper end */
+ br 3f
1:
#if INTSTACK
- ld r3, r31, REG_OFF(EF_VECTOR)
- cmp r3, r3, 1 /* is interrupt ? */
- bb0 eq, r3, 3f /* no, we will stay on kern stack */
- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
- or r31, r31, lo16(_intstack_end)
+ ld r3, r31, REG_OFF(EF_VECTOR)
+ cmp r3, r3, 1 /* is interrupt ? */
+ bb0 eq, r3, 3f /* no, we will stay on kern stack */
+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
+ or r31, r31, lo16(_intstack_end)
#endif /* INTSTACK */
- /* This label is here for debugging */
+ /* This label is here for debugging */
exception_handler_has_ksp: global exception_handler_has_ksp
-3: /*
- here - r30 holds a pointer to the exception frame.
- r31 is a pointer to the kernel stack/interrupt stack.
- */
- subu r31, r31, 8 /* make some breathing space */
- st r30, r31, 0 /* store frame pointer on the stack */
+3: /*
+ * here - r30 holds a pointer to the exception frame.
+ * r31 is a pointer to the kernel stack/interrupt stack.
+ */
+ subu r31, r31, 8 /* make some breathing space */
+ st r30, r31, 0 /* store frame pointer on the stack */
#if DDB
- st r30, r31, 4 /* store it again for the debugger to recognize */
+ st r30, r31, 4 /* store it again for the debugger to recognize */
#endif /* DDB */
- ld r2, r30, REG_OFF(EF_VECTOR)
- bcnd.n eq0, r2, return_to_calling_exception_handler /* is error */
- ld r14, r30, REG_OFF(EF_RET)
- cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */
- bb1.n eq, r3, return_to_calling_exception_handler /* skip if so */
+ ld r2, r30, REG_OFF(EF_VECTOR)
+ bcnd.n eq0, r2, return_to_calling_exception_handler /* is error */
+ ld r14, r30, REG_OFF(EF_RET)
+ cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */
+ bb1.n eq, r3, return_to_calling_exception_handler /* skip if so */
#if DDB
- cmp r3, r2, 130 /* DDB break exception */
- bb1.n eq, r3, return_to_calling_exception_handler
-
- cmp r3, r2, 132 /* DDB entry exception */
- bb1.n eq, r3, return_to_calling_exception_handler
+ cmp r3, r2, 130 /* DDB break exception */
+ bb1.n eq, r3, return_to_calling_exception_handler
+ cmp r3, r2, 132 /* DDB entry exception */
+ bb1.n eq, r3, return_to_calling_exception_handler
#endif
- ldcr r2, PSR
- clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */
- stcr r2, PSR
+ ldcr r2, PSR
+ clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */
+ stcr r2, PSR
#if DDB
- FLUSH_PIPELINE
+ FLUSH_PIPELINE
#endif
- /* service any outstanding data pipeline stuff
- - check dmt0 anything outstanding?*/
+ /* service any outstanding data pipeline stuff
+ - check dmt0 anything outstanding?*/
- ld r3, r30, REG_OFF(EF_DMT0)
- bb0 DMT_VALID_BIT, r3, return_to_calling_exception_handler
+ ld r3, r30, REG_OFF(EF_DMT0)
+ bb0 DMT_VALID_BIT, r3, return_to_calling_exception_handler
-/*
- r30 can be clobbered by calls. So stuff its value into a
- preserved register, say r15. R14 is in use (see return_to_... below).
- */
- or r15, r0, r30
+ /*
+ r30 can be clobbered by calls. So stuff its value into a
+ preserved register, say r15. R14 is in use (see return_to_... below).
+ */
+ or r15, r0, r30
- CALL(_C_LABEL(trap18x), T_DATAFLT, r15)
- CALL(_data_access_emulation, r15, r0)
+ CALL(_m88100_trap, T_DATAFLT, r15)
+ CALL(_data_access_emulation, r15, r0)
-/* restore it... */
- or r30, r0, r15
+ /* restore it... */
+ or r30, r0, r15
- /* clear the dmt0 word in the E.F */
- st r0, r30, REG_OFF(EF_DMT0)
+ /* clear the dmt0 word in the E.F */
+ st r0, r30, REG_OFF(EF_DMT0)
ASGLOBAL(return_to_calling_exception_handler)
- jmp r14 /* loaded above */
-#endif /* defined(MVME187) || defined (MVME188) */
+ jmp r14 /* loaded above */
+#endif /* m88100 */
/*
@@ -1881,16 +1981,16 @@ ASGLOBAL(return_to_calling_exception_handler)
*/
ENTRY(proc_trampoline)
- ld r1,r31,0 /* load func */
- ld r2,r31,4 /* load proc pointer */
- jsr.n r1
- subu r31,r31,40 /* create stack space for function */
- addu r31,r31,48 /* stack space above + ksigframe */
- ld r1, r31,0 /* load pc */
- ld r2, r31,4 /* & proc pointer from switch frame */
- jsr.n r1
- addu r31,r31,8
- bsr _panic
+ ld r1,r31,0 /* load func */
+ ld r2,r31,4 /* load proc pointer */
+ jsr.n r1
+ subu r31,r31,40 /* create stack space for function */
+ addu r31,r31,48 /* stack space above + ksigframe */
+ ld r1, r31,0 /* load pc */
+ ld r2, r31,4 /* & proc pointer from switch frame */
+ jsr.n r1
+ addu r31,r31,8
+ bsr _panic
/*
* proc_do_uret
@@ -1901,10 +2001,10 @@ ENTRY(proc_trampoline)
*/
ENTRY(proc_do_uret)
- ld r3,r2,P_ADDR /* p->p_addr */
- addu r3,r3,PCB_USER_STATE /* p->p_addr.u_pcb.user_state */
- st r3,r31,0 /* put it on the stack */
- br return_from_exception_handler
+ ld r3,r2,P_ADDR /* p->p_addr */
+ addu r3,r3,PCB_USER_STATE /* p->p_addr.u_pcb.user_state */
+ st r3,r31,0 /* put it on the stack */
+ br return_from_exception_handler
ASGLOBAL(return_from_exception_handler)
GLOBAL(return_from_main)
@@ -1924,25 +2024,23 @@ GLOBAL(return_from_main)
* and thread_bootstrap in luna88k/locore.c.
*
*/
-#if (defined(MVME187) || defined(MVME188)) && defined(MVME197)
+#ifdef M88110
or.u r2, r0, hi16(_cputyp)
ld r3, r2, lo16(_cputyp)
- cmp r2, r3, 0x197
- bb1 eq, r2, m197_return_code
+ cmp r2, r3, CPU_88110
+ bb1 eq, r2, m88110_return_code
#endif
-
- /* 18x part for return_from_exception_handler() follows... */
-#if defined(MVME187) || defined(MVME188)
+#ifdef M88100
#define FPTR r14
ld FPTR, r31, 0 /* grab exception frame pointer */
ld r3, FPTR, REG_OFF(EF_DMT0)
bb0 DMT_VALID_BIT, r3, _check_ast /*[Oh well, nothing to do here] */
#if 1
- /*
- * This might happen for non-interrupts If the user sets DMT0
- * in an exception handler.........
- */
+ /*
+ * This might happen for non-interrupts If the user sets DMT0
+ * in an exception handler.........
+ */
ld r2, FPTR, REG_OFF(EF_VECTOR)
cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */
bb1 eq, r2, 1f
@@ -1959,86 +2057,63 @@ GLOBAL(return_from_main)
text
1:
#endif
- /*
- * If it's the interrupt exception, enable interrupt.
- * Take care of any data access exception...... 90/8/15 add by yama
- */
-
- /*
- * Is it ever possible to have interrupt exception while EPSR has
- * it disabled? I don't think so.. XXX nivas
- */
+ /*
+ * If it's the interrupt exception, enable interrupt.
+ * Take care of any data access exception...... 90/8/15 add by yama
+ */
+
+ /*
+ * Is it ever possible to have interrupt exception while EPSR has
+ * it disabled? I don't think so.. XXX nivas
+ */
ld r2, FPTR, REG_OFF(EF_VECTOR)
cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */
bb1 ne, r2, 1f /* If not so, skip */
- /* if EPSR has interrupts disabled, skip also */
+ /* if EPSR has interrupts disabled, skip also */
ld r2, FPTR, REG_OFF(EF_EPSR)
- bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */
+ bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */
ldcr r2, PSR
- clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */
- FLUSH_PIPELINE
+ clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */
+ FLUSH_PIPELINE
stcr r2, PSR
- 1:
+1:
ld r2, FPTR, REG_OFF(EF_DMT0)
bb0 DMT_VALID_BIT, r2, 2f
- /*
- * if there happens to be a data fault that hasn't been serviced yet,
- * go off and service that...
- */
- CALL(_C_LABEL(trap18x), T_DATAFLT, r30)
+ /*
+ * if there happens to be a data fault that hasn't been serviced yet,
+ * go off and service that...
+ */
+ CALL(_m88100_trap, T_DATAFLT, r30)
CALL(_data_access_emulation, r30, r0) /* really only 2 args */
-
- /* clear the dmt0 word in the E.F. */
+ /* clear the dmt0 word in the E.F. */
st r0 , FPTR, REG_OFF(EF_DMT0)
- 2:
+2:
br _check_ast
-#endif /* defined(MVME187) || defined(MVME188) */
- /* 197 part for return_from_exception_handler() follows... */
-#ifdef MVME197
-ASLOCAL(m197_return_code)
+#endif /* m88100 */
+
+#ifdef M88110
+ASLOCAL(m88110_return_code)
#define FPTR r14
ld FPTR, r31, 0 /* grab exception frame pointer */
- ld r3, FPTR, REG_OFF(EF_DSR)
- cmp r2, r3, 0x0
- bb1 eq, r2, _check_ast /*[Oh well, nothing to do here] */
-#if 1
/*
- * This might happen for non-interrupts If the user sets DMT0
- * in an exception handler.........
+ * If it's the interrupt exception, enable interrupt.
+ * If it's the data access exception, take care of it.
*/
- ld r2, FPTR, REG_OFF(EF_VECTOR)
- cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */
- bb1 eq, r2, 1f
- or.u r4, r0, hi16(2f)
- or r4, r4, lo16(2f)
-#if DDB
- CALL(_db_printf, r4, r0)
- tb0 0, r0, 132
-#endif
- br 1f
- data
-2: string "OOPS: DSR not zero and not interrupt.\n\000"
- align 8
- text
-1:
-#endif
- /*
- * If it's the interrupt exception, enable interrupt.
- * Take care of any data access exception...... 90/8/15 add by yama
- */
- /*
- * Is it ever possible to have interrupt exception while EPSR has
- * it disabled? I don't think so.. XXX nivas
- */
+ /*
+ * Is it ever possible to have interrupt exception while EPSR has
+ * it disabled? I don't think so.. XXX nivas
+ *
+ * On mc88110, you can. The NMI interrupt. aka ABORT. XXX smurph
+ */
ld r2, FPTR, REG_OFF(EF_VECTOR)
- cmp r2, r2, 1 /* interrupt is exception #1 ; Is an interrupt? */
- bb1 ne, r2, 1f /* If not so, skip */
+ cmp r2, r2, 1 /* Is it an interrupt? */
+ bb1 ne, r2, 1f /* If not, skip */
- /* if EPSR has interrupts disabled, skip also */
+ /* if EPSR has interrupts disabled, skip also */
ld r2, FPTR, REG_OFF(EF_EPSR)
bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if disabled */
ldcr r2, PSR
@@ -2046,20 +2121,22 @@ ASLOCAL(m197_return_code)
FLUSH_PIPELINE
stcr r2, PSR
1:
- ld r2, FPTR, REG_OFF(EF_DSR)
- cmp r3, r2, 0x0
- bb1 eq, r3, 2f
+ ld r2, FPTR, REG_OFF(EF_VECTOR)
+ cmp r3, r2, 3 /* Is it a data access exception? */
+ bb1 ne, r3, 2f /* If not, skip */
- /*
- * if there happens to be a data fault that hasn't been serviced yet,
- * go off and service that...
- */
- CALL(_C_LABEL(trap197), T_DATAFLT, r30)
+ /*
+ * if there happens to be a data fault that hasn't been serviced yet,
+ * go off and service that...
+ */
+ CALL(_m88110_trap, T_DATAFLT, r30)
- /* clear the dmt0 word in the E.F. */
+ /* clear the dsr word in the E.F. */
st r0, FPTR, REG_OFF(EF_DSR)
+ st r0, FPTR, REG_OFF(EF_DLAR)
+ st r0, FPTR, REG_OFF(EF_DPAR)
2:
-#endif /* MVME197 */
+#endif /* M88110 */
/*
* If the saved ipl is 0, then call dosoftint() to process soft
@@ -2071,17 +2148,18 @@ GLOBAL(check_ast)
ld r2, FPTR, REG_OFF(EF_EPSR) /* get pre-exception PSR */
bb1 PSR_INTERRUPT_DISABLE_BIT, r2, 1f /* skip if ints off */
ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */
- bcnd ne0, r2, 1f /* can't do softint's */
+ bcnd ne0, r2, 1f /* can't do softint's */
subu r31, r31, 32
bsr.n _setipl
or r2,r0,1
+ /* at ipl 1 now */
addu r31, r31, 32
bsr _dosoftint
/* is this needed? we are going to restore the ipl below XXX nivas */
subu r31, r31, 32
bsr.n _setipl
- or r2,r0,0 /* ints are enabled */
+ or r2,r0,0 /* ints are enabled */
addu r31, r31, 32
/* at ipl 0 now */
1:
@@ -2097,45 +2175,37 @@ GLOBAL(check_ast)
/*
* trap(AST,...) will service ast's.
*/
-
-#if defined(MVME187) || defined(MVME188)
-#if defined(MVME197)
+#ifdef M88110
or.u r2, r0, hi16(_cputyp)
ld r3, r2, lo16(_cputyp)
- cmp r2, r3, 0x197
- bb1 eq, r2, 1f
-#endif
- CALL(_C_LABEL(trap18x), T_ASTFLT, FPTR)
-#if defined(MVME197)
- br 2f
-1:
-#endif
-#endif
-#if defined(MVME197)
- CALL(_C_LABEL(trap197), T_ASTFLT, FPTR)
+ cmp r2, r3, CPU_88110
+ bb0 eq, r2, 2f
+ CALL(_m88110_trap, T_ASTFLT, FPTR)
+ br no_ast
2:
#endif
+#ifdef M88100
+ CALL(_m88100_trap, T_ASTFLT, FPTR)
+#endif
#if 0
/* assert that ipl is 0; if going back to user, it should be 0 */
bsr _getipl
- bcnd eq0, r2, 2f
+ bcnd eq0, r2, 3f
bsr _panic
-2:
+3:
#endif
ASGLOBAL(no_ast)
/* disable interrupts */
-
ldcr r1, PSR
set r1, r1, 1<PSR_INTERRUPT_DISABLE_BIT>
FLUSH_PIPELINE
stcr r1, PSR
/* now ready to return....*/
-
ld r2, FPTR, REG_OFF(EF_MASK) /* get pre-exception ipl */
bsr.n _setipl
subu r31, r31, 40
@@ -2145,7 +2215,6 @@ ASGLOBAL(no_ast)
* Transfer the frame pointer to r31, since we no longer need a stack.
* No page faults here, and interrupts are disabled.
*/
-
or r31, r0, FPTR
/* restore r1 later */
ld.d r2 , r31, GENREG_OFF(2)
@@ -2170,18 +2239,20 @@ ASGLOBAL(no_ast)
FLUSH_PIPELINE
stcr r1, PSR
+ /* reload the control regs*/
+#ifdef M88110
or.u r1, r0, hi16(_cputyp)
- ld r1, r1, lo16(_cputyp)
- cmp r1, r1, 0x197
+ ld r30, r1, lo16(_cputyp)
+ cmp r1, r30, CPU_88110
bb0 eq, r1, 1f
-
- ld r30, r31, REG_OFF(EF_SNIP)
- ld r1, r31, REG_OFF(EF_SXIP)
- stcr r30, SNIP
- stcr r1, SXIP
+ /* mc88110 needs the EXIP */
+ ld r30, r31, REG_OFF(EF_ENIP)
+ ld r1, r31, REG_OFF(EF_EXIP)
+ stcr r30, ENIP
+ stcr r1, EXIP
br 2f
-1:
- /* reload the control regs*/
+1:
+#endif
st r0, r31, REG_OFF(EF_IPFSR)
st r0, r31, REG_OFF(EF_DPFSR)
@@ -2212,171 +2283,173 @@ ASGLOBAL(no_ast)
ASGLOBAL(return_from_exception)
RTE
-#ifdef MVME197
+#ifdef M88110
/*#########################################################################*/
/*#### THE ACTUAL EXCEPTION HANDLER ENTRY POINTS - MVME197 ################*/
/*#########################################################################*/
/* unknown exception handler */
-GLOBAL(m197_unknown_handler)
- PREP2("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)
- DONE(DEBUG_UNKNOWN_BIT)
+GLOBAL(m88110_unknown_handler)
+ PREP2("unknown", 0, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_C_LABEL(m88110_trap), T_UNKNOWNFLT, r30)
+ DONE(DEBUG_UNKNOWN_BIT)
/* interrupt exception handler */
-GLOBAL(m197_interrupt_handler)
- PREP2("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_sbc_ext_int, 1, r30)
- DONE(DEBUG_INTERRUPT_BIT)
+GLOBAL(m88110_interrupt_handler)
+ PREP2("interrupt", 1, DEBUG_INTERRUPT_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_INT, r30)
+ DONE(DEBUG_INTERRUPT_BIT)
/* instruction access exception handler */
-GLOBAL(m197_instruction_access_handler)
- PREP2("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_INSTFLT, r30)
- DONE(DEBUG_INSTRUCTION_BIT)
-
+GLOBAL(m88110_instruction_access_handler)
+ PREP2("inst", 2, DEBUG_INSTRUCTION_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_INSTFLT, r30)
+ DONE(DEBUG_INSTRUCTION_BIT)
/*
* data access exception handler --
* See badaddr() below for info about Data_Precheck.
*/
-GLOBAL(m197_data_exception_handler)
- PREP2("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, M197_Data_Precheck)
- DONE(DEBUG_DATA_BIT)
+GLOBAL(m88110_data_exception_handler)
+ PREP2("data", 3, DEBUG_DATA_BIT, No_SSBR_Stuff, M88110_Data_Precheck)
+ DONE(DEBUG_DATA_BIT)
/* misaligned access exception handler */
-GLOBAL(m197_misaligned_handler)
- PREP2("misalign", 4, DEBUG_MISALIGN_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_MISALGNFLT, r30)
- DONE(DEBUG_MISALIGN_BIT)
+GLOBAL(m88110_misaligned_handler)
+ PREP2("misalign", 4, DEBUG_MISALIGN_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_MISALGNFLT, r30)
+ DONE(DEBUG_MISALIGN_BIT)
/* unimplemented opcode exception handler */
-GLOBAL(m197_unimplemented_handler)
- PREP2("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_ILLFLT, r30)
- DONE(DEBUG_UNIMPLEMENTED_BIT)
+GLOBAL(m88110_unimplemented_handler)
+ PREP2("unimp", 5, DEBUG_UNIMPLEMENTED_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_ILLFLT, r30)
+ DONE(DEBUG_UNIMPLEMENTED_BIT)
/* privilege exception handler */
-GLOBAL(m197_privilege_handler)
- PREP2("privilege", 6, DEBUG_PRIVILEGE_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_PRIVINFLT, r30)
- DONE(DEBUG_PRIVILEGE_BIT)
+GLOBAL(m88110_privilege_handler)
+ PREP2("privilege", 6, DEBUG_PRIVILEGE_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_PRIVINFLT, r30)
+ DONE(DEBUG_PRIVILEGE_BIT)
/*
* I'm not sure what the trap(T_BNDFLT,...) does, but it doesn't send
* a signal to the process...
*/
-GLOBAL(m197_bounds_handler)
- PREP2("bounds", 7, DEBUG_BOUNDS_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_BNDFLT, r30)
- DONE(DEBUG_BOUNDS_BIT)
+GLOBAL(m88110_bounds_handler)
+ PREP2("bounds", 7, DEBUG_BOUNDS_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_BNDFLT, r30)
+ DONE(DEBUG_BOUNDS_BIT)
/* integer divide-by-zero exception handler */
-GLOBAL(m197_divide_handler)
- PREP2("divide", 8, DEBUG_DIVIDE_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_ZERODIV, r30)
- DONE(DEBUG_DIVIDE_BIT)
+GLOBAL(m88110_divide_handler)
+ PREP2("divide", 8, DEBUG_DIVIDE_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_ZERODIV, r30)
+ DONE(DEBUG_DIVIDE_BIT)
/* integer overflow exception handelr */
-GLOBAL(m197_overflow_handler)
- PREP2("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_OVFFLT, r30)
- DONE(DEBUG_OVERFLOW_BIT)
+GLOBAL(m88110_overflow_handler)
+ PREP2("overflow", 9, DEBUG_OVERFLOW_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_OVFFLT, r30)
+ DONE(DEBUG_OVERFLOW_BIT)
/* Floating-point precise handler */
-GLOBAL(m197_fp_precise_handler)
- PREP2("FPU precise", 114, DEBUG_FPp_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_m88110_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/
- DONE(DEBUG_FPp_BIT)
+GLOBAL(m88110_fp_precise_handler)
+ PREP2("FPU precise", 114, DEBUG_FPp_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_Xfp_precise, r0, r30) /* call fp_precise(??, exception_frame)*/
+ DONE(DEBUG_FPp_BIT)
-/* MVME197 non-maskable interrupt handler */
-GLOBAL(m197_nonmaskable)
- PREP2("MVME197 non-mask", 11, DEBUG_NON_MASK_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_NON_MASK, r30)
- DONE(DEBUG_NON_MASK_BIT)
+/* MVME197 non-maskable interrupt handler (ABORT button) */
+GLOBAL(m88110_nonmaskable)
+ PREP2("MVME197 non-mask", 11, DEBUG_NON_MASK_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_NON_MASK, r30)
+ DONE(DEBUG_NON_MASK_BIT)
/* MVME197 data MMU read miss handler */
-GLOBAL(m197_data_read_miss)
- PREP2("MVME197 read miss", 12, DEBUG_197_READ_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_197_READ, r30)
- DONE(DEBUG_197_READ_BIT)
+GLOBAL(m88110_data_read_miss)
+ PREP2("MVME197 read miss", 12, DEBUG_197_READ_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_197_READ, r30)
+ DONE(DEBUG_197_READ_BIT)
/* MVME197 data MMU write miss handler */
-GLOBAL(m197_data_write_miss)
- PREP2("MVME197 write miss", 13, DEBUG_197_WRITE_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_197_WRITE, r30)
- DONE(DEBUG_197_WRITE_BIT)
+GLOBAL(m88110_data_write_miss)
+ PREP2("MVME197 write miss", 13, DEBUG_197_WRITE_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_197_WRITE, r30)
+ DONE(DEBUG_197_WRITE_BIT)
/* MVME197 inst MMU ATC miss handler */
-GLOBAL(m197_inst_atc_miss)
- PREP2("MVME197 inst miss", 14, DEBUG_197_INST_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_197_INST, r30)
- DONE(DEBUG_197_INST_BIT)
+GLOBAL(m88110_inst_atc_miss)
+ PREP2("MVME197 inst miss", 14, DEBUG_197_INST_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_197_INST, r30)
+ DONE(DEBUG_197_INST_BIT)
/* All standard system calls. */
-GLOBAL(m197_syscall_handler)
- PREP2("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)
- ld r13, r30, GENREG_OFF(13)
- CALL(_m197_syscall, r13, r30) /* system call no. is in r13 */
- DONE(DEBUG_SYSCALL_BIT)
+GLOBAL(m88110_syscall_handler)
+ PREP2("syscall", 128, DEBUG_SYSCALL_BIT, No_SSBR_Stuff, No_Precheck)
+ ld r13, r30, GENREG_OFF(13)
+ CALL(_m88110_syscall, r13, r30) /* system call no. is in r13 */
+ DONE(DEBUG_SYSCALL_BIT)
/* trap 496 comes here */
-GLOBAL(m197_bugtrap)
- PREP2("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)
- ld r9, r30, GENREG_OFF(9)
- CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */
- DONE(DEBUG_SYSCALL_BIT)
-
-GLOBAL(m197_sigsys)
- PREP2("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_SIGSYS, r30)
- DONE(DEBUG_SIGSYS_BIT)
-
-GLOBAL(m197_sigtrap)
- PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_SIGTRAP, r30)
- DONE(DEBUG_SIGTRAP_BIT)
-
-GLOBAL(m197_stepbpt)
- PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_STEPBPT, r30)
- DONE(DEBUG_SIGTRAP_BIT)
-
-GLOBAL(m197_userbpt)
- PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_USERBPT, r30)
- DONE(DEBUG_SIGTRAP_BIT)
+GLOBAL(m88110_bugtrap)
+ PREP2("bugsyscall", 496, DEBUG_BUGCALL_BIT, No_SSBR_Stuff, No_Precheck)
+ ld r9, r30, GENREG_OFF(9)
+ CALL(_bugsyscall, r9, r30) /* system call no. is in r9 */
+ DONE(DEBUG_BUGCALL_BIT)
+
+GLOBAL(m88110_sigsys)
+ PREP2("sigsys", 0, DEBUG_SIGSYS_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_SIGSYS, r30)
+ DONE(DEBUG_SIGSYS_BIT)
+
+GLOBAL(m88110_sigtrap)
+ PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_SIGTRAP, r30)
+ DONE(DEBUG_SIGTRAP_BIT)
+
+GLOBAL(m88110_stepbpt)
+ PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_STEPBPT, r30)
+ DONE(DEBUG_SIGTRAP_BIT)
+
+GLOBAL(m88110_userbpt)
+ PREP2("sigtrap", 0, DEBUG_SIGTRAP_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_USERBPT, r30)
+ DONE(DEBUG_SIGTRAP_BIT)
#if DDB
- GLOBAL(m197_break)
- PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_KDB_BREAK, r30)
- DONE(DEBUG_BREAK_BIT)
- GLOBAL(m197_trace)
- PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_KDB_TRACE, r30)
- DONE(DEBUG_TRACE_BIT)
- GLOBAL(m197_entry)
- PREP2("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_KDB_ENTRY, r30)
- DONE(DEBUG_KDB_BIT)
-
+GLOBAL(m88110_break)
+ PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_KDB_BREAK, r30)
+ DONE(DEBUG_BREAK_BIT)
+
+GLOBAL(m88110_trace)
+ PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_KDB_TRACE, r30)
+ DONE(DEBUG_TRACE_BIT)
+
+GLOBAL(m88110_entry)
+ PREP2("kdb", 132, DEBUG_KDB_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_KDB_ENTRY, r30)
+ DONE(DEBUG_KDB_BIT)
#else /* else not DDB */
- GLOBAL(m197_break)
- PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)
- DONE(DEBUG_BREAK_BIT)
- GLOBAL(m197_trace)
- PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)
- DONE(DEBUG_TRACE_BIT)
- GLOBAL(m197_entry)
- PREP2("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
- CALL(_C_LABEL(trap197), T_UNKNOWNFLT, r30)
- DONE(DEBUG_KDB_BIT)
+GLOBAL(m88110_break)
+ PREP2("break", 130, DEBUG_BREAK_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_UNKNOWNFLT, r30)
+ DONE(DEBUG_BREAK_BIT)
+
+GLOBAL(m88110_trace)
+ PREP2("trace", 131, DEBUG_TRACE_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_UNKNOWNFLT, r30)
+ DONE(DEBUG_TRACE_BIT)
+
+GLOBAL(m88110_entry)
+ PREP2("unknown", 132, DEBUG_UNKNOWN_BIT, No_SSBR_Stuff, No_Precheck)
+ CALL(_m88110_trap, T_UNKNOWNFLT, r30)
+ DONE(DEBUG_KDB_BIT)
#endif /* DDB */
-/*--------------------------------------------------------------------------*/
+/*--------------------------------------------------------------------------*/
/*
* The error exception handler.
* The error exception is raised when any other non-trap exception is raised
@@ -2388,7 +2461,36 @@ GLOBAL(m197_userbpt)
* We'll not worry about trashing r26-29 here,
* since they aren't generally used.
*/
-GLOBAL(m197_error_handler)
+GLOBAL(m88110_error_handler)
+ stcr r2, SRX
+ or r2, r0, 10
+ stcr r2, SR0
+ br.n _m88110_fatal
+ ldcr r2, SRX
+
+/*
+ * The reset exception handler.
+ * The reset exception is raised when the RST signal is asserted (machine
+ * is reset), the value of VBR is changed after exceptions are enabled,
+ * or when a jmp, br/bsr to addr 0 (accidents do happen :-)
+ *
+ * To tell the difference, you should check the value of r1 and the valid
+ * bit of SXIP.
+ *
+ * Upon a real reset, VBR is set to zero (0), so code must be at addr 0
+ * to handle it!!!
+ *
+ * This is totaly different than _error_handler. Shadowing might or
+ * might not be on.
+ * R1-R31 could tell u alot about what happend, so we'll save them.
+ *
+ * We'll not worry about trashing r26-29 here,
+ * since they aren't generally used.
+ */
+GLOBAL(m88110_reset_handler)
+ stcr r0, SR0
+ /* FALL THROUGH */
+GLOBAL(m88110_fatal)
/* pick up the slavestack */
or r26, r0, r31 /* save old stack */
or.u r31, r0, hi16(_intstack_end)
@@ -2402,15 +2504,15 @@ GLOBAL(m197_error_handler)
st r0, r0, r27
br.n 1b
addu r27, r27, 4 /* bump up */
-2: /* stack has been cleared */
+2: /* stack has been cleared */
- /* ensure that stack is 8-byte aligned */
+ /* ensure that stack is 8-byte aligned */
clr r31, r31, 3<0> /* round down to 8-byte boundary */
- /* create exception frame on stack */
+ /* create exception frame on stack */
subu r31, r31, SIZEOF_EF /* r31 now our E.F. */
- /* save old R31 and other R registers */
+ /* save old R31 and other R registers */
st.d r0 , r31, GENREG_OFF(0)
st.d r2 , r31, GENREG_OFF(2)
st.d r4 , r31, GENREG_OFF(4)
@@ -2426,17 +2528,61 @@ GLOBAL(m197_error_handler)
st.d r24, r31, GENREG_OFF(24)
st r30, r31, GENREG_OFF(30)
st r26, r31, GENREG_OFF(31)
+
+ /* vector is put in SRO (either 0 or 10 at this point) */
+ ldcr r10, SR0
+ st r10, r31, REG_OFF(EF_VECTOR)
+ cmp r10, r10, 0 /* Is it the reset exception? */
+ bb1.n ne, r10, 1f /* If not, skip. */
/* save shadow registers (are OLD if error_handler, though) */
ldcr r10, EPSR
st r10, r31, REG_OFF(EF_EPSR)
- ldcr r10, SXIP
- st r10, r31, REG_OFF(EF_SXIP)
- ldcr r10, SNIP
- st r10, r31, REG_OFF(EF_SNIP)
+ ldcr r10, EXIP
+ st r10, r31, REG_OFF(EF_EXIP)
+ ldcr r10, ENIP
+ st r10, r31, REG_OFF(EF_ENIP)
+ ldcr r10, DSR
+ st r10, r31, REG_OFF(EF_DSR)
+ ldcr r10, DLAR
+ st r10, r31, REG_OFF(EF_DLAR)
+ ldcr r10, DPAR
+ st r10, r31, REG_OFF(EF_DPAR)
+ ldcr r10, ISR
+ st r10, r31, REG_OFF(EF_ISR)
+ ldcr r10, ILAR
+ st r10, r31, REG_OFF(EF_ILAR)
+ ldcr r10, IPAR
+ st r10, r31, REG_OFF(EF_IPAR)
ldcr r10, SR1
+ br.n 2f
st r10, r31, REG_OFF(EF_MODE)
+1:
+ /* retrieve saved shadow registers for error_handler, though) */
+ GET_R(r10, OFF_EPSR)
+ st r10, r31, REG_OFF(EF_EPSR)
+ GET_R(r10, OFF_EXIP)
+ st r10, r31, REG_OFF(EF_EXIP)
+ GET_R(r10, OFF_ENIP)
+ st r10, r31, REG_OFF(EF_ENIP)
+ GET_R(r10, OFF_DSR)
+ st r10, r31, REG_OFF(EF_DSR)
+ GET_R(r10, OFF_DLAR)
+ st r10, r31, REG_OFF(EF_DLAR)
+ GET_R(r10, OFF_DPAR)
+ st r10, r31, REG_OFF(EF_DPAR)
+ GET_R(r10, OFF_ISR)
+ st r10, r31, REG_OFF(EF_ISR)
+ GET_R(r10, OFF_ILAR)
+ st r10, r31, REG_OFF(EF_ILAR)
+ GET_R(r10, OFF_IPAR)
+ st r10, r31, REG_OFF(EF_IPAR)
+ GET_R(r10, OFF_VEC)
+ st r10, r31, REG_OFF(EF_VECTOR)
+ ldcr r10, SR1
+ st r10, r31, REG_OFF(EF_MODE)
+2:
/* shove sr2 into EF_FPLS1 */
ldcr r10, SR2
st r10, r31, REG_OFF(EF_FPLS1)
@@ -2445,8 +2591,6 @@ GLOBAL(m197_error_handler)
ldcr r10, SR3
st r10, r31, REG_OFF(EF_FPHS2)
- /* error vector is zippo numero el'zeroooo */
- st r0, r31, REG_OFF(EF_VECTOR)
/*
* Cheap way to enable FPU and start shadowing again.
@@ -2468,8 +2612,8 @@ GLOBAL(m197_error_handler)
or r20, r20, lo16(0x87654321)
st r20, r31, 0x04
st r20, r31, 0x00
-
- CALL(_error_fault, r30, r30)
+
+ CALL(_error_fatal, r30, r30)
/* TURN INTERUPTS back on */
ldcr r1, PSR
@@ -2477,549 +2621,463 @@ GLOBAL(m197_error_handler)
stcr r1, PSR
FLUSH_PIPELINE
-ASGLOBAL(m197_error_loop)
- bsr m197_error_loop
+ASGLOBAL(m88110_error_loop)
+ bsr m88110_error_loop
/* never returns*/
-/*
- * The reset exception handler.
- * The reset exception is raised when the RST signal is asserted (machine
- * is reset), the value of VBR is changed after exceptions are enabled,
- * or when a jmp, br/bsr to addr 0 (accidents do happen :-)
- *
- * To tell the difference, you should check the value of r1 and the valid
- * bit of SXIP.
- *
- * Upon a real reset, VBR is set to zero (0), so code must be at addr 0
- * to handle it!!!
- *
- * This is totaly different than _error_handler. Shadowing might or
- * might not be on.
- * R1-R31 could tell u alot about what happend, so we'll save them.
- *
- * We'll not worry about trashing r26-29 here,
- * since they aren't generally used.
- */
-GLOBAL(m197_reset_handler)
- /* pick up the slavestack */
- or r26, r0, r31 /* save old stack */
- or.u r31, r0, hi16(_intstack_end)
- or r31, r31, lo16(_intstack_end)
-
- /* zero the stack, so we'll know what we're lookin' at */
- or.u r27, r0, hi16(_intstack)
- or r27, r27, lo16(_intstack)
-1: cmp r28, r27, r31
- bb1 ge, r28, 2f /* branch if at the end of the stack */
- st r0, r0, r27
- br.n 1b
- addu r27, r27, 4 /* bump up */
-2: /* stack has been cleared */
-
- /* ensure that stack is 8-byte aligned */
- clr r31, r31, 3<0> /* round down to 8-byte boundary */
-
- /* create exception frame on stack */
- subu r31, r31, SIZEOF_EF /* r31 now our E.F. */
-
- /* save old R31 and other R registers */
- st.d r0 , r31, GENREG_OFF(0)
- st.d r2 , r31, GENREG_OFF(2)
- st.d r4 , r31, GENREG_OFF(4)
- st.d r6 , r31, GENREG_OFF(6)
- st.d r8 , r31, GENREG_OFF(8)
- st.d r10, r31, GENREG_OFF(10)
- st.d r12, r31, GENREG_OFF(12)
- st.d r14, r31, GENREG_OFF(14)
- st.d r16, r31, GENREG_OFF(16)
- st.d r18, r31, GENREG_OFF(18)
- st.d r20, r31, GENREG_OFF(20)
- st.d r22, r31, GENREG_OFF(22)
- st.d r24, r31, GENREG_OFF(24)
- st r30, r31, GENREG_OFF(30)
- st r26, r31, GENREG_OFF(31)
-
- /* save shadow registers */
- ldcr r10, EPSR
- st r10, r31, REG_OFF(EF_EPSR)
- ldcr r10, SXIP
- st r10, r31, REG_OFF(EF_SXIP)
- ldcr r10, SNIP
- st r10, r31, REG_OFF(EF_SNIP)
- ldcr r10, SR1
- st r10, r31, REG_OFF(EF_MODE)
-
- /* shove sr2 into EF_FPLS1 */
- ldcr r10, SR2
- st r10, r31, REG_OFF(EF_FPLS1)
-
- /* shove sr3 into EF_FPHS2 */
- ldcr r10, SR3
- st r10, r31, REG_OFF(EF_FPHS2)
-
- /* error vector is zippo numero el'zeroooo */
- st r0, r31, REG_OFF(EF_VECTOR)
-
+ASGLOBAL(m88110_setup_phase_one)
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread (if any, null if not) *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: saved copy of exception-time r1 *
+ * SR3: must be preserved .. may be the exception-time stack *
+ * r1: return address to calling exception handler *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * Decide where we're going to put the exception frame. *
+ * Might be at the end of R31, SR3, or the thread's *
+ * pcb. *
+ \***************************************************************/
+
+ /* Check if we are coming in from a FPU restart exception.
+ If so, the pcb will be in SR3 */
+ NOP
+ xcr r1, r1, SR2
+ NOP
+ NOP
+ NOP
+
+ bb1 FLAG_ENABLING_FPU, FLAGS, m88110_use_SR3_pcb
+ /* are we coming in from user mode? If so, pick up thread pcb */
+ bb0 FLAG_FROM_KERNEL, FLAGS, m88110_pickup_stack
+
+ /* Interrupt in kernel mode, not FPU restart */
+ASGLOBAL(m88110_already_on_kernel_stack)
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread (if any, null if not) *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: must be preserved; may be important for other exceptions *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * We're already on the kernel stack, but not having *
+ * needed to use SR3. We can just make room on the *
+ * stack (r31) for our exception frame. *
+ \***************************************************************/
+ subu r31, r31, SIZEOF_EF /* r31 now our E.F. */
+ st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */
+ st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/
+
+ ldcr r1, SR3 /* save previous SR3 */
+ st r1, r31, REG_OFF(EF_SR3)
+
+ addu r1, r31, SIZEOF_EF /* save previous r31 */
+ br.n m88110_have_pcb
+ st r1, r31, GENREG_OFF(31)
+
+
+ASGLOBAL(m88110_use_SR3_pcb)
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread (if any, null if not) *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: must be preserved; exception-time stack pointer *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * An exception occured while enabling the FPU. Since r31 *
+ * is the user's r31 while enabling the FPU, we had put *
+ * our pcb pointer into SR3, so make room from *
+ * there for our stack pointer. *
+ * We need to check if SR3 is the old stack pointer or the *
+ * pointer off to the user pcb. If it pointing to the user *
+ * pcb, we need to pick up the kernel stack. Otherwise *
+ * we need to allocate a frame upon it. *
+ * We look at the EPSR to see if it was from user mode *
+ * Unfortunately, we have no registers free at the moment *
+ * But we know register 0 in the pcb frame will always be *
+ * zero, so we can use it as scratch storage. *
+ * *
+ * *
+ \***************************************************************/
+ xcr r30, r30, SR3 /* r30 = old exception frame */
+ st r1, r30, GENREG_OFF(0) /* free up r1 */
+ ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */
+ bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */
+ ld r1, r30, GENREG_OFF(0) /* restore r1 */
+ /* we were in kernel mode - dump frame upon the stack */
+ st r0, r30, GENREG_OFF(0) /* repair old frame */
+ subu r30, r30, SIZEOF_EF /* r30 now our E.F. */
+ st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */
+ st r1, r30, GENREG_OFF(1) /* save prev. r1 (now r1 free) */
+
+ st r31, r30, GENREG_OFF(31) /* save previous r31 */
+ or r31, r0, r30 /* make r31 our pointer. */
+ addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */
+ st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */
+ br.n m88110_have_pcb
+ xcr r30, r30, SR3 /* restore r30 */
+1:
+ /* we took an exception while restarting the FPU from user space.
+ * Consequently, we never picked up a stack. Do so now.
+ * R1 is currently free (saved in the exception frame pointed at by
+ * r30) */
+ or.u r1, r0, hi16(_kstack)
+ ld r1, r1, lo16(_kstack)
+ addu r1, r1, USIZE-SIZEOF_EF
+ st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */
+ st r31, r1, GENREG_OFF(31) /* store r31 - now free */
+ st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */
+ or r31, r1, r0 /* make r31 our exception frame pointer */
+ ld r1, r30, GENREG_OFF(0) /* restore old r1 */
+ st r0, r30, GENREG_OFF(0) /* repair that frame */
+ st r1, r31, GENREG_OFF(1) /* store r1 in its proper place */
+ br.n m88110_have_pcb
+ xcr r30, r30, SR3 /* restore r30 */
+
+ASGLOBAL(m88110_pickup_stack)
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: free *
+ * FLAGS: CPU status flags *
+ *************************************************** *
+ * immediate goal: *
+ * Since we're servicing an exception from user mode, we *
+ * know that SR3 is free. We use it to free up a temp. *
+ * register to be used in getting the thread's pcb *
+ \***************************************************************/
+ stcr r31, SR3 /* save previous r31 */
+
+ /* switch to the thread's kernel stack. */
+ or.u r31, r0, hi16(_curpcb)
+ ld r31, r31, lo16(_curpcb)
+ addu r31, r31, PCB_USER_STATE /* point to user save area */
+ st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */
+ st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/
+ ldcr r1, SR3 /* save previous r31 */
+ st r1, r31, GENREG_OFF(31)
+ /*FALLTHROUGH */
+
+ASGLOBAL(m88110_have_pcb)
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: return address to the calling exception handler *
+ * SR3: free *
+ * r1: free *
+ * FLAGS: CPU status flags *
+ * r31: our exception frame *
+ * Valid in the exception frame: *
+ * Exception-time r1, r31, FLAGS. *
+ * Exception SR3, if appropriate. *
+ *************************************************** *
+ * immediate goal: *
+ * Save the shadow registers that need to be saved to *
+ * the exception frame. *
+ \***************************************************************/
+ stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */
+ SAVE_TMP2
+ SAVE_TMP3
+
+ /* save some exception-time registers to the exception frame */
+ ldcr TMP, EPSR
+ st TMP, r31, REG_OFF(EF_EPSR)
+ ldcr TMP2, EXIP
+ st TMP2, r31, REG_OFF(EF_EXIP)
+ bb0.n 0, TMP2, 1f
+ /* The instruction was NOT in the delay slot, zero ENIP. */
+ st r0, r31, REG_OFF(EF_ENIP)
+ /* The instruction was in the delay slot, save ENIP. */
+ ldcr TMP3, ENIP
+ st TMP3, r31, REG_OFF(EF_ENIP)
+1:
+ /* NO SFIP on mc88110, zero it */
+ st r0, r31, REG_OFF(EF_SFIP)
+
+ /* get and store the cpu number */
+ extu TMP, FLAGS, FLAG_CPU_FIELD_WIDTH<0> /* TMP = cpu# */
+ st TMP, r31, REG_OFF(EF_CPU)
+
/*
- * Cheap way to enable FPU and start shadowing again.
+ * Save Pbus fault status register from data and inst CMMU.
*/
- ldcr r10, PSR
- clr r10, r10, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */
- clr r10, r10, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */
-
- stcr r10, PSR /* bang */
- FLUSH_PIPELINE
-
- /* put pointer to regs into r30... r31 will become a simple stack */
- or r30, r31, r0
-
- subu r31, r31, 0x10 /* make some breathing space */
- st r30, r31, 0x0c /* store frame pointer on the st */
- st r30, r31, 0x08 /* store again for the debugger to recognize */
- or.u r20, r0, hi16(0x87654321)
- or r20, r20, lo16(0x87654321)
- st r20, r31, 0x04
- st r20, r31, 0x00
-
- CALL(_error_reset, r30, r30)
-
- /* TURN INTERUPTS back on */
- ldcr r1, PSR
- clr r1, r1, 1<PSR_INTERRUPT_DISABLE_BIT>
- stcr r1, PSR
- FLUSH_PIPELINE
-
-ASGLOBAL(m197_error_loop2)
- bsr m197_error_loop2
-/* never returns*/
-
-
-ASGLOBAL(m197_setup_phase_one)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread (if any, null if not) *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: saved copy of exception-time r1 *
- * SR3: must be preserved .. may be the exception-time stack *
- * r1: return address to calling exception handler *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * Decide where we're going to put the exception frame. *
- * Might be at the end of R31, SR3, or the thread's *
- * pcb. *
- \***************************************************************/
-
- /* Check if we are coming in from a FPU restart exception.
- If so, the pcb will be in SR3 */
- NOP
- xcr r1, r1, SR2
- NOP
- NOP
- NOP
-
- bb1 FLAG_ENABLING_FPU, FLAGS, m197_use_SR3_pcb
- /* are we coming in from user mode? If so, pick up thread pcb */
- bb0 FLAG_FROM_KERNEL, FLAGS, m197_pickup_stack
-
- /* Interrupt in kernel mode, not FPU restart */
-ASGLOBAL(m197_already_on_kernel_stack)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread (if any, null if not) *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: must be preserved; may be important for other exceptions *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * We're already on the kernel stack, but not having *
- * needed to use SR3. We can just make room on the *
- * stack (r31) for our exception frame. *
- \***************************************************************/
- subu r31, r31, SIZEOF_EF /* r31 now our E.F. */
- st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */
- st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/
-
- ldcr r1, SR3 /* save previous SR3 */
- st r1, r31, REG_OFF(EF_SR3)
-
- addu r1, r31, SIZEOF_EF /* save previous r31 */
- br.n m197_have_pcb
- st r1, r31, GENREG_OFF(31)
-
-
-ASGLOBAL(m197_use_SR3_pcb)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread (if any, null if not) *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: must be preserved; exception-time stack pointer *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * An exception occurred while enabling the FPU. Since r31 *
- * is the user's r31 while enabling the FPU, we had put *
- * our pcb pointer into SR3, so make room from *
- * there for our stack pointer. *
- * We need to check if SR3 is the old stack pointer or the *
- * pointer off to the user pcb. If it pointing to the user *
- * pcb, we need to pick up the kernel stack. Otherwise *
- * we need to allocate a frame upon it. *
- * We look at the EPSR to see if it was from user mode *
- * Unfortunately, we have no registers free at the moment *
- * But we know register 0 in the pcb frame will always be *
- * zero, so we can use it as scratch storage. *
- * *
- * *
- \***************************************************************/
- xcr r30, r30, SR3 /* r30 = old exception frame */
- st r1, r30, GENREG_OFF(0) /* free up r1 */
- ld r1, r30, REG_OFF(EF_EPSR) /* get back the epsr */
- bb0.n PSR_SUPERVISOR_MODE_BIT, r1, 1f /* if user mode */
- ld r1, r30, GENREG_OFF(0) /* restore r1 */
- /* we were in kernel mode - dump frame upon the stack */
- st r0, r30, GENREG_OFF(0) /* repair old frame */
- subu r30, r30, SIZEOF_EF /* r30 now our E.F. */
- st FLAGS,r30, REG_OFF(EF_FLAGS) /* save flags */
- st r1, r30, GENREG_OFF(1) /* save prev. r1 (now r1 free) */
-
- st r31, r30, GENREG_OFF(31) /* save previous r31 */
- or r31, r0, r30 /* make r31 our pointer. */
- addu r30, r30, SIZEOF_EF /* r30 now has previous SR3 */
- st r30, r31, REG_OFF(EF_SR3) /* save previous SR3 */
- br.n m197_have_pcb
- xcr r30, r30, SR3 /* restore r30 */
-1:
- /* we took an exception while restarting the FPU from user space.
- * Consequently, we never picked up a stack. Do so now.
- * R1 is currently free (saved in the exception frame pointed at by
- * r30) */
- or.u r1, r0, hi16(_kstack)
- ld r1, r1, lo16(_kstack)
- addu r1, r1, USIZE-SIZEOF_EF
- st FLAGS,r1, REG_OFF(EF_FLAGS) /* store flags */
- st r31, r1, GENREG_OFF(31) /* store r31 - now free */
- st r30, r1, REG_OFF(EF_SR3) /* store old SR3 (pcb) */
- or r31, r1, r0 /* make r31 our exception frame pointer */
- ld r1, r30, GENREG_OFF(0) /* restore old r1 */
- st r0, r30, GENREG_OFF(0) /* repair that frame */
- st r1, r31, GENREG_OFF(1) /* store r1 in its proper place */
- br.n m197_have_pcb
- xcr r30, r30, SR3 /* restore r30 */
-
-ASGLOBAL(m197_pickup_stack)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: free *
- * FLAGS: CPU status flags *
- *************************************************** *
- * immediate goal: *
- * Since we're servicing an exception from user mode, we *
- * know that SR3 is free. We use it to free up a temp. *
- * register to be used in getting the thread's pcb *
- \***************************************************************/
- stcr r31, SR3 /* save previous r31 */
-
- /* switch to the thread's kernel stack. */
- or.u r31, r0, hi16(_curpcb)
- ld r31, r31, lo16(_curpcb)
- addu r31, r31, PCB_USER_STATE /* point to user save area */
- st FLAGS,r31, REG_OFF(EF_FLAGS) /* save flags */
- st r1, r31, GENREG_OFF(1) /* save prev. r1 (now r1 free)*/
- ldcr r1, SR3 /* save previous r31 */
- st r1, r31, GENREG_OFF(31)
- /*FALLTHROUGH */
-
-ASGLOBAL(m197_have_pcb)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: return address to the calling exception handler *
- * SR3: free *
- * r1: free *
- * FLAGS: CPU status flags *
- * r31: our exception frame *
- * Valid in the exception frame: *
- * Exception-time r1, r31, FLAGS. *
- * Exception SR3, if appropriate. *
- *************************************************** *
- * immediate goal: *
- * Save the shadow registers that need to be saved to *
- * the exception frame. *
- \***************************************************************/
- stcr TMP, SR3 /* free up TMP, TMP2, TMP3 */
- SAVE_TMP2
- SAVE_TMP3
-
- /* save some exception-time registers to the exception frame */
- ldcr TMP, EPSR
- st TMP, r31, REG_OFF(EF_EPSR)
- ldcr TMP3, SNIP
- st TMP3, r31, REG_OFF(EF_SNIP)
-
- /*
- * Save Pbus fault status register from data and inst CMMU.
- */
-
- ldcr TMP, ISR
- ldcr TMP2, ILAR
- ldcr TMP3, IPAR
- st TMP, r31, REG_OFF(EF_ISR)
- st TMP2, r31, REG_OFF(EF_ILAR)
- st TMP3, r31, REG_OFF(EF_IPAR)
- ldcr TMP, ISAP
- st TMP, r31, REG_OFF(EF_DMT0) /* hack ef! */
- ldcr TMP, DSR
- ldcr TMP2, DLAR
- ldcr TMP3, DPAR
- st TMP, r31, REG_OFF(EF_DSR)
- st TMP2, r31, REG_OFF(EF_DLAR)
- st TMP3, r31, REG_OFF(EF_DPAR)
- ldcr TMP, DSAP
- st TMP, r31, REG_OFF(EF_DMT1) /* hack ef! */
- ldcr TMP2, SXIP
- st TMP2, r31, REG_OFF(EF_SXIP)
-
- ldcr r1, SR2
- jmp r1 /* return */
-
+ ldcr TMP, ISR
+ ldcr TMP2, ILAR
+ ldcr TMP3, IPAR
+ st TMP, r31, REG_OFF(EF_ISR)
+ st TMP2, r31, REG_OFF(EF_ILAR)
+ st TMP3, r31, REG_OFF(EF_IPAR)
+ ldcr TMP, ISAP
+ ldcr TMP2, IUAP
+ st TMP, r31, REG_OFF(EF_ISAP)
+ st TMP2, r31, REG_OFF(EF_IUAP)
+ ldcr TMP, DSR
+ ldcr TMP2, DLAR
+ ldcr TMP3, DPAR
+ st TMP, r31, REG_OFF(EF_DSR)
+ st TMP2, r31, REG_OFF(EF_DLAR)
+ st TMP3, r31, REG_OFF(EF_DPAR)
+ ldcr TMP, DSAP
+ ldcr TMP2, DUAP
+ st TMP, r31, REG_OFF(EF_DSAP)
+ st TMP2, r31, REG_OFF(EF_DUAP)
+
+ ldcr r1, SR2
+ jmp r1 /* return */
+
/************************************************************************/
/************************************************************************/
-ASGLOBAL(m197_setup_phase_two)
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: saved return address to calling exception handler *
- * SR1: saved copy of exception-time register now holding FLAGS *
- * SR2: free *
- * SR3: saved TMP *
- * r1: return address to calling exception handler *
- * TMP: possibly revised SSBR *
- * TMP2: free *
- * TMP3: free *
- * FLAGS: CPU status flags *
- * r31: our exception frame *
- * Valid in the exception frame: *
- * Exception-time r1, r31, FLAGS. *
- * Exception-time TMP2, TMP3. *
- * Exception-time espr, sfip, snip, sxip. *
- * Exception number (EF_VECTOR). *
- * Dmt0 *
- * Other data pipeline control registers, if appropriate. *
- * FPU control registers, if appropriate. *
- * Exception SR3, if appropriate. *
- *************************************************** *
- * immediate goal: *
- * restore the system to the exception-time state (except *
- * SR3 will be OUR stack pointer) so that we may resart the FPU. *
- \***************************************************************/
- /*stcr r1, SR0*/ /* save return address */
-
- RESTORE_TMP2 /* done with extra temp regs */
- RESTORE_TMP3 /* done with extra temp regs */
-
- ldcr TMP, PSR
- clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */
- clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */
- stcr TMP, EPSR
-
- or.u TMP, r0, hi16(m197_fpu_enable)
- or TMP, TMP, lo16(m197_fpu_enable)
- stcr TMP, EXIP /* jump to here fpu_enable */
- addu TMP, TMP, 4
- stcr TMP, ENIP /* and then continue after that */
-
- set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/
- xcr FLAGS, FLAGS, SR1
- st r1, r31, REG_OFF(EF_RET) /* save the return address */
- ld r1, r31, GENREG_OFF(1) /* get original r1 */
-
- xcr TMP, r31, SR3 /* TMP now restored. R31 now saved in SR3 */
- ld r31, r31, GENREG_OFF(31) /* get original r31 */
-
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: CPU flags *
- * SR2: free *
- * SR3: pointer to our exception frame (our stack pointer) *
- * r1 through r31: original exception-time values *
- * *
- * Valid in the exception frame: *
- * Exception-time FLAGS. *
- * Exception-time espr, sfip, snip, sxip. *
- * Exception number (EF_VECTOR). *
- * Dmt0 *
- * Other data pipeline control registers, if appropriate. *
- * FPU control registers, if appropriate. *
- * Exception SR3, if appropriate. *
- * Held temporarly in the exception frame: *
- * Return address to the calling excption handler. *
- *************************************************** *
- * immediate goal: *
- * Do an RTE to restart the fpu and jump to "fpu_enable" *
- * Another exception (or exceptions) may be raised in *
- * this, which is why FLAG_ENABLING_FPU is set in SR1. *
- \***************************************************************/
- NOP
- RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */
-
-ASGLOBAL(m197_fpu_enable)
- FLUSH_PIPELINE
- xcr TMP, TMP, SR3 /* get E.F. pointer */
- st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */
- or r31, TMP, r0 /* transfer E.F. pointer to r31 */
- ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/
-
- /* make sure that the FLAG_ENABLING_FPU bit is off */
- xcr FLAGS,FLAGS,SR1
- clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>
- xcr FLAGS,FLAGS,SR1
-
- xcr TMP, TMP, SR3 /* replace TMP, SR3 */
-
- /* now save all regs to the exception frame. */
- st.d r0 , r31, GENREG_OFF(0)
- st.d r2 , r31, GENREG_OFF(2)
- st.d r4 , r31, GENREG_OFF(4)
- st.d r6 , r31, GENREG_OFF(6)
- st.d r8 , r31, GENREG_OFF(8)
- st.d r10, r31, GENREG_OFF(10)
- st.d r12, r31, GENREG_OFF(12)
- st.d r14, r31, GENREG_OFF(14)
- st.d r16, r31, GENREG_OFF(16)
- st.d r18, r31, GENREG_OFF(18)
- st.d r20, r31, GENREG_OFF(20)
- st.d r22, r31, GENREG_OFF(22)
- st.d r24, r31, GENREG_OFF(24)
- st.d r26, r31, GENREG_OFF(26)
- st.d r28, r31, GENREG_OFF(28)
+ASGLOBAL(m88110_setup_phase_two)
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: saved return address to calling exception handler *
+ * SR1: saved copy of exception-time register now holding FLAGS *
+ * SR2: free *
+ * SR3: saved TMP *
+ * r1: return address to calling exception handler *
+ * TMP: possibly revised SSBR *
+ * TMP2: free *
+ * TMP3: free *
+ * FLAGS: CPU status flags *
+ * r31: our exception frame *
+ * Valid in the exception frame: *
+ * Exception-time r1, r31, FLAGS. *
+ * Exception-time TMP2, TMP3. *
+ * Exception-time espr, sfip, snip, sxip. *
+ * Exception number (EF_VECTOR). *
+ * Dmt0 *
+ * Other data pipeline control registers, if appropriate. *
+ * FPU control registers, if appropriate. *
+ * Exception SR3, if appropriate. *
+ *************************************************** *
+ * immediate goal: *
+ * restore the system to the exception-time state (except *
+ * SR3 will be OUR stack pointer) so that we may resart the FPU. *
+ \***************************************************************/
+ /*stcr r1, SR0*/ /* save return address */
+
+ RESTORE_TMP2 /* done with extra temp regs */
+ RESTORE_TMP3 /* done with extra temp regs */
+
+ ldcr TMP, PSR
+ clr TMP, TMP, 1<PSR_FPU_DISABLE_BIT> /* enable the FPU */
+ clr TMP, TMP, 1<PSR_SHADOW_FREEZE_BIT> /* also enable shadowing */
+ stcr TMP, EPSR
+
+ or.u TMP, r0, hi16(m88110_fpu_enable)
+ or TMP, TMP, lo16(m88110_fpu_enable)
+ stcr TMP, EXIP /* jump to here fpu_enable */
+ addu TMP, TMP, 4
+ stcr TMP, ENIP /* and then continue after that */
+
+ set FLAGS, FLAGS, 1<FLAG_ENABLING_FPU> /* note what we're doing.*/
+ xcr FLAGS, FLAGS, SR1
+ st r1, r31, REG_OFF(EF_RET) /* save the return address */
+ ld r1, r31, GENREG_OFF(1) /* get original r1 */
+
+ ldcr TMP, SR3
+ stcr r31, SR3 /* TMP now restored. R31 now saved in SR3 */
+ ld r31, r31, GENREG_OFF(31) /* get original r31 */
+
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: CPU flags *
+ * SR2: free *
+ * SR3: pointer to our exception frame (our stack pointer) *
+ * r1 through r31: original exception-time values *
+ * *
+ * Valid in the exception frame: *
+ * Exception-time FLAGS. *
+ * Exception-time espr, sfip, enip, exip. *
+ * Exception number (EF_VECTOR). *
+ * Dmt0 *
+ * Other data pipeline control registers, if appropriate. *
+ * FPU control registers, if appropriate. *
+ * Exception SR3, if appropriate. *
+ * Held temporarly in the exception frame: *
+ * Return address to the calling excption handler. *
+ *************************************************** *
+ * immediate goal: *
+ * Do an RTE to restart the fpu and jump to "fpu_enable" *
+ * Another exception (or exceptions) may be raised in *
+ * this, which is why FLAG_ENABLING_FPU is set in SR1. *
+ \***************************************************************/
+ NOP
+ RTE /* jumps to "fpu_enable" on the next line to enable the FPU. */
+
+ASGLOBAL(m88110_fpu_enable)
+ FLUSH_PIPELINE
+ /* Now we can handle another exception!!! */
+ /* Now that EFZE is cleared we can clear these */
+ stcr r0, ISR /* Clear ISR */
+ stcr r0, ILAR /* Clear ILAR */
+ stcr r0, IPAR /* Clear IPAR */
+ stcr r0, DSR /* Clear DSR */
+ stcr r0, DLAR /* Clear DLAR */
+ stcr r0, DPAR /* Clear DPAR */
+ xcr TMP, TMP, SR3 /* get E.F. pointer */
+ st.d r30, TMP, GENREG_OFF(30) /* save previous r30, r31 */
+ or r31, TMP, r0 /* transfer E.F. pointer to r31 */
+ ld TMP, r31, REG_OFF(EF_SR3) /* get previous SR3; maybe important*/
+
+ /* make sure that the FLAG_ENABLING_FPU bit is off */
+ xcr FLAGS,FLAGS,SR1
+ clr FLAGS,FLAGS,1<FLAG_ENABLING_FPU>
+ xcr FLAGS,FLAGS,SR1
+
+ xcr TMP, TMP, SR3 /* replace TMP, SR3 */
+
+ /* now save all regs to the exception frame. */
+ st.d r0 , r31, GENREG_OFF(0)
+ st.d r2 , r31, GENREG_OFF(2)
+ st.d r4 , r31, GENREG_OFF(4)
+ st.d r6 , r31, GENREG_OFF(6)
+ st.d r8 , r31, GENREG_OFF(8)
+ st.d r10, r31, GENREG_OFF(10)
+ st.d r12, r31, GENREG_OFF(12)
+ st.d r14, r31, GENREG_OFF(14)
+ st.d r16, r31, GENREG_OFF(16)
+ st.d r18, r31, GENREG_OFF(18)
+ st.d r20, r31, GENREG_OFF(20)
+ st.d r22, r31, GENREG_OFF(22)
+ st.d r24, r31, GENREG_OFF(24)
+ st.d r26, r31, GENREG_OFF(26)
+ st.d r28, r31, GENREG_OFF(28)
#ifdef JEFF_DEBUG
- /* mark beginning of frame with notable value */
- or.u r20, r0, hi16(0x12345678)
- or r20, r20, lo16(0x12345678)
- st r20, r31, GENREG_OFF(0)
+ /* mark beginning of frame with notable value */
+ or.u r20, r0, hi16(0x12345678)
+ or r20, r20, lo16(0x12345678)
+ st r20, r31, GENREG_OFF(0)
#endif
-
- /***************** REGISTER STATUS BLOCK ***********************\
- * SR0: current thread *
- * SR1: free *
- * SR2: free *
- * SR3: previous exception-time SR3 *
- * r1: return address to the calling exception handler *
- * r2 through r30: free *
- * r31: our exception frame *
- * *
- * Valid in the exception frame: *
- * Exception-time r0 through r31. *
- * Exception-time FLAGS. *
- * Exception-time espr, sfip, snip, sxip. *
- * Exception number (EF_VECTOR). *
- * Dmt0 *
- * Other data pipeline control registers, if appropriate. *
- * FPU control registers, if appropriate. *
- * Exception SR3, if appropriate. *
- *************************************************** *
- * immediate goal: *
- * Pick up a stack if we came in from user mode. Put *
- * A copy of the exception frame pointer into r30 *
- * bump the stack a doubleword and write the exception *
- * frame pointer. *
- * if not an interrupt exception, *
- * Turn on interrupts and service any outstanding *
- * data access exceptions. *
- * Return to calling exception handler to *
- * service the exception. *
- \***************************************************************/
-
- /*
- * If it's not the interrupt exception, enable interrupts and
- * take care of any data access exceptions......
- *
+
+ /***************** REGISTER STATUS BLOCK ***********************\
+ * SR0: current thread *
+ * SR1: free *
+ * SR2: free *
+ * SR3: previous exception-time SR3 *
+ * r1: return address to the calling exception handler *
+ * r2 through r30: free *
+ * r31: our exception frame *
+ * *
+ * Valid in the exception frame: *
+ * Exception-time r0 through r31. *
+ * Exception-time FLAGS. *
+ * Exception-time espr, enip, exip. *
+ * Exception number (EF_VECTOR). *
+ * DSR *
+ * Other data pipeline control registers, if appropriate. *
+ * FPU control registers, if appropriate. *
+ * Exception SR3, if appropriate. *
+ *************************************************** *
+ * immediate goal: *
+ * Pick up a stack if we came in from user mode. Put *
+ * A copy of the exception frame pointer into r30 *
+ * bump the stack a doubleword and write the exception *
+ * frame pointer. *
+ * if not an interrupt exception, *
+ * Turn on interrupts and service any outstanding *
+ * data access exceptions. *
+ * Return to calling exception handler to *
+ * service the exception. *
+ \***************************************************************/
+
+ /*
+ * If it's not the interrupt exception, enable interrupts and
+ * take care of any data access exceptions......
+ */
#if INTSTACK
- * If interrupt exception, switch to interrupt stack if not
- * already there. Else, switch to kernel stack.
+ /*
+ * If interrupt exception, switch to interrupt stack if not
+ * already there. Else, switch to kernel stack.
+ */
#endif
- */
- or r30, r0, r31 /* get a copy of the e.f. pointer */
- ld r2, r31, REG_OFF(EF_EPSR)
- bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */
+ or r30, r0, r31 /* get a copy of the e.f. pointer */
+ ld r2, r31, REG_OFF(EF_EPSR)
+ bb1 PSR_SUPERVISOR_MODE_BIT, r2, 1f /* If in kernel mode */
#if INTSTACK
- ld r3, r31, REG_OFF(EF_VECTOR)
- cmp r3, r3, 1 /* is interrupt ? */
- bb0 eq, r3, 2f
- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
- or r31, r31, lo16(_intstack_end)
- br 3f
+ ld r3, r31, REG_OFF(EF_VECTOR)
+ cmp r3, r3, 1 /* is interrupt ? */
+ bb0 eq, r3, 2f
+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
+ or r31, r31, lo16(_intstack_end)
+ br 3f
2:
#endif
- or.u r31, r0, hi16(_kstack)
- ld r31, r31, lo16(_kstack)
- addu r31, r31, USIZE /* point at proper end */
- br 3f
+ or.u r31, r0, hi16(_kstack)
+ ld r31, r31, lo16(_kstack)
+ addu r31, r31, USIZE /* point at proper end */
+ br 3f
1:
#if INTSTACK
- ld r3, r31, REG_OFF(EF_VECTOR)
- cmp r3, r3, 1 /* is interrupt ? */
- bb0 eq, r3, 3f /* no, we will stay on kern stack */
- or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
- or r31, r31, lo16(_intstack_end)
-#endif /* INTSTACK */
- /* This label is here for debugging */
-m197_exception_handler_has_ksp: global m197_exception_handler_has_ksp
-3: /*
- here - r30 holds a pointer to the exception frame.
- r31 is a pointer to the kernel stack/interrupt stack.
- */
- subu r31, r31, 8 /* make some breathing space */
- st r30, r31, 0 /* store frame pointer on the stack */
+ ld r3, r31, REG_OFF(EF_VECTOR)
+ cmp r3, r3, 1 /* is interrupt ? */
+ bb0 eq, r3, 3f /* no, we will stay on kern stack */
+ or.u r31, r0, hi16(_intstack_end) /* swith to int stack */
+ or r31, r31, lo16(_intstack_end)
+#endif /* INTSTACK */
+ /* This label is here for debugging */
+m88110_exception_handler_has_ksp: global m88110_exception_handler_has_ksp
+3: /*
+ * here - r30 holds a pointer to the exception frame.
+ * r31 is a pointer to the kernel stack/interrupt stack.
+ */
+ subu r31, r31, 8 /* make some breathing space */
+ st r30, r31, 0 /* store frame pointer on the stack */
#if DDB
- st r30, r31, 4 /* store it again for the debugger to recognize */
+ st r30, r31, 4 /* store it again for the debugger to recognize */
#endif /* DDB */
- ld r2, r30, REG_OFF(EF_VECTOR)
- bcnd.n eq0, r2, m197_return_to_calling_exception_handler /* is error */
- ld r14, r30, REG_OFF(EF_RET)
- cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */
- bb1.n eq, r3, m197_return_to_calling_exception_handler /* skip if so */
+ ld r2, r30, REG_OFF(EF_VECTOR)
+ bcnd.n eq0, r2, m88110_return_to_calling_exception_handler /* is error */
+ ld r14, r30, REG_OFF(EF_RET) /* load return value XXX!!! */
+ cmp r3, r2, 1 /* interrupt is exception #1 ;Is an interrupt? */
+ bb1.n eq, r3, m88110_return_to_calling_exception_handler /* skip if so */
#if DDB
- cmp r3, r2, 130 /* DDB break exception */
- bb1.n eq, r3, m197_return_to_calling_exception_handler
+ cmp r3, r2, 130 /* DDB break exception */
+ bb1.n eq, r3, m88110_return_to_calling_exception_handler
- cmp r3, r2, 132 /* DDB entry exception */
- bb1.n eq, r3, m197_return_to_calling_exception_handler
+ cmp r3, r2, 132 /* DDB entry exception */
+ bb1.n eq, r3, m88110_return_to_calling_exception_handler
#endif
- ldcr r2, PSR
- clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */
- stcr r2, PSR
+ ldcr r2, PSR
+ clr r2, r2, 1<PSR_INTERRUPT_DISABLE_BIT> /* enable interrupts */
+ stcr r2, PSR
#if DDB
- FLUSH_PIPELINE
+ FLUSH_PIPELINE
#endif
+#if 1 /* test */
+ br m88110_return_to_calling_exception_handler
+#endif
+ /* service any outstanding data pipeline stuff
+ - check dsr... anything outstanding?*/
- /* service any outstanding data pipeline stuff
- - check dsr... anything outstanding?*/
-
- ld r3, r30, REG_OFF(EF_DSR)
- cmp r3, r3, 0
- bb1 eq, r3, m197_return_to_calling_exception_handler
+ ld r3, r30, REG_OFF(EF_DSR)
+ cmp r3, r3, 0
+ bb1 eq, r3, m88110_return_to_calling_exception_handler
/*
- r30 can be clobbered by calls. So stuff its value into a
- preserved register, say r15. R14 is in use (see return_to_... below).
+ * r30 can be clobbered by calls. So stuff its value into a
+ * preserved register, say r15. R14 is in use (see return_to_... below).
*/
- or r15, r0, r30
-
- CALL(_C_LABEL(trap197), T_DATAFLT, r15)
-
-/* restore it... */
- or r30, r0, r15
+ or r15, r0, r30
+#if 0
+ CALL(_test_trap, r15, r0)
+#endif
+ CALL(_m88110_trap, T_DATAFLT, r15)
- /* clear the dsr word in the E.F */
- st r0, r30, REG_OFF(EF_DSR)
+ /* restore it... */
+ or r30, r0, r15
-ASGLOBAL(m197_return_to_calling_exception_handler)
- jmp r14 /* loaded above */
+ /* clear the dsr word in the E.F */
+ st r0, r30, REG_OFF(EF_DSR)
+ASGLOBAL(m88110_return_to_calling_exception_handler)
+ jmp r14 /* loaded above */
#endif
diff --git a/sys/arch/mvme88k/mvme88k/genassym.cf b/sys/arch/mvme88k/mvme88k/genassym.cf
index a08ccbbe51c..3d1274d85e4 100644
--- a/sys/arch/mvme88k/mvme88k/genassym.cf
+++ b/sys/arch/mvme88k/mvme88k/genassym.cf
@@ -1,4 +1,4 @@
-# $OpenBSD: genassym.cf,v 1.2 2001/09/16 14:28:04 miod Exp $
+# $OpenBSD: genassym.cf,v 1.3 2001/12/13 08:55:52 smurph Exp $
#
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@@ -32,7 +32,7 @@
# SUCH DAMAGE.
#
# @(#)genassym.c 7.8 (Berkeley) 5/7/91
-# $Id: genassym.cf,v 1.2 2001/09/16 14:28:04 miod Exp $
+# $Id: genassym.cf,v 1.3 2001/12/13 08:55:52 smurph Exp $
#
include <sys/param.h>
@@ -107,16 +107,33 @@ define EF_MODE offsetof(struct m88100_saved_state, mode) / sizeof(int)
define EF_RET offsetof(struct m88100_saved_state, scratch1) / sizeof(int)
define EF_IPFSR offsetof(struct m88100_saved_state, ipfsr) / sizeof(int)
define EF_DPFSR offsetof(struct m88100_saved_state, dpfsr) / sizeof(int)
+define EF_CPU offsetof(struct m88100_saved_state, cpu) / sizeof(int)
+
+# m88110 m88100_saved_state element indexes
+define EF_EXIP offsetof(struct m88100_saved_state, exip) / sizeof(int)
+define EF_ENIP offsetof(struct m88100_saved_state, enip) / sizeof(int)
define EF_DSR offsetof(struct m88100_saved_state, dsr) / sizeof(int)
define EF_DLAR offsetof(struct m88100_saved_state, dlar) / sizeof(int)
define EF_DPAR offsetof(struct m88100_saved_state, dpar) / sizeof(int)
-define EF_ISR offsetof(struct m88100_saved_state, dsr) / sizeof(int)
+define EF_ISR offsetof(struct m88100_saved_state, isr) / sizeof(int)
define EF_ILAR offsetof(struct m88100_saved_state, ilar) / sizeof(int)
define EF_IPAR offsetof(struct m88100_saved_state, ipar) / sizeof(int)
-define EF_CPU offsetof(struct m88100_saved_state, cpu) / sizeof(int)
+define EF_ISAP offsetof(struct m88100_saved_state, isap) / sizeof(int)
+define EF_DSAP offsetof(struct m88100_saved_state, dsap) / sizeof(int)
+define EF_IUAP offsetof(struct m88100_saved_state, iuap) / sizeof(int)
+define EF_DUAP offsetof(struct m88100_saved_state, duap) / sizeof(int)
define SIZEOF_EF sizeof(struct m88100_saved_state)
+# machine-dependent pointers fields
+define MD_TRAP offsetof(struct md_p, trap_func)
+define MD_INT offsetof(struct md_p, interrupt_func)
+define MD_FP offsetof(struct md_p, fp_precise_func)
+define MD_SYSC offsetof(struct md_p, syscall_func)
+define MD_IMASK offsetof(struct md_p, intr_mask)
+define MD_ILEVEL offsetof(struct md_p, intr_ipl)
+define MD_ISRC offsetof(struct md_p, intr_src)
+
# more (machine-dependent) pcb fields
struct m88100_pcb
member pcb_pc
@@ -139,3 +156,4 @@ member pcb_r28
member pcb_r29
member pcb_r30
member pcb_sp
+
diff --git a/sys/arch/mvme88k/mvme88k/locore.S b/sys/arch/mvme88k/mvme88k/locore.S
index c5d13c6d662..2d5899f44da 100644
--- a/sys/arch/mvme88k/mvme88k/locore.S
+++ b/sys/arch/mvme88k/mvme88k/locore.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.S,v 1.20 2001/08/31 01:41:33 miod Exp $ */
+/* $OpenBSD: locore.S,v 1.21 2001/12/13 08:55:52 smurph Exp $ */
/*
* Copyright (c) 1998 Steve Murphree, Jr.
* Copyright (c) 1996 Nivas Madhur
@@ -62,7 +62,6 @@
#include <machine/asm.h>
#include <machine/trap.h>
-#include <machine/m88100.h>
#include <machine/psl.h>
#include <machine/param.h>
#include <machine/vmparam.h> /* INTSTACK_SIZE */
@@ -94,9 +93,9 @@ GLOBAL(doboot)
*/
#ifdef MVME188
/* check if it's a mvme188 */
- or.u r4, r0, hi16(_C_LABEL(cputyp))
- ld r3, r4, lo16(_C_LABEL(cputyp))
- cmp r4, r3, 0x188
+ or.u r4, r0, hi16(_C_LABEL(brdtyp))
+ ld r3, r4, lo16(_C_LABEL(brdtyp))
+ cmp r4, r3, BRD_188
bb1 ne, r4, 1f
bsr _C_LABEL(m188_reset)
br m188_doboot_fail
@@ -140,7 +139,7 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */
*/
/*
* (*entry)(flag, bugargs.ctrl_addr, cp, kernel.smini,
- * kernel.emini, bootdev, cputyp);
+ * kernel.emini, bootdev, brdtyp);
*/
or.u r13, r0, hi16(_boothowto)
st r2, r13, lo16(_boothowto)
@@ -154,8 +153,21 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */
#endif
or.u r13, r0, hi16(_bootdev)
st r7, r13, lo16(_bootdev)
+ or.u r13, r0, hi16(_brdtyp)
+ st r8, r13, lo16(_brdtyp)
+
+ /* set _cputyp */
+ cmp r2, r8, BRD_197 /* r8 contains brdtyp */
+ bb1 ne, r2, 1f /* if it's a '197, CPU is 88110 */
+ or.u r13, r0, hi16(CPU_88110)
+ or r8, r13, lo16(CPU_88110)/* r8 contains 0x110 */
+ br 2f
+1:
+ or.u r13, r0, hi16(CPU_88100)
+ or r8, r13, lo16(CPU_88100)/* r8 contains 0x100 */
+2:
or.u r13, r0, hi16(_cputyp)
- st r8, r13, lo16(_cputyp)
+ st r8, r13, lo16(_cputyp) /* r8 contains cputyp */
/*
* CPU Initialization
@@ -191,23 +203,23 @@ GLOBAL(start_text) /* This is the *real* start upon poweron or reset */
*
* jfriedl@omron.co.jp
*/
- cmp r2, r8, 0x197 /* r8 contains cputyp */
- bb1 eq, r2, 1f /* if it's a '197, skip SSBR */
- stcr r0, SSBR /* clear this for later */
+
+ cmp r2, r8, CPU_88110 /* r8 contains cputyp */
+ bb1 eq, r2, 1f /* if it's a 'mc88110, skip SSBR */
+ stcr r0, SSBR /* clear this for later */
1:
- stcr r0, SR0 /* clear "current thread" */
- stcr r0, SR1 /* clear the CPU flags */
+ stcr r0, SR0 /* clear "current thread" */
+ stcr r0, SR1 /* clear the CPU flags */
+
+ set r11, r0, 1<PSR_SUPERVISOR_MODE_BIT>
+ set r11, r11, 1<PSR_INTERRUPT_DISABLE_BIT>
+ set r11, r11, 1<PSR_SERIALIZE_BIT>
+ stcr r11, PSR
+ stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */
+ FLUSH_PIPELINE
+ cmp r2, r8, CPU_88110 /* r8 contains cputyp */
+ bb1 eq, r2, master_start /* if it's a '197, skip to master_start */
- set r11, r0, 1<PSR_SUPERVISOR_MODE_BIT>
- set r11, r11, 1<PSR_INTERRUPT_DISABLE_BIT>
- set r11, r11, 1<4>
- set r11, r11, 1<29>
- set r11, r11, 1<25>
- stcr r11, PSR
- stcr r0, VBR /* set Vector Base Register to 0, ALWAYS! */
- FLUSH_PIPELINE
- cmp r2, r8, 0x197 /* r8 contains cputyp */
- bb1 eq, r2, master_start /* if it's a '197, skip to master_start */
#if 0
/* clear BSS. Boot loader might have already done this... */
or.u r2, r0, hi16(_edata)
@@ -296,17 +308,17 @@ ASGLOBAL(master_start)
or r31, r31, lo16(_intstack_end)
clr r31, r31, 3<0> /* round down to 8-byte boundary */
-#ifdef MVME197
- cmp r2, r8, 0x197 /* r8 contains cputyp */
- bb1 ne, r2, 1f /* if it's a '197, use different vectors */
- or.u r3, r0, hi16(_m197_vector_list)
- or r3, r3, lo16(_m197_vector_list)
+#ifdef M88110
+ cmp r2, r8, CPU_88110 /* r8 contains cputyp */
+ bb1 ne, r2, 1f /* if it's a 'mc88110, use different vectors */
+ or.u r3, r0, hi16(_m88110_vector_list)
+ or r3, r3, lo16(_m88110_vector_list)
bsr.n _vector_init
ldcr r2, VBR
br 2f
-#endif /* MVME197 */
+#endif /* M88110 */
1:
-#if defined(MVME187) || defined(MVME188)
+#ifdef M88100
/*
* Want to make the call:
* vector_init(VBR, vector_list)
@@ -315,7 +327,7 @@ ASGLOBAL(master_start)
or r3, r3, lo16(_vector_list)
bsr.n _vector_init
ldcr r2, VBR
-#endif /* defined(MVME187) || defined(MVME188) */
+#endif /* M88100 */
2:
/* still on int stack */
bsr.n _mvme_bootstrap
@@ -390,21 +402,22 @@ GLOBAL(spin_cpu)
/*****************************************************************************/
data
+#ifdef M88100
.align 4096 /* VBR points to page aligned list */
-#if defined(MVME187) || defined(MVME188)
global _vector_list, _vector_list_end
_vector_list: /* references memory BELOW this line */
#include "machine/exception_vectors.h"
_vector_list_end:
word END_OF_VECTOR_LIST
-#endif /* defined(MVME187) || defined(MVME188) */
-#ifdef MVME197
- global _m197_vector_list, _m197_vector_list_end
-_m197_vector_list: /* references memory BELOW this line */
+#endif /* M88100 */
+#ifdef M88110
+ .align 4096 /* VBR points to page aligned list */
+ global _m88110_vector_list, _m88110_vector_list_end
+_m88110_vector_list: /* references memory BELOW this line */
#include "machine/exception_vectors2.h"
-_m197_vector_list_end:
+_m88110_vector_list_end:
word END_OF_VECTOR_LIST
-#endif /* MVME197 */
+#endif /* M88110 */
.align 4096 /* SDT (segment descriptor table */
global _kernel_sdt
_kernel_sdt:
@@ -545,4 +558,3 @@ _intrcnt:
word 0,0,0,0,0,0,0,0,0,0,0,0
_eintrcnt:
-
diff --git a/sys/arch/mvme88k/mvme88k/locore_asm_routines.S b/sys/arch/mvme88k/mvme88k/locore_asm_routines.S
index 1e6f85f06ca..52fdca441a3 100644
--- a/sys/arch/mvme88k/mvme88k/locore_asm_routines.S
+++ b/sys/arch/mvme88k/mvme88k/locore_asm_routines.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore_asm_routines.S,v 1.16 2001/08/24 22:53:15 miod Exp $ */
+/* $OpenBSD: locore_asm_routines.S,v 1.17 2001/12/13 08:55:52 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1992 Carnegie Mellon University
@@ -29,13 +29,11 @@
*/
#include "assym.h"
-
-#include <sys/errno.h>
-
#include <machine/asm.h>
#include <machine/board.h>
-#include <machine/cpu_number.h>
+#include <machine/param.h>
#include <machine/trap.h>
+#include <sys/errno.h>
/*****************************************************************************
* DO_LOAD_ADDRESS
@@ -169,6 +167,227 @@ ENTRY(do_xmem_byte) /* do_xmem_byte(address, data, supervisor) */
1: xmem.bu r3,r2,r0
2: jmp r1
+ .data
+
+/*
+ * reserve MAX_CPUS words for lockinit and lockeach;
+ * counters for simple_lock_init calls and lock acquisition calls.
+ */
+
+lockinit:
+ zero 4*MAX_CPUS
+
+lockuse:
+ zero 4*MAX_CPUS
+
+lockpause:
+ zero 4*MAX_CPUS
+
+ .text
+
+/*************************************************************************/
+/****************** SIMPLE LOCK OPERATIONS *****************************/
+/*************************************************************************/
+
+#ifdef done_in_kernel
+/*************************************************************
+ *************************************************************
+ **
+ ** void simple_lock_init(int *lock_data)
+ ** {
+ ** *lock_data = 0;
+ ** }
+ **
+ ** void simple_unlock(simple_lock_t *)
+ ** {
+ ** *lock_data = 0;
+ ** }
+ **/
+#undef simple_unlock
+ENTRY(simple_lock_init)
+ st r0, r2, 0 /* init */
+
+ ldcr r2, SR1
+ extu r2, r2, FLAG_CPU_FIELD_WIDTH<0> /* r2 = cpu# */
+ mask r2, r2, 3 /* play it safe */
+ or.u r3, r0, hi16(lockinit)
+ or r3, r3, lo16(lockinit)
+ ld r4, r3[r2]
+ addu r4, r4, 1
+ jmp.n r1
+ st r4, r3[r2]
+
+ENTRY(simple_unlock)
+ jmp.n r1
+ st r0, r2, 0
+
+#if DDB
+/* version of simple_unlock for the debugger - should be identical to
+ simple_unlock, but should never have breakpoints inserted on it */
+ENTRY(db_simple_unlock)
+ jmp.n r1
+ st r0, r2, 0
+#endif
+
+/**
+ ** Simple_lock
+ **
+ ** Returns when the lock is taken. It also increments lockuse[cpu]
+ **/
+ENTRY(simple_lock)
+ /* do r3 = test_and_set(r2, 1) */
+ or r3, r0, 1
+ xmem r3, r2, r0
+ bcnd ne0, r3, 1f
+#if 0
+ ldcr r5, SR1
+ extu r5, r5, FLAG_CPU_FIELD_WIDTH<0> /* r5 = cpu# */
+ mask r5, r5, 3 /* play it safe */
+ or.u r3, r0, hi16(lockuse)
+ or r3, r3, lo16(lockuse)
+ ld r4, r3[r5]
+ addu r4, r4, 1
+ st r4, r3[r5]
+#endif
+ jmp r1
+
+1:
+ /* wait until the lock appears to be free */
+ or.u r4, r0, 0x0300
+2:
+ subu r4, r4, 1
+ bcnd eq0, r4, _simple_lock_too_long
+ ld r3, r2, 0 /* check lock */
+ bcnd ne0, r3, 2b
+ br _simple_lock /* looks free... check again with the xmem */
+
+ENTRY(simple_lock_too_long)
+#ifdef JEFF_DEBUG
+ /* just want to break here.... */
+ tb0 0, r0 , 0x84 /* gimmeabreak */
+#else
+ /* waited too long */
+ subu r31, r31, 0x40
+ st r1, r31, 0x30
+ st r30, r31, 0x34
+ st r2, r31, 0x38
+ or r3, r0, r1
+#if 0
+ bsr _report_lock_info
+#endif
+ ld r2, r31, 0x38
+ ld r30, r31, 0x34
+ ld r1, r31, 0x30
+ addu r31, r31, 0x40
+ br _simple_lock
+#endif /* JEFF_DEBUG */
+
+
+#if DDB
+/*
+ * Version of simple_lock for the kernel debugger; should never have
+ * breakpoints set on it. Should be kept consistent with simple_lock.
+ */
+ENTRY(db_simple_lock)
+ /* do r10 = test_and_set(r2, 1) */
+ or r10, r0, 1
+ xmem r10, r2, r0
+ bcnd ne0, r10, db_simple_lock_watch
+
+ ldcr r2, SR1
+ extu r2, r2, FLAG_CPU_FIELD_WIDTH<0> /* r2 = cpu# */
+ mask r2, r2, 3 /* play it safe */
+ or.u r3, r0, hi16(lockuse)
+ or r3, r3, lo16(lockuse)
+ ld r4, r3[r2]
+ addu r4, r4, 1
+ jmp.n r1
+ st r4, r3[r2]
+
+db_simple_lock_watch:
+ /* wait until the lock appears to be free */
+3:
+ ld r10, r2, 0
+ bcnd ne0, r10, 3b
+ br _db_simple_lock /* looks free... check again with the xmem */
+#endif /* DDB */
+
+/*************************************************************
+ *************************************************************
+ **
+ ** boolean_t simple_try_lock(simple_lock_t *);
+ **
+ ** Grab the lock if it's free. Return zero if the lock was
+ ** busy, non-zero if the lock has been taken.
+ **/
+ENTRY(simple_lock_try)
+ or r3, r0, 1 /* r3 := test_and_set(r2, 1) */
+ xmem r3, r2, r0
+ /* If r3 is now zero, we hold the lock -- return non-zero. */
+ /* If r3 is now one, we didn't get it -- return zero. */
+ /* Thus, we want to "return(!r3)" */
+ cmp r4, r3, r0
+ jmp.n r1
+ extu r2, r4, 1<2>
+
+#if DDB
+/* version for the kernel debugger - keep consistent with above */
+ENTRY(db_simple_lock_try)
+ or r3, r0, 1 /* r3 := test_and_set(r2, 1) */
+ xmem r3, r2, r0
+ /* If r3 is now zero, we hold the lock -- return non-zero. */
+ /* If r3 is now one, we didn't get it -- return zero. */
+ /* Thus, we want to "return(!r3)" */
+ cmp r4, r3, r0
+ jmp.n r1
+ extu r2, r4, 1<2>
+#endif
+
+#if DDB /* version for the debugger */
+ENTRY(db_simple_lock_held)
+ jmp.n r1
+ ld r2, r2, 0
+#endif
+
+/*
+ * void simple_lock_pause(void).
+ *
+ * This routine is called when we find a simple lock held that we wish to
+ * acquire, but cannot spin on because we are holding a lock that is in the
+ * wrong order to it with respect to the locking hierarchy. Once we drop the
+ * lock we are holding, however, we cannot assume the lock we were trying to
+ * acquire is not deallocated. Consequently, we drop the lock we are holding
+ * and wait for a while, then retry. This is the wait for a while routine.
+ *
+ * We define a array of counters[cpus], lockpause
+ * to tell use how many times this routine is called.
+ * We currently wait 128 cycles per call.
+ */
+
+ENTRY(simple_lock_pause)
+ ldcr r2, SR1
+ extu r2, r2, FLAG_CPU_FIELD_WIDTH<0> /* r2 = cpu# */
+ mask r2, r2, 3 /* play it safe */
+ or.u r3, r0, hi16(lockpause)
+ or r3, r3, lo16(lockpause)
+ ld r4, r3[r2]
+ or r5, r0, 128 /* initialize counters*/
+1: subu r5, r5, 1 /* count down */
+ bcnd ne0, r5, 1b
+ addu r4, r4, 1
+ jmp.n r1 /* return*/
+ st r4, r3[r2]
+
+#endif /* done_in_kernel */
+
+ENTRY(are_interrupts_disabled)
+ ldcr r2, PSR /* get the processor status word */
+ set r3, r0, 1<PSR_INTERRUPT_DISABLE_BIT> /* set mask */
+ jmp.n r1 /* delayed return */
+ and r2, r2, r3 /* r2 = r3 & r2 */
+
+
+/* version for the debugger */
#if DDB
ENTRY(db_are_interrupts_disabled)
ldcr r2, PSR /* get the processor status word */
@@ -1546,7 +1765,7 @@ ENTRY(bzero)
bb1 0, R_dest, not_initially_word_aligned
bb1 1, R_dest, not_initially_word_aligned
- now_word_aligned:
+now_word_aligned:
/*
* before we get into the main loop, grab the
* address of the label "mark" below.
@@ -1554,7 +1773,7 @@ ENTRY(bzero)
or.u R_mark_address, r0, hi16(mark)
or R_mark_address, R_mark_address, lo16(mark)
- top_of_main_loop:
+top_of_main_loop:
#define MAX_AT_ONE_TIME 128
/*
* Now we find out how many words we can zero-fill in a row.
@@ -1642,17 +1861,17 @@ do_max: subu R_len, R_len, R_bytes /* NOTE: this is in the delay slot! */
st r0, R_dest, 0x04 /* 4 */
st r0, R_dest, 0x00 /* 0 */
- mark:
+mark:
br.n top_of_main_loop
addu R_dest, R_dest, R_bytes /* bump up the dest address */
- done_doing_words:
+done_doing_words:
bcnd ne0, R_len, finish_up_last_bytes
jmp r1 /* RETURN */
- finish_up_last_bytes:
+finish_up_last_bytes:
subu R_len, R_len, 1
bcnd.n ne0, R_len, finish_up_last_bytes
st.b r0, R_dest, R_len
@@ -1660,7 +1879,7 @@ do_max: subu R_len, R_len, R_bytes /* NOTE: this is in the delay slot! */
leave:
jmp r1 /* RETURN */
- not_initially_word_aligned:
+not_initially_word_aligned:
/*
* Bzero to word-align the address (at least if the length allows it).
*/
diff --git a/sys/arch/mvme88k/mvme88k/locore_c_routines.c b/sys/arch/mvme88k/mvme88k/locore_c_routines.c
index 45da20d844d..19ef9fb884c 100644
--- a/sys/arch/mvme88k/mvme88k/locore_c_routines.c
+++ b/sys/arch/mvme88k/mvme88k/locore_c_routines.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore_c_routines.c,v 1.14 2001/11/27 05:37:02 miod Exp $ */
+/* $OpenBSD: locore_c_routines.c,v 1.15 2001/12/13 08:55:52 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1993-1991 Carnegie Mellon University
@@ -28,14 +28,17 @@
#include "assym.h"
+#include <sys/param.h>
#include <sys/types.h>
#include <sys/systm.h>
+#include <machine/cpu_number.h> /* cpu_number() */
+#include <machine/board.h> /* m188 bit defines */
+#include <machine/cmmu.h> /* DMT_VALID */
#include <machine/asm.h> /* END_OF_VECTOR_LIST, etc. */
#include <machine/asm_macro.h> /* enable/disable interrupts */
#include <machine/mmu.h>
#include <machine/board.h> /* m188 bit defines */
-#include <machine/cmmu.h>
#include <machine/cpu_number.h> /* cpu_number() */
#include <machine/locore.h>
#include <machine/m88100.h> /* DMT_VALID */
@@ -62,8 +65,18 @@
#define DMT_HALF 2
#define DMT_WORD 4
-extern volatile u_char *int_mask_level; /* machdep.c */
+typedef struct {
+ unsigned word_one,
+ word_two;
+} m88k_exception_vector_area;
+
+extern volatile unsigned int * int_mask_reg[MAX_CPUS]; /* in machdep.c */
+extern unsigned master_cpu; /* in cmmu.c */
+
+/* FORWARDS */
+void vector_init(m88k_exception_vector_area *vector, unsigned *vector_init_list);
+#ifdef M88100
static struct {
unsigned char offset;
unsigned char size;
@@ -73,6 +86,7 @@ static struct {
{0, DMT_BYTE}, {0, 0}, {0, 0}, {0, 0},
{0, DMT_HALF}, {0, 0}, {0, 0}, {0, DMT_WORD}
};
+#endif
#ifdef DATA_DEBUG
int data_access_emulation_debug = 0;
@@ -94,7 +108,7 @@ void setlevel __P((int));
void db_setlevel __P((int));
#endif
-#if defined(MVME187) || defined(MVME188)
+#ifdef M88100
void
dae_print(unsigned *eframe)
{
@@ -136,7 +150,6 @@ dae_print(unsigned *eframe)
}
}
-#endif /* defined(MVME187) || defined(MVME188) */
void
data_access_emulation(unsigned *eframe)
@@ -281,6 +294,7 @@ data_access_emulation(unsigned *eframe)
}
eframe[EF_DMT0] = 0;
}
+#endif /* M88100 */
/*
***********************************************************************
@@ -292,13 +306,6 @@ data_access_emulation(unsigned *eframe)
#define EMPTY_BR 0xC0000000U /* empty "br" instruction */
#define NO_OP 0xf4005800U /* "or r0, r0, r0" */
-typedef struct {
- unsigned word_one,
- word_two;
-} m88k_exception_vector_area;
-
-void vector_init __P((m88k_exception_vector_area *, unsigned *));
-
#define BRANCH(FROM, TO) (EMPTY_BR | ((unsigned)(TO) - (unsigned)(FROM)) >> 2)
#define SET_VECTOR(NUM, to, VALUE) { \
@@ -329,28 +336,27 @@ vector_init(m88k_exception_vector_area *vector, unsigned *vector_init_list)
}
switch (cputyp) {
-#ifdef MVME197
- case CPU_197:
+#ifdef M88110
+ case CPU_88110:
while (num < 496) {
- SET_VECTOR(num, to, m197_sigsys);
+ SET_VECTOR(num, to, m88110_sigsys);
num++;
}
num++; /* skip 496, BUG ROM vector */
- SET_VECTOR(450, to, m197_syscall_handler);
+ SET_VECTOR(450, to, m88110_syscall_handler);
while (num <= SIGSYS_MAX)
- SET_VECTOR(num++, to, m197_sigsys);
+ SET_VECTOR(num++, to, m88110_sigsys);
while (num <= SIGTRAP_MAX)
- SET_VECTOR(num++, to, m197_sigtrap);
+ SET_VECTOR(num++, to, m88110_sigtrap);
- SET_VECTOR(504, to, m197_stepbpt);
- SET_VECTOR(511, to, m197_userbpt);
+ SET_VECTOR(504, to, m88110_stepbpt);
+ SET_VECTOR(511, to, m88110_userbpt);
break;
#endif /* MVME197 */
-#if defined(MVME187) || defined(MVME188)
- case CPU_187:
- case CPU_188:
+#ifdef M88100
+ case CPU_88100:
while (num < 496) {
SET_VECTOR(num, to, sigsys);
num++;
@@ -485,17 +491,17 @@ spl(void)
int cpu = 0; /* prevent warning */
#endif
psr = disable_interrupts_return_psr();
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME188
- case CPU_188:
+ case BRD_188:
cpu = cpu_number();
curspl = m188_curspl[cpu];
break;
#endif /* MVME188 */
#if defined(MVME187) || defined(MVME197)
- case CPU_187:
- case CPU_197:
- curspl = *int_mask_level;
+ case BRD_187:
+ case BRD_197:
+ curspl = *md.intr_mask;
break;
#endif /* defined(MVME187) || defined(MVME197) */
}
@@ -514,17 +520,17 @@ db_spl(void)
#endif
psr = disable_interrupts_return_psr();
- switch (cputyp) {
-#ifdef MVME188
- case CPU_188:
+ switch (brdtyp) {
+ #ifdef MVME188
+ case BRD_188:
cpu = cpu_number();
curspl = m188_curspl[cpu];
break;
-#endif /* MVME188 */
-#if defined(MVME187) || defined(MVME197)
- case CPU_187:
- case CPU_197:
- curspl = *int_mask_level;
+ #endif /* MVME188 */
+ #if defined(MVME187) || defined(MVME197)
+ case BRD_187:
+ case BRD_197:
+ curspl = *md.intr_mask;
break;
#endif /* defined(MVME187) || defined(MVME197) */
}
@@ -560,19 +566,19 @@ setipl(unsigned level)
}
psr = disable_interrupts_return_psr();
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME188
- case CPU_188:
+ case BRD_188:
cpu = cpu_number();
curspl = m188_curspl[cpu];
setlevel(level);
break;
#endif /* MVME188 */
#if defined(MVME187) || defined(MVME197)
- case CPU_187:
- case CPU_197:
- curspl = *int_mask_level;
- *int_mask_level = level;
+ case BRD_187:
+ case BRD_197:
+ curspl = *md.intr_mask;
+ *md.intr_mask = level;
break;
#endif /* defined(MVME187) || defined(MVME197) */
}
@@ -598,19 +604,19 @@ db_setipl(unsigned level)
#endif
psr = disable_interrupts_return_psr();
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME188
- case CPU_188:
+ case BRD_188:
cpu = cpu_number();
curspl = m188_curspl[cpu];
db_setlevel(level);
break;
#endif /* MVME188 */
#if defined(MVME187) || defined(MVME197)
- case CPU_187:
- case CPU_197:
- curspl = *int_mask_level;
- *int_mask_level = level;
+ case BRD_187:
+ case BRD_197:
+ curspl = *md.intr_mask;
+ *md.intr_mask = level;
break;
#endif /* defined(MVME187) || defined(MVME197) */
}
diff --git a/sys/arch/mvme88k/mvme88k/m197_cmmu.c b/sys/arch/mvme88k/mvme88k/m197_cmmu.c
deleted file mode 100644
index d60af287134..00000000000
--- a/sys/arch/mvme88k/mvme88k/m197_cmmu.c
+++ /dev/null
@@ -1,800 +0,0 @@
-/* $OpenBSD: m197_cmmu.c,v 1.11 2001/11/27 05:37:02 miod Exp $ */
-/*
- * Copyright (c) 1998 Steve Murphree, Jr.
- * Copyright (c) 1996 Nivas Madhur
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Nivas Madhur.
- * 4. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-/*
- * Mach Operating System
- * Copyright (c) 1993-1991 Carnegie Mellon University
- * Copyright (c) 1991 OMRON Corporation
- * All Rights Reserved.
- *
- * Permission to use, copy, modify and distribute this software and its
- * documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
- * School of Computer Science
- * Carnegie Mellon University
- * Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
-#include <sys/param.h>
-#include <sys/types.h>
-#include <sys/simplelock.h>
-
-#include <machine/board.h>
-#include <machine/cpus.h>
-#include <machine/cpu_number.h>
-#include <machine/locore.h>
-#include <machine/m88110.h>
-#include <machine/m88110_mmu.h>
-
-#ifdef DDB
-#include <ddb/db_output.h>
-#endif
-
-#ifdef DEBUG
-#define DB_CMMU 0x4000 /* MMU debug */
-unsigned int debuglevel = 0;
-#define dprintf(_L_,_X_) { if (debuglevel & (_L_)) { unsigned int psr = disable_interrupts_return_psr(); printf("%d: ", cpu_number()); printf _X_; set_psr(psr); } }
-#else
-#define dprintf(_L_,_X_)
-#endif
-
-#undef SHADOW_BATC /* don't use BATCs for now XXX nivas */
-
-/*
- * CMMU(cpu,data) Is the cmmu struct for the named cpu's indicated cmmu.
- * REGS(cpu,data) is the actual register structure.
- */
-
-#define CMMU(cpu, data) cpu_cmmu[(cpu)].pair[(data)?DATA_CMMU:INST_CMMU]
-#define REGS(cpu, data) (*CMMU(cpu, data)->cmmu_regs)
-
-/* prototypes */
-void m197_cmmu_store __P((int, int, unsigned));
-int m197_cmmu_alive __P((int));
-unsigned m197_cmmu_get __P((int, int));
-void m197_cmmu_set __P((int, unsigned, int, int, int, int, vm_offset_t));
-int probe_mmu __P((vm_offset_t, int));
-void m197_cmmu_sync_cache __P((vm_offset_t, int));
-void m197_cmmu_sync_inval_cache __P((vm_offset_t, int));
-void m197_cmmu_inval_cache __P((vm_offset_t, int));
-
-/*
- * This lock protects the cmmu SAR and SCR's; other ports
- * can be accessed without locking it
- *
- * May be used from "db_interface.c".
- */
-
-#ifdef CMMU_DEBUG
-void
-m197_show_apr(unsigned value)
-{
- union apr_template apr_template;
- apr_template.bits = value;
-
- printf("table @ 0x%x000", apr_template.field.st_base);
- if (apr_template.field.wt) printf(", writethrough");
- if (apr_template.field.g) printf(", global");
- if (apr_template.field.ci) printf(", cache inhibit");
- if (apr_template.field.te) printf(", valid");
- else printf(", not valid");
- printf("\n");
-}
-
-void
-m197_show_sctr(unsigned value)
-{
- union {
- unsigned bits;
- struct {
- unsigned :16,
- pe: 1,
- se: 1,
- pr: 1,
- :13;
- } fields;
- } sctr;
- sctr.bits = value;
- printf("%spe, %sse %spr]\n",
- sctr.fields.pe ? "" : "!",
- sctr.fields.se ? "" : "!",
- sctr.fields.pr ? "" : "!");
-}
-#endif
-
-void
-m197_setup_board_config(void)
-{
- /* dummy routine */
- m197_setup_cmmu_config();
- return;
-}
-
-void
-m197_setup_cmmu_config(void)
-{
- /* we can print something here... */
- cpu_sets[0] = 1; /* This cpu installed... */
- return;
-}
-
-void m197_cmmu_dump_config(void)
-{
- /* dummy routine */
- return;
-}
-
-void
-m197_cmmu_store(int mmu, int reg, unsigned val)
-{
-}
-
-int
-m197_cmmu_alive(int mmu)
-{
- return 1;
-}
-
-unsigned
-m197_cmmu_get(int mmu, int reg)
-{
- return 0;
-}
-
-/*
- * This function is called by the MMU module and pokes values
- * into the CMMU's registers.
- */
-void
-m197_cmmu_set(int reg, unsigned val, int flags,
- int num, int mode, int access, vm_offset_t addr)
-{
- return;
-}
-
-#ifdef DDB
-/*
- * Used by DDB for cache probe functions
- */
-unsigned m197_cmmu_get_by_mode(int cpu, int mode)
-{
- return 0;
-}
-#endif
-
-/*
- * Should only be called after the calling cpus knows its cpu
- * number and master/slave status . Should be called first
- * by the master, before the slaves are started.
-*/
-void
-m197_cpu_configuration_print(int master)
-{
- int pid = read_processor_identification_register();
- int proctype = (pid & 0xff00) >> 8;
- int procvers = (pid & 0xe) >> 1;
- int cpu = cpu_number();
- struct simplelock print_lock;
-
- if (master)
- simple_lock_init(&print_lock);
-
- simple_lock(&print_lock);
-
- printf("Processor %d: ", cpu);
- if (proctype)
- printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n",
- proctype, procvers);
- else
- printf("M88110 Version 0x%x\n", procvers);
-
- simple_unlock(&print_lock);
- return;
-}
-
-/*
- * CMMU initialization routine
- */
-void m197_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel);
-
-void
-m197_cmmu_init(void)
-{
- int i;
- unsigned tmp;
- extern void *kernel_sdt;
- unsigned lba, pba, value;
-
- /* clear BATCs */
- for (i=0; i<8; i++) {
- m197_cmmu_set_pair_batc_entry(0, i, 0);
- }
- /* clear PATCs */
- for (i=0; i<32; i++) {
- m197_load_patc(i, 0, 0, 0);
- }
- set_ictl(CMMU_ICTL_DID /* Double instruction disable */
- | CMMU_ICTL_MEN
- | CMMU_ICTL_HTEN);
-
-
- set_dctl(CMMU_DCTL_MEN
- | CMMU_DCTL_HTEN);
-
- set_icmd(CMMU_ICMD_INV_ITIC); /* clear instruction cache */
- set_dcmd(CMMU_DCMD_INV_ALL); /* clear data cache */
-
- tmp = (0x00000 << 12) | /* segment table base address */
- AREA_D_WT | /* write through */
- AREA_D_G | /* global */
- ! AREA_D_TE ; /* not translation enable */
-
- set_isap(tmp);
- set_dsap(tmp);
-
- set_isr(0);
- set_ilar(0);
- set_ipar(0);
- set_dsr(0);
- set_dlar(0);
- set_dpar(0);
-
- lba = pba = (unsigned)&kernel_sdt;
- lba &= ~0x7FFFF;
- pba = pba >> 13;
- pba &= ~0x3F;
- value = lba | pba | 0x20 | 0x01;
-
- m197_cmmu_set_pair_batc_entry(0, 0, value);
-
-}
-
-/*
- * Just before poweroff or reset....
- */
-void
-m197_cmmu_shutdown_now(void)
-{
-}
-
-/*
- * enable parity
- */
-void
-m197_cmmu_parity_enable(void)
-{
-#ifdef PARITY_ENABLE
-#endif /* PARITY_ENABLE */
-}
-
-/*
- * Find out the CPU number from accessing CMMU
- * Better be at splhigh, or even better, with interrupts
- * disabled.
- */
-#define ILLADDRESS U(0x0F000000) /* any faulty address */
-
-unsigned
-m197_cmmu_cpu_number(void)
-{
- return 0; /* to make compiler happy */
-}
-
-/**
- ** Functions that actually modify CMMU registers.
- **/
-void
-m197_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x)
-{
- panic("m197_cmmu_remote_set() called!");
-}
-
-/*
- * cmmu_cpu_lock should be held when called if read
- * the CMMU_SCR or CMMU_SAR.
- */
-unsigned
-m197_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data)
-{
- panic("m197_cmmu_remote_get() called!");
- return 0;
-}
-
-/* Needs no locking - read only registers */
-unsigned
-m197_cmmu_get_idr(unsigned data)
-{
- return 0; /* todo */
-}
-
-int
-probe_mmu(vm_offset_t va, int data)
-{
- unsigned result;
- if (data) {
- set_dsar((unsigned)va);
- set_dcmd(CMMU_DCMD_PRB_SUPR);
- result = get_dsr();
- if (result & CMMU_DSR_PH)
- return 1;
- else
- return 0;
- } else {
- set_isar((unsigned)va);
- set_icmd(CMMU_ICMD_PRB_SUPR);
- result = get_isr();
- if (result & CMMU_ISR_BH)
- return 2;
- else if (result & CMMU_ISR_PH)
- return 1;
- else
- return 0;
- }
- return 0;
-}
-
-void
-m197_cmmu_set_sapr(unsigned ap)
-{
- int result;
- set_icmd(CMMU_ICMD_INV_SATC);
- set_dcmd(CMMU_DCMD_INV_SATC);
- /* load an entry pointing to seg table into PATC */
- /* Don't forget to set it valid */
-
- m197_load_patc(0, (vm_offset_t)ap, (vm_offset_t)(ap | 0x1), 1);
- if (!(result = probe_mmu((vm_offset_t) ap, 1))) {
- printf("Didn't make it!!!!\n");
- return;
- } else {
- if (result == 2)
- printf("area pointer is in BATC.\n");
- if (result == 1)
- printf("area pointer is in PATC.\n");
- }
-
- set_isap(ap);
- set_dsap(ap);
-}
-
-void
-m197_cmmu_remote_set_sapr(unsigned cpu, unsigned ap)
-{
- m197_cmmu_set_sapr(ap);
-}
-
-void
-m197_cmmu_set_uapr(unsigned ap)
-{
- set_iuap(ap);
- set_duap(ap);
-}
-
-/*
- * Set batc entry number entry_no to value in
- * the data or instruction cache depending on data.
- *
- * Except for the cmmu_init, this function, m197_cmmu_set_pair_batc_entry,
- * and m197_cmmu_pmap_activate are the only functions which may set the
- * batc values.
- */
-void
-m197_cmmu_set_batc_entry(
- unsigned cpu,
- unsigned entry_no,
- unsigned data, /* 1 = data, 0 = instruction */
- unsigned value) /* the value to stuff */
-{
- if (data) {
- set_dir(entry_no);
- set_dbp(value);
- } else {
- set_iir(entry_no);
- set_ibp(value);
- }
-}
-
-/*
- * Set batc entry number entry_no to value in
- * the data and instruction cache for the named CPU.
- */
-void
-m197_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value)
-/* the value to stuff into the batc */
-{
- m197_cmmu_set_batc_entry(cpu, entry_no, 1, value);
- m197_cmmu_set_batc_entry(cpu, entry_no, 0, value);
-}
-
-/**
- ** Functions that invalidate TLB entries.
- **/
-
-/*
- * flush any tlb
- * Some functionality mimiced in m197_cmmu_pmap_activate.
- */
-void
-m197_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size)
-{
- register int s = splhigh();
- if (kernel) {
- set_icmd(CMMU_ICMD_INV_SATC);
- set_dcmd(CMMU_DCMD_INV_SATC);
- } else {
- set_icmd(CMMU_ICMD_INV_UATC);
- set_dcmd(CMMU_DCMD_INV_UATC);
- }
- splx(s);
-}
-
-/*
- * flush my personal tlb
- */
-void
-m197_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size)
-{
- int cpu;
- cpu = cpu_number();
- m197_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
-}
-
-/*
- * New fast stuff for pmap_activate.
- * Does what a few calls used to do.
- * Only called from pmap.c's _pmap_activate().
- */
-void
-m197_cmmu_pmap_activate(
- unsigned cpu,
- unsigned uapr,
- batc_template_t i_batc[BATC_MAX],
- batc_template_t d_batc[BATC_MAX])
-{
- /* int entry_no;*/
-
- m197_cmmu_set_uapr(uapr);
-
- /*
- for (entry_no = 0; entry_no < 8; entry_no++) {
- m197_cmmu_set_batc_entry(cpu, entry_no, 0, i_batc[entry_no].bits);
- m197_cmmu_set_batc_entry(cpu, entry_no, 1, d_batc[entry_no].bits);
- }
- */
- /*
- * Flush the user TLB.
- * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES,
- * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL.
- */
- set_icmd(CMMU_ICMD_INV_UATC);
- set_dcmd(CMMU_DCMD_INV_UATC);
-}
-
-/**
- ** Functions that invalidate caches.
- **
- ** Cache invalidates require physical addresses. Care must be exercised when
- ** using segment invalidates. This implies that the starting physical address
- ** plus the segment length should be invalidated. A typical mistake is to
- ** extract the first physical page of a segment from a virtual address, and
- ** then expecting to invalidate when the pages are not physically contiguous.
- **
- ** We don't push Instruction Caches prior to invalidate because they are not
- ** snooped and never modified (I guess it doesn't matter then which form
- ** of the command we use then).
- **/
-/*
- * flush both Instruction and Data caches
- */
-void
-m197_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size)
-{
- register int s = splhigh();
- set_icmd(CMMU_ICMD_INV_ITIC);
- set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
- splx(s);
-}
-
-/*
- * flush both Instruction and Data caches
- */
-void
-m197_cmmu_flush_cache(vm_offset_t physaddr, int size)
-{
- int cpu = cpu_number();
- m197_cmmu_flush_remote_cache(cpu, physaddr, size);
-}
-
-/*
- * flush Instruction caches
- */
-void
-m197_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size)
-{
- register int s = splhigh();
-
- set_icmd(CMMU_ICMD_INV_ITIC);
-
- splx(s);
-}
-
-/*
- * flush Instruction caches
- */
-void
-m197_cmmu_flush_inst_cache(vm_offset_t physaddr, int size)
-{
- int cpu;
- cpu = cpu_number();
- m197_cmmu_flush_remote_inst_cache(cpu, physaddr, size);
-}
-
-/*
- * flush data cache
- */
-void
-m197_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size)
-{
- register int s = splhigh();
- set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
- splx(s);
-}
-
-/*
- * flush data cache
- */
-void
-m197_cmmu_flush_data_cache(vm_offset_t physaddr, int size)
-{
- int cpu;
- cpu = cpu_number();
- m197_cmmu_flush_remote_data_cache(cpu, physaddr, size);
-}
-
-/*
- * sync dcache (and icache too)
- */
-void
-m197_cmmu_sync_cache(vm_offset_t physaddr, int size)
-{
- register int s = splhigh();
- int cpu;
- cpu = cpu_number();
- /* set_mmureg(CMMU_ICTL, CMMU_ICMD_INV_TIC); */
- set_dcmd(CMMU_DCMD_FLUSH_ALL);
-
- splx(s);
-}
-
-void
-m197_cmmu_sync_inval_cache(vm_offset_t physaddr, int size)
-{
- register int s = splhigh();
- int cpu;
- cpu = cpu_number();
-
- set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
- splx(s);
-}
-
-void
-m197_cmmu_inval_cache(vm_offset_t physaddr, int size)
-{
- register int s = splhigh();
- int cpu;
- cpu = cpu_number();
- set_icmd(CMMU_ICMD_INV_ITIC);
- set_dcmd(CMMU_DCMD_INV_ALL);
- splx(s);
-}
-
-void
-m197_dma_cachectl(vm_offset_t va, int size, int op)
-{
- if (op == DMA_CACHE_SYNC)
- m197_cmmu_sync_cache(kvtop(va), size);
- else if (op == DMA_CACHE_SYNC_INVAL)
- m197_cmmu_sync_inval_cache(kvtop(va), size);
- else
- m197_cmmu_inval_cache(kvtop(va), size);
-}
-
-#ifdef DDB
-
- #define VV_EX_UNMOD 0
- #define VV_EX_MOD 1
- #define VV_SHARED_UNMOD 2
- #define VV_INVALID 3
-
- #define D(UNION, LINE) \
- ((LINE) == 3 ? (UNION).field.d3 : \
- ((LINE) == 2 ? (UNION).field.d2 : \
- ((LINE) == 1 ? (UNION).field.d1 : \
- ((LINE) == 0 ? (UNION).field.d0 : ~0))))
- #define VV(UNION, LINE) \
- ((LINE) == 3 ? (UNION).field.vv3 : \
- ((LINE) == 2 ? (UNION).field.vv2 : \
- ((LINE) == 1 ? (UNION).field.vv1 : \
- ((LINE) == 0 ? (UNION).field.vv0 : ~0))))
-
-
- #undef VEQR_ADDR
- #define VEQR_ADDR 0
-
-/*
- * Show (for debugging) how the given CMMU translates the given ADDRESS.
- * If cmmu == -1, the data cmmu for the current cpu is used.
- */
-void
-m197_cmmu_show_translation(unsigned address,
- unsigned supervisor_flag,
- unsigned verbose_flag,
- int cmmu_num)
-{
- /*
- * A virtual address is split into three fields. Two are used as
- * indicies into tables (segment and page), and one is an offset into
- * a page of memory.
- */
- /*
- union {
- unsigned bits;
- struct {
- unsigned segment_table_index:10,
- page_table_index:10,
- page_offset:12;
- } field;
- } virtual_address;
- */
-
-#ifdef DDB
- if (verbose_flag)
- db_printf("-------------------------------------------\n");
-#endif
-}
-
-
-void
-m197_cmmu_cache_state(unsigned addr, unsigned supervisor_flag)
-{
- /*
- static char *vv_name[4] =
- {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"};
- */
-}
-
-void
-m197_show_cmmu_info(unsigned addr)
-{
- m197_cmmu_cache_state(addr, 1);
-}
-#endif /* end if DDB */
-
-#define MSDTENT(addr, va) ((sdt_entry_t *)(addr + SDTIDX(va)))
-#define MPDTENT(addr, va) ((sdt_entry_t *)(addr + PDTIDX(va)))
-void
-m197_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel)
-{
- unsigned lpa, pfa, i;
-
- lpa = (unsigned)vaddr & 0xFFFFF000;
- if (kernel) {
- lpa |= 0x01;
- }
- pfa = (unsigned)paddr;
- i = entry << 5;
- set_iir(i);
- set_ippu(lpa);
- set_ippl(pfa);
- set_dir(i);
- set_dppu(lpa);
- set_dppl(lpa);
-}
-
-#define SDT_WP(sd_ptr) ((sd_ptr)->prot != 0)
-#define SDT_SUP(sd_ptr) ((sd_ptr)->sup != 0)
-#define PDT_WP(pte_ptr) ((pte_ptr)->prot != 0)
-#define PDT_SUP(pte_ptr) ((pte_ptr)->sup != 0)
-
-int
-m197_table_search(pmap_t map, vm_offset_t virt, int write, int kernel, int data)
-{
- sdt_entry_t *sdt;
- pt_entry_t *pte;
- unsigned lpa, i;
- static int entry_num = 0;
-
- if (map == (pmap_t)0)
- panic("m197_table_search: pmap is NULL");
-
- sdt = SDTENT(map, virt);
-
- /*
- * Check whether page table exist or not.
- */
- if (!SDT_VALID(sdt))
- return (4); /* seg fault */
-
- /* OK, it's valid. Now check permissions. */
- if (!kernel)
- if (SDT_SUP(sdt))
- return (6); /* Supervisor Violation */
- if (write)
- if (SDT_WP(sdt))
- return (7); /* Write Violation */
-
- pte = (pt_entry_t *)(((sdt + SDT_ENTRIES)->table_addr)<<PDT_SHIFT) + PDTIDX(virt);
-
- /*
- * Check whether page frame exist or not.
- */
- if (!PDT_VALID(pte))
- return (5); /* Page Fault */
-
- /* OK, it's valid. Now check permissions. */
- if (!kernel)
- if (PDT_SUP(sdt))
- return (6); /* Supervisor Violation */
- if (write)
- if (PDT_WP(sdt))
- return (7); /* Write Violation */
- /* If we get here, load the PATC. */
- if (entry_num > 32)
- entry_num = 0;
- lpa = (unsigned)virt & 0xFFFFF000;
- if (kernel)
- lpa |= 0x01;
- i = entry_num << 5;
- if (data) {
- set_dir(i); /* set PATC index */
- set_dppu(lpa); /* set logical address */
- set_dppl((unsigned)pte); /* set page fram address */
- } else {
- set_iir(i);
- set_ippu(lpa);
- set_ippl((unsigned)pte);
- }
- return 0;
-}
diff --git a/sys/arch/mvme88k/mvme88k/m88100_fp.S b/sys/arch/mvme88k/mvme88k/m88100_fp.S
index 5442c3e2b5c..a23f34530e2 100644
--- a/sys/arch/mvme88k/mvme88k/m88100_fp.S
+++ b/sys/arch/mvme88k/mvme88k/m88100_fp.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: m88100_fp.S,v 1.12 2001/11/18 01:43:33 miod Exp $ */
+/* $OpenBSD: m88100_fp.S,v 1.13 2001/12/13 08:55:52 smurph Exp $ */
/*
* Mach Operating System
* Copyright (c) 1991 Carnegie Mellon University
@@ -27,6 +27,8 @@
*/
/* Floating point trouble routines */
+#ifdef M88100
+
#include "assym.h"
#include <machine/trap.h>
#include <machine/asm.h>
@@ -2298,3 +2300,5 @@ Iwritesingle:
st r11, r3 [r2]
/* Return.. */
jmp r1
+#endif /* M88100 */
+
diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c
new file mode 100644
index 00000000000..364e95f3fa9
--- /dev/null
+++ b/sys/arch/mvme88k/mvme88k/m88110.c
@@ -0,0 +1,1107 @@
+/* $OpenBSD: m88110.c,v 1.1 2001/12/13 08:55:52 smurph Exp $ */
+/*
+ * Copyright (c) 1998 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Nivas Madhur.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Mach Operating System
+ * Copyright (c) 1993-1991 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+#ifdef M88110
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/simplelock.h>
+#include <machine/board.h>
+#include <machine/cpus.h>
+#include <machine/cpu_number.h>
+#include <machine/cmmu.h>
+#include <machine/locore.h>
+
+#define CMMU_DEBUG 1
+
+#ifdef DEBUG
+ #define DB_CMMU 0x4000 /* MMU debug */
+unsigned int debuglevel = 0;
+ #define dprintf(_L_,_X_) { if (debuglevel & (_L_)) { unsigned int psr = disable_interrupts_return_psr(); printf("%d: ", cpu_number()); printf _X_; set_psr(psr); } }
+#else
+ #define dprintf(_L_,_X_)
+#endif
+
+#ifdef DDB
+#include <ddb/db_output.h> /* db_printf() */
+#define DEBUG_MSG db_printf
+#define STATIC
+#else
+#define DEBUG_MSG printf
+#define STATIC static
+#endif /* DDB */
+
+/* kernel copy of PATC entries */
+unsigned patc_data_u[32];
+unsigned patc_data_l[32];
+unsigned patc_inst_u[32];
+unsigned patc_inst_l[32];
+
+#define INST 0
+#define DATA 1
+#define BOTH 2
+#define KERN 1
+#define USER 0
+
+/* FORWARDS */
+unsigned batc_val __P((unsigned phys, unsigned virt, unsigned prot));
+void patc_insert __P((unsigned upper, unsigned lower, int which));
+void patc_clear __P((void));
+void patc_sync __P((int which));
+void patc_load __P((int index, unsigned upper, unsigned lower, int which));
+void m88110_cmmu_sync_cache __P((vm_offset_t physaddr, int size));
+void m88110_cmmu_sync_inval_cache __P((vm_offset_t physaddr, int size));
+void m88110_cmmu_inval_cache __P((vm_offset_t physaddr, int size));
+int probe_mmu __P((vm_offset_t va, int data));
+
+/* This is the function table for the mc88110 built-in CMMUs */
+struct cmmu_p cmmu88110 = {
+ m88110_cmmu_init,
+ m88110_show_apr,
+ m88110_setup_board_config,
+ m88110_setup_cmmu_config,
+ m88110_cmmu_dump_config,
+ m88110_cpu_configuration_print,
+ m88110_cmmu_shutdown_now,
+ m88110_cmmu_parity_enable,
+ m88110_cmmu_cpu_number,
+ m88110_cmmu_remote_set,
+ m88110_cmmu_remote_get,
+ m88110_cmmu_get_idr,
+ m88110_cmmu_set_sapr,
+ m88110_cmmu_remote_set_sapr,
+ m88110_cmmu_set_uapr,
+ m88110_cmmu_set_batc_entry,
+ m88110_cmmu_set_pair_batc_entry,
+ m88110_cmmu_flush_remote_tlb,
+ m88110_cmmu_flush_tlb,
+ m88110_cmmu_pmap_activate,
+ m88110_cmmu_flush_remote_cache,
+ m88110_cmmu_flush_cache,
+ m88110_cmmu_flush_remote_inst_cache,
+ m88110_cmmu_flush_inst_cache,
+ m88110_cmmu_flush_remote_data_cache,
+ m88110_cmmu_flush_data_cache,
+ m88110_dma_cachectl,
+#ifdef DDB
+ m88110_cmmu_get_by_mode,
+ m88110_cmmu_show_translation,
+ m88110_cmmu_cache_state,
+ m88110_show_cmmu_info,
+#endif /* end if DDB */
+};
+
+void
+patc_load(int index, unsigned upper, unsigned lower, int which)
+{
+ /* sanity check!!! */
+ if (index > 31) {
+ panic("invalid PATC index %d!", index);
+ }
+ index = index << 5;
+ switch (which) {
+ case INST:
+ set_iir(index);
+ set_ippu(upper);
+ set_ippl(lower);
+ break;
+ case DATA:
+ set_dir(index);
+ set_dppu(upper);
+ set_dppl(lower);
+ break;
+ default:
+ panic("invalid PATC! Choose DATA or INST...");
+ }
+}
+
+void
+patc_sync(int which)
+{
+ int i;
+ switch (which) {
+ case BOTH:
+ for (i=0; i<32; i++) {
+ patc_load(i, patc_data_u[i], patc_data_l[i], DATA);
+ patc_load(i, patc_inst_u[i], patc_inst_l[i], INST);
+ }
+ break;
+ case INST:
+ for (i=0; i<32; i++) {
+ patc_load(i, patc_inst_u[i], patc_inst_l[i], INST);
+ }
+ break;
+ case DATA:
+ for (i=0; i<32; i++) {
+ patc_load(i, patc_data_u[i], patc_data_l[i], DATA);
+ }
+ break;
+ }
+}
+
+void
+patc_clear(void)
+{
+ int i;
+ for (i=0; i<32; i++) {
+ patc_data_u[i] = 0;
+ patc_data_l[i] = 0;
+ patc_inst_u[i] = 0;
+ patc_inst_l[i] = 0;
+ }
+ patc_sync(BOTH);
+}
+
+/* implement a FIFO on the PATC entries */
+void
+patc_insert(unsigned upper, unsigned lower, int which)
+{
+ int i;
+ switch(which){
+ case INST:
+ for (i=31; i>0; i--) {
+ patc_inst_u[i] = patc_inst_u[i-1];
+ patc_inst_l[i] = patc_inst_l[i-1];
+ }
+ patc_inst_u[0] = upper;
+ patc_inst_l[0] = lower;
+ patc_sync(INST);
+ break;
+ case DATA:
+ for (i=31; i>0; i--) {
+ patc_data_u[i] = patc_data_u[i-1];
+ patc_data_l[i] = patc_data_l[i-1];
+ }
+ patc_data_u[0] = upper;
+ patc_data_l[0] = lower;
+ patc_sync(DATA);
+ break;
+ case BOTH:
+ panic("patc_insert(): can't insert both INST and DATA.");
+ }
+}
+
+unsigned
+batc_val(unsigned phys, unsigned virt, unsigned prot)
+{
+ unsigned val = 0;
+ virt = (virt >> BATC_ADDR_SHIFT);
+ val |= (virt << BATC_LBA_SHIFT);
+ phys = (phys >> BATC_ADDR_SHIFT);
+ val |= (phys << BATC_PBA_SHIFT);
+ val |= prot;
+ return(val);
+}
+
+
+void
+m88110_show_apr(unsigned value)
+{
+ union apr_template apr_template;
+ apr_template.bits = value;
+
+ printf("table @ 0x%x000", apr_template.field.st_base);
+ if (apr_template.field.wt) printf(", writethrough");
+ if (apr_template.field.g) printf(", global");
+ if (apr_template.field.ci) printf(", cache inhibit");
+ if (apr_template.field.te) printf(", valid");
+ else printf(", not valid");
+ printf("\n");
+}
+
+void
+m88110_setup_board_config(void)
+{
+ /* dummy routine */
+ m88110_setup_cmmu_config();
+ return;
+}
+
+void
+m88110_setup_cmmu_config(void)
+{
+ /* we can print something here... */
+ cpu_sets[0] = 1; /* This cpu installed... */
+ return;
+}
+
+void m88110_cmmu_dump_config(void)
+{
+ /* dummy routine */
+ return;
+}
+
+#ifdef DDB
+/*
+ * Used by DDB for cache probe functions
+ */
+unsigned m88110_cmmu_get_by_mode(int cpu, int mode)
+{
+ CMMU_LOCK;
+ return 0;
+ CMMU_UNLOCK;
+}
+#endif
+
+/*
+ * Should only be called after the calling cpus knows its cpu
+ * number and master/slave status . Should be called first
+ * by the master, before the slaves are started.
+*/
+void
+m88110_cpu_configuration_print(int master)
+{
+ int pid = read_processor_identification_register();
+ int proctype = (pid & 0xff00) >> 8;
+ int procvers = (pid & 0xe) >> 1;
+ int cpu = cpu_number();
+ struct simplelock print_lock;
+
+ CMMU_LOCK;
+ if (master)
+ simple_lock_init(&print_lock);
+
+ simple_lock(&print_lock);
+
+ printf("Processor %d: ", cpu);
+ if (proctype)
+ printf("Architectural Revision 0x%x UNKNOWN CPU TYPE Version 0x%x\n",
+ proctype, procvers);
+ else
+ printf("M88110 Version 0x%x\n", procvers);
+
+ simple_unlock(&print_lock);
+ CMMU_UNLOCK;
+ return;
+}
+
+/*
+ * CMMU initialization routine
+ */
+void m88110_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel);
+
+void
+m88110_cmmu_init(void)
+{
+ int i;
+
+ /* clear BATCs */
+ for (i=0; i<8; i++) {
+ m88110_cmmu_set_pair_batc_entry(0, i, 0);
+ }
+ /* clear PATCs */
+ patc_clear();
+
+ set_ictl(BATC_32M
+ | CMMU_ICTL_DID /* Double instruction disable */
+ | CMMU_ICTL_MEN
+ | CMMU_ICTL_CEN
+ | CMMU_ICTL_BEN
+ | CMMU_ICTL_HTEN);
+
+ set_dctl(BATC_32M
+ | CMMU_DCTL_MEN
+ | CMMU_DCTL_CEN
+ | CMMU_DCTL_SEN
+ | CMMU_DCTL_ADS
+ | CMMU_DCTL_HTEN);
+
+
+ mc88110_inval_inst(); /* clear instruction cache & TIC */
+ mc88110_inval_data(); /* clear data cache */
+ mc88410_inval(); /* clear external data cache */
+
+ set_dcmd(CMMU_DCMD_INV_SATC); /* invalidate ATCs */
+
+ set_isr(0);
+ set_ilar(0);
+ set_ipar(0);
+ set_dsr(0);
+ set_dlar(0);
+ set_dpar(0);
+}
+
+/*
+ * Just before poweroff or reset....
+ */
+void
+m88110_cmmu_shutdown_now(void)
+{
+ CMMU_LOCK;
+ CMMU_UNLOCK;
+}
+
+/*
+ * enable parity
+ */
+void
+m88110_cmmu_parity_enable(void)
+{
+#ifdef PARITY_ENABLE
+ CMMU_LOCK;
+ CMMU_UNLOCK;
+#endif /* PARITY_ENABLE */
+}
+
+/*
+ * Find out the CPU number from accessing CMMU
+ * Better be at splhigh, or even better, with interrupts
+ * disabled.
+ */
+#define ILLADDRESS U(0x0F000000) /* any faulty address */
+
+unsigned
+m88110_cmmu_cpu_number(void)
+{
+ return 0; /* to make compiler happy */
+}
+
+/**
+ ** Funcitons that actually modify CMMU registers.
+ **/
+void
+m88110_cmmu_remote_set(unsigned cpu, unsigned r, unsigned data, unsigned x)
+{
+ panic("m88110_cmmu_remote_set() called!\n");
+}
+
+/*
+ * cmmu_cpu_lock should be held when called if read
+ * the CMMU_SCR or CMMU_SAR.
+ */
+unsigned
+m88110_cmmu_remote_get(unsigned cpu, unsigned r, unsigned data)
+{
+ panic("m88110_cmmu_remote_get() called!\n");
+ return 0;
+}
+
+/* Needs no locking - read only registers */
+unsigned
+m88110_cmmu_get_idr(unsigned data)
+{
+ return 0; /* todo */
+}
+
+int
+probe_mmu(vm_offset_t va, int data)
+{
+ unsigned result;
+ if (data) {
+ CMMU_LOCK;
+ set_dsar((unsigned)va);
+ set_dcmd(CMMU_DCMD_PRB_SUPR);
+ result = get_dsr();
+ CMMU_UNLOCK;
+ if (result & CMMU_DSR_BH)
+ return 2;
+ else if (result & CMMU_DSR_PH)
+ return 1;
+ else
+ return 0;
+ } else {
+ CMMU_LOCK;
+ set_isar((unsigned)va);
+ set_icmd(CMMU_ICMD_PRB_SUPR);
+ result = get_isr();
+ CMMU_UNLOCK;
+ if (result & CMMU_ISR_BH)
+ return 2;
+ else if (result & CMMU_ISR_PH)
+ return 1;
+ else
+ return 0;
+ }
+ return 0;
+}
+
+void
+m88110_cmmu_set_sapr(unsigned ap)
+{
+#if 0
+ int result;
+#endif
+ unsigned ictl, dctl;
+ CMMU_LOCK;
+
+ set_icmd(CMMU_ICMD_INV_SATC);
+ set_dcmd(CMMU_DCMD_INV_SATC);
+
+ ictl = get_ictl();
+ dctl = get_dctl();
+ /* disabel translation */
+ set_ictl((ictl &~ CMMU_ICTL_MEN));
+ set_dctl((dctl &~ CMMU_DCTL_MEN));
+
+ set_isap(ap);
+ set_dsap(ap);
+
+ patc_clear();
+
+ set_icmd(CMMU_ICMD_INV_UATC);
+ set_icmd(CMMU_ICMD_INV_SATC);
+ set_dcmd(CMMU_DCMD_INV_UATC);
+ set_dcmd(CMMU_DCMD_INV_SATC);
+
+ /* restore MMU settings */
+ set_ictl(ictl);
+ set_dctl(dctl);
+
+ CMMU_UNLOCK;
+ return;
+}
+
+void
+m88110_cmmu_remote_set_sapr(unsigned cpu, unsigned ap)
+{
+ m88110_cmmu_set_sapr(ap);
+}
+
+void
+m88110_cmmu_set_uapr(unsigned ap)
+{
+ CMMU_LOCK;
+ set_iuap(ap);
+ set_duap(ap);
+ set_icmd(CMMU_ICMD_INV_UATC);
+ set_dcmd(CMMU_DCMD_INV_UATC);
+ mc88110_inval_inst();
+ CMMU_UNLOCK;
+}
+
+/*
+ * Set batc entry number entry_no to value in
+ * the data or instruction cache depending on data.
+ *
+ * Except for the cmmu_init, this function, m88110_cmmu_set_pair_batc_entry,
+ * and m88110_cmmu_pmap_activate are the only functions which may set the
+ * batc values.
+ */
+void
+m88110_cmmu_set_batc_entry(
+ unsigned cpu,
+ unsigned entry_no,
+ unsigned data, /* 1 = data, 0 = instruction */
+ unsigned value) /* the value to stuff */
+{
+ CMMU_LOCK;
+ if (data) {
+ set_dir(entry_no);
+ set_dbp(value);
+ } else {
+ set_iir(entry_no);
+ set_ibp(value);
+ }
+ CMMU_UNLOCK;
+}
+
+/*
+ * Set batc entry number entry_no to value in
+ * the data and instruction cache for the named CPU.
+ */
+void
+m88110_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value)
+/* the value to stuff into the batc */
+{
+ m88110_cmmu_set_batc_entry(cpu, entry_no, 1, value);
+ m88110_cmmu_set_batc_entry(cpu, entry_no, 0, value);
+}
+
+/**
+ ** Functions that invalidate TLB entries.
+ **/
+
+/*
+ * flush any tlb
+ * Some functionality mimiced in m88110_cmmu_pmap_activate.
+ */
+void
+m88110_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr, int size)
+{
+ register int s = splhigh();
+
+ CMMU_LOCK;
+ if (kernel) {
+ set_icmd(CMMU_ICMD_INV_SATC);
+ set_dcmd(CMMU_DCMD_INV_SATC);
+ } else {
+ set_icmd(CMMU_ICMD_INV_UATC);
+ set_dcmd(CMMU_DCMD_INV_UATC);
+ }
+ CMMU_UNLOCK;
+
+ splx(s);
+}
+
+/*
+ * flush my personal tlb
+ */
+void
+m88110_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size)
+{
+ int cpu;
+ cpu = cpu_number();
+ m88110_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
+}
+
+/*
+ * New fast stuff for pmap_activate.
+ * Does what a few calls used to do.
+ * Only called from pmap.c's _pmap_activate().
+ */
+void
+m88110_cmmu_pmap_activate(
+ unsigned cpu,
+ unsigned uapr,
+ batc_template_t i_batc[BATC_MAX],
+ batc_template_t d_batc[BATC_MAX])
+{
+ m88110_cmmu_set_uapr(uapr);
+
+ /*
+ for (entry_no = 0; entry_no < 8; entry_no++) {
+ m88110_cmmu_set_batc_entry(cpu, entry_no, 0, i_batc[entry_no].bits);
+ m88110_cmmu_set_batc_entry(cpu, entry_no, 1, d_batc[entry_no].bits);
+ }
+ */
+ /*
+ * Flush the user TLB.
+ * IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES,
+ * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL.
+ */
+ set_icmd(CMMU_ICMD_INV_UATC);
+ set_dcmd(CMMU_DCMD_INV_UATC);
+}
+
+/**
+ ** Functions that invalidate caches.
+ **
+ ** Cache invalidates require physical addresses. Care must be exercised when
+ ** using segment invalidates. This implies that the starting physical address
+ ** plus the segment length should be invalidated. A typical mistake is to
+ ** extract the first physical page of a segment from a virtual address, and
+ ** then expecting to invalidate when the pages are not physically contiguous.
+ **
+ ** We don't push Instruction Caches prior to invalidate because they are not
+ ** snooped and never modified (I guess it doesn't matter then which form
+ ** of the command we use then).
+ **/
+
+/*
+ * Care must be taken to avoid flushing the data cache when
+ * the data cache is not on! From the 0F92L Errata Documentation
+ * Package, Version 1.1
+ */
+
+/*
+ * flush both Instruction and Data caches
+ */
+void
+m88110_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size)
+{
+ register int s = splhigh();
+
+ mc88110_inval_inst();
+ mc88110_flush_data();
+ mc88410_flush();
+ splx(s);
+}
+
+/*
+ * flush both Instruction and Data caches
+ */
+void
+m88110_cmmu_flush_cache(vm_offset_t physaddr, int size)
+{
+ int cpu = cpu_number();
+
+ m88110_cmmu_flush_remote_cache(cpu, physaddr, size);
+}
+
+/*
+ * flush Instruction caches
+ */
+void
+m88110_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size)
+{
+ register int s = splhigh();
+
+ mc88110_inval_inst();
+ splx(s);
+}
+
+/*
+ * flush Instruction caches
+ */
+void
+m88110_cmmu_flush_inst_cache(vm_offset_t physaddr, int size)
+{
+ int cpu;
+
+ cpu = cpu_number();
+ m88110_cmmu_flush_remote_inst_cache(cpu, physaddr, size);
+}
+
+/*
+ * flush data cache
+ */
+void
+m88110_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size)
+{
+ register int s = splhigh();
+
+ mc88110_flush_data();
+ mc88410_flush();
+ splx(s);
+}
+
+/*
+ * flush data cache
+ */
+void
+m88110_cmmu_flush_data_cache(vm_offset_t physaddr, int size)
+{
+ int cpu;
+
+ cpu = cpu_number();
+ m88110_cmmu_flush_remote_data_cache(cpu, physaddr, size);
+}
+
+/*
+ * sync dcache (and icache too)
+ */
+void
+m88110_cmmu_sync_cache(vm_offset_t physaddr, int size)
+{
+ register int s = splhigh();
+
+ mc88110_inval_inst();
+ mc88110_flush_data();
+ mc88410_flush();
+ splx(s);
+}
+
+void
+m88110_cmmu_sync_inval_cache(vm_offset_t physaddr, int size)
+{
+ register int s = splhigh();
+
+ mc88110_sync_data();
+ mc88410_sync();
+ splx(s);
+}
+
+void
+m88110_cmmu_inval_cache(vm_offset_t physaddr, int size)
+{
+ register int s = splhigh();
+
+ mc88110_inval_inst();
+ mc88110_inval_data();
+ mc88410_inval();
+ splx(s);
+}
+
+void
+m88110_dma_cachectl(vm_offset_t va, int size, int op)
+{
+ if (op == DMA_CACHE_SYNC)
+ m88110_cmmu_sync_cache(kvtop(va), size);
+ else if (op == DMA_CACHE_SYNC_INVAL)
+ m88110_cmmu_sync_inval_cache(kvtop(va), size);
+ else
+ m88110_cmmu_inval_cache(kvtop(va), size);
+}
+
+#ifdef DDB
+
+ #define VV_EX_UNMOD 0
+ #define VV_EX_MOD 1
+ #define VV_SHARED_UNMOD 2
+ #define VV_INVALID 3
+
+ #define D(UNION, LINE) \
+ ((LINE) == 3 ? (UNION).field.d3 : \
+ ((LINE) == 2 ? (UNION).field.d2 : \
+ ((LINE) == 1 ? (UNION).field.d1 : \
+ ((LINE) == 0 ? (UNION).field.d0 : ~0))))
+ #define VV(UNION, LINE) \
+ ((LINE) == 3 ? (UNION).field.vv3 : \
+ ((LINE) == 2 ? (UNION).field.vv2 : \
+ ((LINE) == 1 ? (UNION).field.vv1 : \
+ ((LINE) == 0 ? (UNION).field.vv0 : ~0))))
+
+
+ #undef VEQR_ADDR
+ #define VEQR_ADDR 0
+
+/*
+ * Show (for debugging) how the given CMMU translates the given ADDRESS.
+ * If cmmu == -1, the data cmmu for the current cpu is used.
+ */
+void
+m88110_cmmu_show_translation(unsigned address,
+ unsigned supervisor_flag,
+ unsigned verbose_flag,
+ int cmmu_num)
+{
+ /*
+ * A virtual address is split into three fields. Two are used as
+ * indicies into tables (segment and page), and one is an offset into
+ * a page of memory.
+ */
+ union {
+ unsigned bits;
+ struct {
+ unsigned segment_table_index:10,
+ page_table_index:10,
+ page_offset:12;
+ } field;
+ } virtual_address;
+ unsigned value;
+ unsigned result;
+ unsigned probeaddr;
+
+ if (verbose_flag)
+ db_printf("-------------------------------------------\n");
+
+ if (supervisor_flag)
+ value = get_dsap();
+ else
+ value = get_duap();
+
+ /******* SEE WHAT A PROBE SAYS (if not a thread) ***********/
+
+ set_dsar(address);
+ if (supervisor_flag) {
+ set_dcmd(CMMU_DCMD_PRB_SUPR);
+ } else {
+ set_dcmd(CMMU_DCMD_PRB_USER);
+ }
+ result = get_dsr();
+ probeaddr = get_dsar();
+ if (verbose_flag > 1)
+ DEBUG_MSG("probe of 0x%08x returns dsr=0x%08x\n",
+ address, result);
+ if (result & CMMU_DSR_PH || result & CMMU_DSR_BH) {
+ DEBUG_MSG("probe of 0x%08x returns phys=0x%x",
+ address, probeaddr);
+ if (result & CMMU_DSR_CP) DEBUG_MSG(", copyback err");
+ if (result & CMMU_DSR_BE) DEBUG_MSG(", bus err");
+ if (result & CMMU_DSR_TBE) DEBUG_MSG(", table search bus error");
+ if (result & CMMU_DSR_SU) DEBUG_MSG(", sup prot");
+ if (result & CMMU_DSR_WE) DEBUG_MSG(", write prot");
+ if (result & CMMU_DSR_PH) DEBUG_MSG(", PATC");
+ if (result & CMMU_DSR_BH) DEBUG_MSG(", BATC");
+ } else {
+ DEBUG_MSG("probe of 0x%08x missed the ATCs");
+ }
+ DEBUG_MSG(".\n");
+
+ /******* INTERPRET AREA DESCRIPTOR *********/
+ {
+ union apr_template apr_template;
+ apr_template.bits = value;
+ if (verbose_flag > 1) {
+ DEBUG_MSG(" %cAPR is 0x%08x\n",
+ supervisor_flag ? 'S' : 'U', apr_template.bits);
+ }
+ DEBUG_MSG(" %cAPR: SegTbl: 0x%x000p",
+ supervisor_flag ? 'S' : 'U', apr_template.field.st_base);
+ if (apr_template.field.wt) DEBUG_MSG(", WTHRU");
+ else DEBUG_MSG(", !wthru");
+ if (apr_template.field.g) DEBUG_MSG(", GLOBAL");
+ else DEBUG_MSG(", !global");
+ if (apr_template.field.ci) DEBUG_MSG(", $INHIBIT");
+ else DEBUG_MSG(", $ok");
+ if (apr_template.field.te) DEBUG_MSG(", VALID");
+ else DEBUG_MSG(", !valid");
+ DEBUG_MSG(".\n");
+
+ /* if not valid, done now */
+ if (apr_template.field.te == 0) {
+ DEBUG_MSG("<would report an error, valid bit not set>\n");
+ return;
+ }
+ value = apr_template.field.st_base << 12; /* now point to seg page */
+ }
+
+ /* translate value from physical to virtual */
+ if (verbose_flag)
+ DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
+ value += VEQR_ADDR;
+
+ virtual_address.bits = address;
+
+ /****** ACCESS SEGMENT TABLE AND INTERPRET SEGMENT DESCRIPTOR *******/
+ {
+ union sdt_entry_template std_template;
+ if (verbose_flag)
+ DEBUG_MSG("will follow to entry %d of page at 0x%x...\n",
+ virtual_address.field.segment_table_index, value);
+ value |= virtual_address.field.segment_table_index *
+ sizeof(struct sdt_entry);
+
+ if (badwordaddr((vm_offset_t)value)) {
+ DEBUG_MSG("ERROR: unable to access page at 0x%08x.\n", value);
+ return;
+ }
+
+ std_template.bits = *(unsigned *)value;
+ if (verbose_flag > 1)
+ DEBUG_MSG("SEG DESC @0x%x is 0x%08x\n", value, std_template.bits);
+ DEBUG_MSG("SEG DESC @0x%x: PgTbl: 0x%x000",
+ value, std_template.sdt_desc.table_addr);
+ if (std_template.sdt_desc.wt) DEBUG_MSG(", WTHRU");
+ else DEBUG_MSG(", !wthru");
+ if (std_template.sdt_desc.sup) DEBUG_MSG(", S-PROT");
+ else DEBUG_MSG(", UserOk");
+ if (std_template.sdt_desc.g) DEBUG_MSG(", GLOBAL");
+ else DEBUG_MSG(", !global");
+ if (std_template.sdt_desc.no_cache) DEBUG_MSG(", $INHIBIT");
+ else DEBUG_MSG(", $ok");
+ if (std_template.sdt_desc.prot) DEBUG_MSG(", W-PROT");
+ else DEBUG_MSG(", WriteOk");
+ if (std_template.sdt_desc.dtype) DEBUG_MSG(", VALID");
+ else DEBUG_MSG(", !valid");
+ DEBUG_MSG(".\n");
+
+ /* if not valid, done now */
+ if (std_template.sdt_desc.dtype == 0) {
+ DEBUG_MSG("<would report an error, STD entry not valid>\n");
+ return;
+ }
+ value = std_template.sdt_desc.table_addr << 12;
+ }
+
+ /* translate value from physical to virtual */
+ if (verbose_flag)
+ DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
+ value += VEQR_ADDR;
+
+ /******* PAGE TABLE *********/
+ {
+ union pte_template pte_template;
+ if (verbose_flag)
+ DEBUG_MSG("will follow to entry %d of page at 0x%x...\n",
+ virtual_address.field.page_table_index, value);
+ value |= virtual_address.field.page_table_index *
+ sizeof(struct pt_entry);
+
+ if (badwordaddr((vm_offset_t)value)) {
+ DEBUG_MSG("error: unable to access page at 0x%08x.\n", value);
+
+ return;
+ }
+
+ pte_template.bits = *(unsigned *)value;
+ if (verbose_flag > 1)
+ DEBUG_MSG("PAGE DESC @0x%x is 0x%08x.\n", value, pte_template.bits);
+ DEBUG_MSG("PAGE DESC @0x%x: page @%x000",
+ value, pte_template.pte.pfn);
+ if (pte_template.pte.wired) DEBUG_MSG(", WIRE");
+ else DEBUG_MSG(", !wire");
+ if (pte_template.pte.wt) DEBUG_MSG(", WTHRU");
+ else DEBUG_MSG(", !wthru");
+ if (pte_template.pte.sup) DEBUG_MSG(", S-PROT");
+ else DEBUG_MSG(", UserOk");
+ if (pte_template.pte.g) DEBUG_MSG(", GLOBAL");
+ else DEBUG_MSG(", !global");
+ if (pte_template.pte.ci) DEBUG_MSG(", $INHIBIT");
+ else DEBUG_MSG(", $ok");
+ if (pte_template.pte.modified) DEBUG_MSG(", MOD");
+ else DEBUG_MSG(", !mod");
+ if (pte_template.pte.pg_used) DEBUG_MSG(", USED");
+ else DEBUG_MSG(", !used");
+ if (pte_template.pte.prot) DEBUG_MSG(", W-PROT");
+ else DEBUG_MSG(", WriteOk");
+ if (pte_template.pte.dtype) DEBUG_MSG(", VALID");
+ else DEBUG_MSG(", !valid");
+ DEBUG_MSG(".\n");
+
+ /* if not valid, done now */
+ if (pte_template.pte.dtype == 0) {
+ DEBUG_MSG("<would report an error, PTE entry not valid>\n");
+ return;
+ }
+
+ value = pte_template.pte.pfn << 12;
+ if (verbose_flag)
+ DEBUG_MSG("will follow to byte %d of page at 0x%x...\n",
+ virtual_address.field.page_offset, value);
+ value |= virtual_address.field.page_offset;
+
+ if (badwordaddr((vm_offset_t)value)) {
+ DEBUG_MSG("error: unable to access page at 0x%08x.\n", value);
+ return;
+ }
+ }
+
+ /* translate value from physical to virtual */
+ if (verbose_flag)
+ DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
+ value += VEQR_ADDR;
+
+ DEBUG_MSG("WORD at 0x%x is 0x%08x.\n", value, *(unsigned *)value);
+}
+
+
+void
+m88110_cmmu_cache_state(unsigned addr, unsigned supervisor_flag)
+{
+#ifdef not_yet
+ static char *vv_name[4] =
+ {"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"};
+ int cmmu_num;
+#endif
+}
+
+void
+m88110_show_cmmu_info(unsigned addr)
+{
+ m88110_cmmu_cache_state(addr, 1);
+}
+#endif /* end if DDB */
+
+#define MSDTENT(addr, va) ((sdt_entry_t *)(addr + SDTIDX(va)))
+#define MPDTENT(addr, va) ((sdt_entry_t *)(addr + PDTIDX(va)))
+void
+m88110_load_patc(int entry, vm_offset_t vaddr, vm_offset_t paddr, int kernel)
+{
+ unsigned long lpa, pfa, i;
+
+ lpa = (unsigned)vaddr & 0xFFFFF000;
+ if (kernel) {
+ lpa |= 0x01;
+ }
+ pfa = (unsigned)paddr & 0xFFFFF000;
+ pfa |= 0x01;
+ i = entry << 5;
+ set_iir(i);
+ set_ippu(lpa);
+ set_ippl(pfa);
+ set_dir(i);
+ set_dppu(lpa);
+ set_dppl(lpa);
+}
+
+#define SDT_WP(sd_ptr) ((sd_ptr)->prot != 0)
+#define SDT_SUP(sd_ptr) ((sd_ptr)->sup != 0)
+#define PDT_WP(pte_ptr) ((pte_ptr)->prot != 0)
+#define PDT_SUP(pte_ptr) ((pte_ptr)->sup != 0)
+
+int
+m88110_table_search(pmap_t map, vm_offset_t virt, int write, int kernel, int data)
+{
+ sdt_entry_t *sdt;
+ pt_entry_t *pte;
+ unsigned long lpa, i;
+ static unsigned int entry_num = 0;
+
+ if (map == (pmap_t)0)
+ panic("m88110_table_search: pmap is NULL");
+
+ sdt = SDTENT(map, virt);
+
+ /*
+ * Check whether page table exist or not.
+ */
+ if (!SDT_VALID(sdt))
+ return (4); /* seg fault */
+
+ /* OK, it's valid. Now check permissions. */
+ if (!kernel && SDT_SUP(sdt))
+ return (6); /* Supervisor Violation */
+ if (write && SDT_WP(sdt))
+ return (7); /* Write Violation */
+
+ pte = (pt_entry_t *)(((sdt + SDT_ENTRIES)->table_addr)<<PDT_SHIFT) + PDTIDX(virt);
+ /*
+ * Check whether page frame exist or not.
+ */
+ if (!PDT_VALID(pte))
+ return (5); /* Page Fault */
+
+ /* OK, it's valid. Now check permissions. */
+ if (!kernel && PDT_SUP(pte))
+ return (6); /* Supervisor Violation */
+ if (write && PDT_WP(pte))
+ return (7); /* Write Violation */
+ /* If we get here, load the PATC. */
+ entry_num++;
+ if (entry_num > 32)
+ entry_num = 0;
+ lpa = (unsigned)virt & 0xFFFFF000;
+ if (kernel)
+ lpa |= 0x01;
+ i = entry_num << 5;
+ if (data) {
+ set_dir(i); /* set PATC index */
+ set_dppu(lpa); /* set logical address */
+ set_dppl((unsigned)pte); /* set page fram address */
+ } else {
+ set_iir(i);
+ set_ippu(lpa);
+ set_ippl((unsigned)pte);
+ }
+ return 0;
+}
+
+#endif /* M88110 */
+
+
diff --git a/sys/arch/mvme88k/mvme88k/m88110_fp.S b/sys/arch/mvme88k/mvme88k/m88110_fp.S
index a15f78297a1..fcc78632a35 100644
--- a/sys/arch/mvme88k/mvme88k/m88110_fp.S
+++ b/sys/arch/mvme88k/mvme88k/m88110_fp.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: m88110_fp.S,v 1.6 2001/08/24 22:53:15 miod Exp $ */
+/* $OpenBSD: m88110_fp.S,v 1.7 2001/12/13 08:55:52 smurph Exp $ */
/*
* Copyright (c) 1999 Steve Murphree, Jr.
* All rights reserved.
@@ -47,10 +47,11 @@
* 1) Unimplemented Floating Point Instruction
* 2) Floating Point Privilege Violation
*/
+#ifdef M88110
#include "assym.h"
-#include <machine/trap.h>
#include <machine/asm.h>
+#include <machine/trap.h>
.text
ENTRY(m88110_Xfp_precise)
@@ -82,7 +83,7 @@ ASGLOBAL(m88110_FPuimp)
st r3,r31,32 /* save exception frame */
or r2,r0,T_FPEPFLT /* load trap type */
or r3, r29, r0
- bsr _C_LABEL(trap197) /* trap */
+ bsr _m88110_trap /* trap */
ld r1,r31,36 /* recover return address */
addu r31,r31,40 /* deallocate stack */
jmp r1
@@ -93,7 +94,7 @@ ASGLOBAL(m88110_FPpriviol)
st r3,r31,32 /* save exception frame */
or r2,r0,T_PRIVINFLT /* load trap type */
or r3, r29, r0
- bsr _C_LABEL(trap197) /* trap */
+ bsr _m88110_trap /* trap */
ld r1,r31,36 /* recover return address */
addu r31,r31,40 /* deallocate stack */
jmp r1
@@ -105,7 +106,6 @@ ENTRY(set_tcfp)
jmp.n r1
fstcr r2, fcr0
-
/*************************************************************************
*************************************************************************
**
@@ -258,3 +258,5 @@ ENTRY(get_mmureg)
ldcr r2, cr26
regmark2: jmp.n r1
ldcr r2, cr25
+#endif /* M88110 */
+
diff --git a/sys/arch/mvme88k/mvme88k/m88110_mmu.S b/sys/arch/mvme88k/mvme88k/m88110_mmu.S
index b3230e4d49e..85ffc94b398 100644
--- a/sys/arch/mvme88k/mvme88k/m88110_mmu.S
+++ b/sys/arch/mvme88k/mvme88k/m88110_mmu.S
@@ -1,12 +1,45 @@
-# $OpenBSD: m88110_mmu.S,v 1.4 2001/08/07 22:12:31 miod Exp $
+/* $OpenBSD: m88110_mmu.S,v 1.5 2001/12/13 08:55:52 smurph Exp $ */
+/*
+ * Copyright (c) 2000 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Steve Murphree, Jr.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifdef M88110
#include <machine/asm.h>
/* set routines */
ENTRY(set_icmd)
+ FLUSH_PIPELINE
jmp.n r1
stcr r2, ICMD
ENTRY(set_ictl)
+ FLUSH_PIPELINE
jmp.n r1
stcr r2, ICTL
ENTRY(set_isar)
@@ -14,10 +47,12 @@ ENTRY(set_isar)
stcr r2, ISAR
ENTRY(set_isap)
FLUSH_PIPELINE
+ NOP
stcr r2, ISAP
jmp r1
ENTRY(set_iuap)
FLUSH_PIPELINE
+ NOP
stcr r2, IUAP
jmp r1
ENTRY(set_iir)
@@ -42,11 +77,15 @@ ENTRY(set_ipar)
jmp.n r1
stcr r2, IPAR
ENTRY(set_dcmd)
+ FLUSH_PIPELINE
jmp.n r1
stcr r2, DCMD
ENTRY(set_dctl)
- jmp.n r1
+ FLUSH_PIPELINE
stcr r2, DCTL
+ NOP
+ FLUSH_PIPELINE
+ jmp r1
ENTRY(set_dsar)
stcr r2, DSAR
NOP
@@ -55,11 +94,15 @@ ENTRY(set_dsap)
FLUSH_PIPELINE
NOP
stcr r2, DSAP
+ FLUSH_PIPELINE
+ NOP
jmp r1
ENTRY(set_duap)
FLUSH_PIPELINE
NOP
stcr r2, DUAP
+ FLUSH_PIPELINE
+ NOP
jmp r1
ENTRY(set_dir)
jmp.n r1
@@ -156,3 +199,5 @@ ENTRY(get_dlar)
ENTRY(get_dpar)
jmp.n r1
ldcr r2, DPAR
+#endif /* M88110 */
+
diff --git a/sys/arch/mvme88k/mvme88k/m18x_cmmu.c b/sys/arch/mvme88k/mvme88k/m8820x.c
index 817ffb42a6f..909bd98a729 100644
--- a/sys/arch/mvme88k/mvme88k/m18x_cmmu.c
+++ b/sys/arch/mvme88k/mvme88k/m8820x.c
@@ -1,6 +1,6 @@
-/* $OpenBSD: m18x_cmmu.c,v 1.14 2001/08/31 01:52:22 miod Exp $ */
+/* $OpenBSD: m8820x.c,v 1.1 2001/12/13 08:55:52 smurph Exp $ */
/*
- * Copyright (c) 1998 Steve Murphree, Jr.
+ * Copyright (c) 2001 Steve Murphree, Jr.
* Copyright (c) 1996 Nivas Madhur
* All rights reserved.
*
@@ -57,6 +57,7 @@
* any improvements or extensions that they make and grant Carnegie the
* rights to redistribute these changes.
*/
+#ifdef M88100
#include <sys/param.h>
#include <sys/types.h>
@@ -68,29 +69,28 @@
#include <machine/cpus.h>
#include <machine/cpu_number.h>
#include <machine/locore.h>
-#include <machine/m882xx.h>
-#ifdef DDB
-#include <ddb/db_output.h> /* db_printf() */
-#endif /* DDB */
+#include <machine/cmmu.h>
#ifdef DDB
+#include <ddb/db_output.h> /* db_printf() */
#define DEBUG_MSG db_printf
+#define STATIC
#else
#define DEBUG_MSG printf
+#define STATIC static
#endif /* DDB */
/* On some versions of 88200, page size flushes don't work. I am using
* sledge hammer approach till I find for sure which ones are bad XXX nivas */
#define BROKEN_MMU_MASK
-#define CMMU_DEBUG
#ifdef DEBUG
#define DB_CMMU 0x4000 /* MMU debug */
-unsigned int m18x_debuglevel = 0;
+unsigned int m8820x_debuglevel = 0;
#define dprintf(_L_,_X_) \
do { \
- if (m18x_debuglevel & (_L_)) { \
+ if (m8820x_debuglevel & (_L_)) { \
unsigned int psr = disable_interrupts_return_psr(); \
printf("%d: ", cpu_number()); \
printf _X_; \
@@ -102,6 +102,43 @@ unsigned int m18x_debuglevel = 0;
#endif
#undef SHADOW_BATC /* don't use BATCs for now XXX nivas */
+/* This is the function table for the mc8820x CMMUs */
+struct cmmu_p cmmu8820x = {
+ m8820x_cmmu_init,
+ m8820x_show_apr,
+ m8820x_setup_board_config,
+ m8820x_setup_cmmu_config,
+ m8820x_cmmu_dump_config,
+ m8820x_cpu_configuration_print,
+ m8820x_cmmu_shutdown_now,
+ m8820x_cmmu_parity_enable,
+ m8820x_cmmu_cpu_number,
+ m8820x_cmmu_remote_set,
+ m8820x_cmmu_remote_get,
+ m8820x_cmmu_get_idr,
+ m8820x_cmmu_set_sapr,
+ m8820x_cmmu_remote_set_sapr,
+ m8820x_cmmu_set_uapr,
+ m8820x_cmmu_set_batc_entry,
+ m8820x_cmmu_set_pair_batc_entry,
+ m8820x_cmmu_flush_remote_tlb,
+ m8820x_cmmu_flush_tlb,
+ m8820x_cmmu_pmap_activate,
+ m8820x_cmmu_flush_remote_cache,
+ m8820x_cmmu_flush_cache,
+ m8820x_cmmu_flush_remote_inst_cache,
+ m8820x_cmmu_flush_inst_cache,
+ m8820x_cmmu_flush_remote_data_cache,
+ m8820x_cmmu_flush_data_cache,
+ m8820x_dma_cachectl,
+#ifdef DDB
+ m8820x_cmmu_get_by_mode,
+ m8820x_cmmu_show_translation,
+ m8820x_cmmu_cache_state,
+ m8820x_show_cmmu_info;
+#endif /* end if DDB */
+};
+
struct cmmu_regs {
/* base + $000 */volatile unsigned idr;
/* base + $004 */volatile unsigned scr;
@@ -125,7 +162,7 @@ struct cmmu_regs {
/* The rest for the 88204 */
#define cssp0 cssp
- /* */ unsigned padding7[0x03];
+ /* */unsigned padding7[0x03];
/* base + $890 */volatile unsigned cssp1;
/* */unsigned padding8[0x03];
/* base + $8A0 */volatile unsigned cssp2;
@@ -133,7 +170,7 @@ struct cmmu_regs {
/* base + $8B0 */volatile unsigned cssp3;
};
-struct cmmu {
+struct m8820x_cmmu {
struct cmmu_regs *cmmu_regs; /* CMMU "base" area */
unsigned char cmmu_cpu; /* cpu number it is attached to */
unsigned char which; /* either INST_CMMU || DATA_CMMU */
@@ -172,27 +209,19 @@ error("ack gag barf!");
* May be used from "db_interface.c".
*/
-int vme188_config;
+STATIC int vme188_config;
+
+/* local prototypes */
+STATIC unsigned m8820x_cmmu_get __P((int mmu, int reg));
+STATIC void m8820x_cmmu_store __P((int, int, unsigned));
+STATIC void m8820x_cmmu_set __P((int, unsigned, int, int, int, int, vm_offset_t));
+STATIC void m8820x_cmmu_sync_cache __P((vm_offset_t, int));
+STATIC void m8820x_cmmu_sync_inval_cache __P((vm_offset_t, int));
+STATIC void m8820x_cmmu_inval_cache __P((vm_offset_t, int));
+STATIC int m8820x_cmmu_alive __P((int));
-/* prototypes */
-void m18x_setup_cmmu_config __P((void));
-void m18x_setup_board_config __P((void));
-#if defined(CMMU_DEBUG)
-void m18x_show_apr __P((unsigned value));
-void m18x_show_sctr __P((unsigned value));
-#endif
-unsigned m18x_cmmu_get __P((int mmu, int reg));
-void m18x_cmmu_set __P((int reg, unsigned val, int flags, int num,
- int mode, int access, vm_offset_t addr));
-void m18x_cmmu_sync_cache __P((vm_offset_t physaddr, int size));
-void m18x_cmmu_sync_inval_cache __P((vm_offset_t physaddr, int size));
-void m18x_cmmu_inval_cache __P((vm_offset_t physaddr, int size));
-int m18x_cmmu_alive __P((int));
-void m18x_cmmu_store __P((int, int, unsigned));
-
-#ifdef CMMU_DEBUG
void
-m18x_show_apr(value)
+m8820x_show_apr(value)
unsigned value;
{
union apr_template apr_template;
@@ -207,28 +236,6 @@ m18x_show_apr(value)
printf("\n");
}
-void
-m18x_show_sctr(value)
- unsigned value;
-{
- union {
- unsigned bits;
- struct {
- unsigned :16,
- pe: 1,
- se: 1,
- pr: 1,
- :13;
- } fields;
- } sctr;
- sctr.bits = value;
- printf("%spe, %sse %spr]\n",
- sctr.fields.pe ? "" : "!",
- sctr.fields.se ? "" : "!",
- sctr.fields.pr ? "" : "!");
-}
-#endif
-
/*----------------------------------------------------------------
* The cmmu.c module was initially designed for the Omron Luna 88K
* layout consisting of 4 CPUs with 2 CMMUs each, one for data
@@ -285,7 +292,8 @@ struct board_config {
int supported;
int ncpus;
int ncmmus;
-} bd_config[] = {
+} bd_config[] =
+{
/* sup, CPU MMU */
{ 1, 4, 8}, /* 4P128 - 4P512 */
{ 1, 2, 8}, /* 2P128 - 2P512 */
@@ -309,7 +317,8 @@ struct board_config {
* Structure for accessing MMUS properly.
*/
-struct cmmu cmmu[MAX_CMMUS] = {
+struct m8820x_cmmu m8820x_cmmu[MAX_CMMUS] =
+{
/* addr cpu mode access
alive addr mask */
{(void *)VME_CMMU_I0, -1, INST_CMMU, CMMU_ACS_BOTH,
@@ -331,11 +340,11 @@ struct cmmu cmmu[MAX_CMMUS] = {
};
struct cpu_cmmu {
- struct cmmu *pair[2];
+ struct m8820x_cmmu *pair[2];
} cpu_cmmu[MAX_CPUS];
void
-m18x_setup_board_config()
+m8820x_setup_board_config()
{
volatile unsigned long *whoami;
@@ -343,47 +352,49 @@ m18x_setup_board_config()
switch (cputyp) {
#ifdef MVME187
case CPU_187:
- vme188_config = 10; /* There is no WHOAMI reg on MVME1x7 - fake it... */
- cmmu[0].cmmu_regs = (void *)SBC_CMMU_I;
- cmmu[0].cmmu_cpu = 0;
- cmmu[1].cmmu_regs = (void *)SBC_CMMU_D;
- cmmu[1].cmmu_cpu = 0;
- cmmu[2].cmmu_regs = (void *)NULL;
- cmmu[3].cmmu_regs = (void *)NULL;
- cmmu[4].cmmu_regs = (void *)NULL;
- cmmu[5].cmmu_regs = (void *)NULL;
- cmmu[6].cmmu_regs = (void *)NULL;
- cmmu[7].cmmu_regs = (void *)NULL;
+ vme188_config = 10; /* There is no WHOAMI reg on MVME187 - fake it... */
+ m8820x_cmmu[0].cmmu_regs = (void *)SBC_CMMU_I;
+ m8820x_cmmu[0].cmmu_cpu = 0;
+ m8820x_cmmu[1].cmmu_regs = (void *)SBC_CMMU_D;
+ m8820x_cmmu[1].cmmu_cpu = 0;
+ m8820x_cmmu[2].cmmu_regs = (void *)NULL;
+ m8820x_cmmu[3].cmmu_regs = (void *)NULL;
+ m8820x_cmmu[4].cmmu_regs = (void *)NULL;
+ m8820x_cmmu[5].cmmu_regs = (void *)NULL;
+ m8820x_cmmu[6].cmmu_regs = (void *)NULL;
+ m8820x_cmmu[7].cmmu_regs = (void *)NULL;
max_cpus = 1;
max_cmmus = 2;
break;
-#endif /* defined(MVME187) */
+#endif /* MVME187 */
#ifdef MVME188
case CPU_188:
whoami = (volatile unsigned long *)MVME188_WHOAMI;
vme188_config = (*whoami & 0xf0) >> 4;
- dprintf(DB_CMMU,("m18x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x vme188_config = %d\n",
+ dprintf(DB_CMMU,("m8820x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x vme188_config = %d\n",
whoami, *whoami, vme188_config));
max_cpus = bd_config[vme188_config].ncpus;
max_cmmus = bd_config[vme188_config].ncmmus;
break;
#endif /* MVME188 */
+ default:
+ panic("m8820x_setup_board_config: Unknown CPU type.");
}
cpu_cmmu_ratio = max_cmmus / max_cpus;
switch (bd_config[vme188_config].supported) {
case 0:
printf("MVME%x board configuration #%X: %d CPUs %d CMMUs\n", cputyp,
vme188_config, max_cpus, max_cmmus);
- panic("This configuration is not supported - go and get another OS.");
+ panic("This configuration is not supported - go and get another OS.\n");
/* NOTREACHED */
break;
case 1:
printf("MVME%x board configuration #%X: %d CPUs %d CMMUs\n", cputyp,
vme188_config, max_cpus, max_cmmus);
- m18x_setup_cmmu_config();
+ m8820x_setup_cmmu_config();
break;
default:
- panic("UNKNOWN MVME%x board configuration: WHOAMI = 0x%02x", cputyp, *whoami);
+ panic("UNKNOWN MVME%x board configuration: WHOAMI = 0x%02x\n", cputyp, *whoami);
/* NOTREACHED */
break;
}
@@ -395,7 +406,7 @@ m18x_setup_board_config()
* motorola/m88k/m88100/cmmu.c module.
*/
void
-m18x_setup_cmmu_config()
+m8820x_setup_cmmu_config()
{
register int num, cmmu_num;
#ifdef MVME188
@@ -404,25 +415,25 @@ m18x_setup_cmmu_config()
volatile unsigned long *pcnfb;
#endif
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: initializing with %d CPU(s) and %d CMMU(s)\n",
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: initializing with %d CPU(s) and %d CMMU(s)\n",
max_cpus, max_cmmus));
/*
* Probe for available MMUs
*/
for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++)
- if (!badwordaddr((vm_offset_t)cmmu[cmmu_num].cmmu_regs)) {
+ if (!badwordaddr((vm_offset_t)m8820x_cmmu[cmmu_num].cmmu_regs)) {
union cpupid id;
- id.cpupid = cmmu[cmmu_num].cmmu_regs->idr;
+ id.cpupid = m8820x_cmmu[cmmu_num].cmmu_regs->idr;
if (id.m88200.type != M88200 && id.m88200.type != M88204) {
printf("WARNING: non M8820x circuit found at CMMU address 0x%08x\n",
- cmmu[cmmu_num].cmmu_regs);
+ m8820x_cmmu[cmmu_num].cmmu_regs);
continue;
}
- cmmu[cmmu_num].cmmu_alive = CMMU_ALIVE;
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d found at 0x%08x\n",
- cmmu_num, cmmu[cmmu_num].cmmu_regs));
+ m8820x_cmmu[cmmu_num].cmmu_alive = CMMU_ALIVE;
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CMMU %d found at 0x%08x\n",
+ cmmu_num, m8820x_cmmu[cmmu_num].cmmu_regs));
}
/*
@@ -436,13 +447,13 @@ m18x_setup_cmmu_config()
for (i = 0; i < cpu_cmmu_ratio; i++) {
dprintf(DB_CMMU,("cmmu_init: testing CMMU %d for CPU %d\n",
num*cpu_cmmu_ratio+i, num));
- if (!m18x_cmmu_alive(num*cpu_cmmu_ratio + i)) {
+ if (!m8820x_cmmu_alive(num*cpu_cmmu_ratio + i)) {
printf("CMMU %d attached to CPU %d is not working\n");
- panic("m18x_setup_cmmu_config");
+ panic("m8820x_setup_cmmu_config");
}
}
cpu_sets[num] = 1; /* This cpu installed... */
- id.cpupid = cmmu[num*cpu_cmmu_ratio].cmmu_regs->idr;
+ id.cpupid = m8820x_cmmu[num*cpu_cmmu_ratio].cmmu_regs->idr;
if (id.m88200.type == M88204)
printf("CPU%d is attached with %d MC88204 CMMUs\n",
@@ -455,7 +466,7 @@ m18x_setup_cmmu_config()
for (num = 0; num < max_cpus; num++) {
cpu_cmmu_strategy[num].inst &= CMMU_SPLIT_MASK;
cpu_cmmu_strategy[num].data &= CMMU_SPLIT_MASK;
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n",
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n",
num, cpu_cmmu_strategy[num].inst, cpu_cmmu_strategy[num].data));
}
@@ -466,7 +477,7 @@ m18x_setup_cmmu_config()
case CONFIG_0:
case CONFIG_5:
case CONFIG_A:
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: resetting strategies\n"));
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: resetting strategies\n"));
for (num = 0; num < max_cpus; num++)
cpu_cmmu_strategy[num].inst = cpu_cmmu_strategy[num].data =
CMMU_SPLIT_ADDRESS;
@@ -482,7 +493,7 @@ m18x_setup_cmmu_config()
val2 = (cpu_cmmu_strategy[1].inst << 2) | cpu_cmmu_strategy[1].data;
*pcnfa = val1;
*pcnfb = val2;
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
break;
case CONFIG_2:
pcnfa = (volatile unsigned long *)MVME188_PCNFA;
@@ -491,46 +502,46 @@ m18x_setup_cmmu_config()
val2 = (cpu_cmmu_strategy[0].data << 2) | cpu_cmmu_strategy[0].data;
*pcnfa = val1;
*pcnfb = val2;
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
break;
case CONFIG_6:
pcnfa = (volatile unsigned long *)MVME188_PCNFA;
val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data;
*pcnfa = val1;
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1));
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1));
break;
#endif /* MVME188 */
default:
- panic("m18x_setup_cmmu_config");
+ panic("m8820x_setup_cmmu_config");
break;
}
#ifdef MVME188
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb));
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb));
#endif /* MVME188 */
/*
* Calculate the CMMU<->CPU connections
*/
for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
- cmmu[cmmu_num].cmmu_cpu =
+ m8820x_cmmu[cmmu_num].cmmu_cpu =
(int) (((float) cmmu_num) * ((float) max_cpus) / ((float) max_cmmus));
- dprintf(DB_CMMU,("m18x_setup_cmmu_config: CMMU %d connected with CPU %d\n",
- cmmu_num, cmmu[cmmu_num].cmmu_cpu));
+ dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CMMU %d connected with CPU %d\n",
+ cmmu_num, m8820x_cmmu[cmmu_num].cmmu_cpu));
}
/*
- * Now set cmmu[].cmmu_access and addr
+ * Now set m8820x_cmmu[].cmmu_access and addr
*/
for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
/*
* We don't set up anything for the hardwired configurations.
*/
if (cpu_cmmu_ratio == 2) {
- cmmu[cmmu_num].cmmu_addr =
- cmmu[cmmu_num].cmmu_addr_mask = 0;
- cmmu[cmmu_num].cmmu_addr_match = 1;
- cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH;
+ m8820x_cmmu[cmmu_num].cmmu_addr =
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0;
+ m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
+ m8820x_cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH;
continue;
}
@@ -538,33 +549,33 @@ m18x_setup_cmmu_config()
* First we set the address/mask pairs for the exact address
* matches.
*/
- switch ((cmmu[cmmu_num].which == INST_CMMU) ?
- cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst :
- cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) {
+ switch ((m8820x_cmmu[cmmu_num].which == INST_CMMU) ?
+ cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
+ cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) {
case CMMU_SPLIT_ADDRESS:
- cmmu[cmmu_num].cmmu_addr = ((cmmu_num & 0x2) ^ 0x2) << 11;
- cmmu[cmmu_num].cmmu_addr_mask = CMMU_A12_MASK;
- cmmu[cmmu_num].cmmu_addr_match = 1;
+ m8820x_cmmu[cmmu_num].cmmu_addr = ((cmmu_num & 0x2) ^ 0x2) << 11;
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_A12_MASK;
+ m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
break;
case CMMU_SPLIT_SPV:
- cmmu[cmmu_num].cmmu_addr =
- cmmu[cmmu_num].cmmu_addr_mask = 0;
- cmmu[cmmu_num].cmmu_addr_match = 1;
+ m8820x_cmmu[cmmu_num].cmmu_addr =
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0;
+ m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
break;
case CMMU_SPLIT_SRAM_ALL:
- cmmu[cmmu_num].cmmu_addr = CMMU_SRAM;
- cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK;
- cmmu[cmmu_num].cmmu_addr_match = (cmmu_num & 0x2) ? 1 : 0;
+ m8820x_cmmu[cmmu_num].cmmu_addr = CMMU_SRAM;
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK;
+ m8820x_cmmu[cmmu_num].cmmu_addr_match = (cmmu_num & 0x2) ? 1 : 0;
break;
case CMMU_SPLIT_SRAM_SPV:
if (cmmu_num & 0x2) {
- cmmu[cmmu_num].cmmu_addr = CMMU_SRAM;
- cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK;
+ m8820x_cmmu[cmmu_num].cmmu_addr = CMMU_SRAM;
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK;
} else {
- cmmu[cmmu_num].cmmu_addr =
- cmmu[cmmu_num].cmmu_addr_mask = 0;
+ m8820x_cmmu[cmmu_num].cmmu_addr =
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0;
}
- cmmu[cmmu_num].cmmu_addr_match = 1;
+ m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
break;
}
@@ -575,26 +586,26 @@ m18x_setup_cmmu_config()
* NOT TESTED!!! - em
*/
if (cpu_cmmu_ratio > 4) {
- cmmu[cmmu_num].cmmu_addr |= ((cmmu_num & 0x4) ^ 0x4) << 12;
- cmmu[cmmu_num].cmmu_addr_mask |= CMMU_A14_MASK;
+ m8820x_cmmu[cmmu_num].cmmu_addr |= ((cmmu_num & 0x4) ^ 0x4) << 12;
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask |= CMMU_A14_MASK;
}
/*
* Next we cope with the various access modes.
*/
- switch ((cmmu[cmmu_num].which == INST_CMMU) ?
- cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst :
- cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data) {
+ switch ((m8820x_cmmu[cmmu_num].which == INST_CMMU) ?
+ cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
+ cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) {
case CMMU_SPLIT_SPV:
- cmmu[cmmu_num].cmmu_access =
+ m8820x_cmmu[cmmu_num].cmmu_access =
(cmmu_num & 0x2 ) ? CMMU_ACS_USER : CMMU_ACS_SUPER;
break;
case CMMU_SPLIT_SRAM_SPV:
- cmmu[cmmu_num].cmmu_access =
+ m8820x_cmmu[cmmu_num].cmmu_access =
(cmmu_num & 0x2 ) ? CMMU_ACS_SUPER : CMMU_ACS_BOTH;
break;
default:
- cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH;
+ m8820x_cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH;
break;
}
}
@@ -611,7 +622,7 @@ static char *cmmu_strat_string[] = {
#endif
void
-m18x_cmmu_dump_config()
+m8820x_cmmu_dump_config()
{
#ifdef MVME188
volatile unsigned long *pcnfa;
@@ -625,60 +636,62 @@ m18x_cmmu_dump_config()
#ifdef MVME187
case CPU_187:
DEBUG_MSG("VME1x7 split mode\n\n");
-#endif /* defined(MVME187) */
+#endif /* MVME187 */
#ifdef MVME188
case CPU_188:
+ DEBUG_MSG("VME188 address decoder: PCNFA = 0x%1x, PCNFB = 0x%1x\n\n", *pcnfa & 0xf, *pcnfb & 0xf);
pcnfa = (volatile unsigned long *)MVME188_PCNFA;
pcnfb = (volatile unsigned long *)MVME188_PCNFB;
- DEBUG_MSG("VME188 address decoder: PCNFA = 0x%1x, PCNFB = 0x%1x\n\n", *pcnfa & 0xf, *pcnfb & 0xf);
for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
DEBUG_MSG("CMMU #%d: %s CMMU for CPU %d:\n Strategy: %s\n %s access addr 0x%08x mask 0x%08x match %s\n",
cmmu_num,
- (cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data",
- cmmu[cmmu_num].cmmu_cpu,
- cmmu_strat_string[(cmmu[cmmu_num].which == INST_CMMU) ?
- cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].inst :
- cpu_cmmu_strategy[cmmu[cmmu_num].cmmu_cpu].data],
- (cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ? "User and spv" :
- ((cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User " :
+ (m8820x_cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data",
+ m8820x_cmmu[cmmu_num].cmmu_cpu,
+ cmmu_strat_string[(m8820x_cmmu[cmmu_num].which == INST_CMMU) ?
+ cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
+ cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data],
+ (m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ? "User and spv" :
+ ((m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User " :
"Supervisor "),
- cmmu[cmmu_num].cmmu_addr,
- cmmu[cmmu_num].cmmu_addr_mask,
- cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE");
+ m8820x_cmmu[cmmu_num].cmmu_addr,
+ m8820x_cmmu[cmmu_num].cmmu_addr_mask,
+ m8820x_cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE");
}
#endif /* MVME188 */
+ default:
+ DEBUG_MSG("Unknown CPU\n\n");
}
}
/* To be implemented as a macro for speedup - XXX-em */
-void
-m18x_cmmu_store(mmu, reg, val)
+STATIC void
+m8820x_cmmu_store(mmu, reg, val)
int mmu, reg;
unsigned val;
{
- *(volatile unsigned *)(reg + (char *)(cmmu[mmu].cmmu_regs)) = val;
+ *(volatile unsigned *)(reg + (char*)(m8820x_cmmu[mmu].cmmu_regs)) = val;
}
-int
-m18x_cmmu_alive(mmu)
+STATIC int
+m8820x_cmmu_alive(mmu)
int mmu;
{
- return (cmmu[mmu].cmmu_alive == CMMU_ALIVE);
+ return (m8820x_cmmu[mmu].cmmu_alive == CMMU_ALIVE);
}
-unsigned
-m18x_cmmu_get(mmu, reg)
+STATIC unsigned
+m8820x_cmmu_get(mmu, reg)
int mmu, reg;
{
- return *(volatile unsigned *)(reg + (char*)(cmmu[mmu].cmmu_regs));
+ return *(volatile unsigned *)(reg + (char*)(m8820x_cmmu[mmu].cmmu_regs));
}
/*
* This function is called by the MMU module and pokes values
* into the CMMU's registers.
*/
-void
-m18x_cmmu_set(reg, val, flags, num, mode, access, addr)
+STATIC void
+m8820x_cmmu_set(reg, val, flags, num, mode, access, addr)
int reg;
unsigned val;
int flags, num, mode, access;
@@ -692,7 +705,7 @@ m18x_cmmu_set(reg, val, flags, num, mode, access, addr)
* Simply store the value away.
*/
/* assert(num < max_cmmus); */
- m18x_cmmu_store(num, reg, val);
+ m8820x_cmmu_store(num, reg, val);
return;
}
@@ -702,19 +715,19 @@ m18x_cmmu_set(reg, val, flags, num, mode, access, addr)
*/
for (mmu = num*cpu_cmmu_ratio; mmu < (num+1)*cpu_cmmu_ratio; mmu++) {
if (((flags & MODE_VAL)) &&
- (cmmu[mmu].which != mode))
+ (m8820x_cmmu[mmu].which != mode))
continue;
if (((flags & ACCESS_VAL)) &&
- (cmmu[mmu].cmmu_access != access) &&
- (cmmu[mmu].cmmu_access != CMMU_ACS_BOTH))
+ (m8820x_cmmu[mmu].cmmu_access != access) &&
+ (m8820x_cmmu[mmu].cmmu_access != CMMU_ACS_BOTH))
continue;
if (flags & ADDR_VAL) {
- if (((addr & cmmu[mmu].cmmu_addr_mask) == cmmu[mmu].cmmu_addr)
- != cmmu[mmu].cmmu_addr_match) {
+ if (((addr & m8820x_cmmu[mmu].cmmu_addr_mask) == m8820x_cmmu[mmu].cmmu_addr)
+ != m8820x_cmmu[mmu].cmmu_addr_match) {
continue;
}
}
- m18x_cmmu_store(mmu, reg, val);
+ m8820x_cmmu_store(mmu, reg, val);
}
}
@@ -723,17 +736,17 @@ m18x_cmmu_set(reg, val, flags, num, mode, access, addr)
* Used by DDB for cache probe functions
*/
unsigned
-m18x_cmmu_get_by_mode(cpu, mode)
+m8820x_cmmu_get_by_mode(cpu, mode)
int cpu, mode;
{
register int mmu;
for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++)
- if (cmmu[mmu].which == mode)
+ if (m8820x_cmmu[mmu].which == mode)
return mmu;
printf("can't figure out first %s CMMU for CPU %d\n",
(mode == DATA_CMMU) ? "data" : "instruction", cpu);
- panic("m18x_cmmu_get_by_mode");
+ panic("m8820x_cmmu_get_by_mode");
/* NOTREACHED */
return(0);
}
@@ -756,7 +769,7 @@ static char *mmutypes[8] = {
* by the master, before the slaves are started.
*/
void
-m18x_cpu_configuration_print(master)
+m8820x_cpu_configuration_print(master)
int master;
{
int pid = read_processor_identification_register();
@@ -783,14 +796,14 @@ m18x_cpu_configuration_print(master)
#endif
for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++) {
- int idr = m18x_cmmu_get(mmu, CMMU_IDR);
+ int idr = m8820x_cmmu_get(mmu, CMMU_IDR);
int mmuid = (0xe00000 & idr)>>21;
printf(" %s %s Cache: ",
- (cmmu[mmu].cmmu_access == CMMU_ACS_BOTH) ? "Spv and User" :
- ((cmmu[mmu].cmmu_access == CMMU_ACS_USER) ? "User " :
+ (m8820x_cmmu[mmu].cmmu_access == CMMU_ACS_BOTH) ? "Spv and User" :
+ ((m8820x_cmmu[mmu].cmmu_access == CMMU_ACS_USER) ? "User " :
"Supervisor "),
- (cmmu[mmu].which == INST_CMMU) ? "Instruction" :
+ (m8820x_cmmu[mmu].which == INST_CMMU) ? "Instruction" :
"Data ");
if (mmutypes[mmuid][0] == 'U')
printf("Type 0x%x ", mmuid);
@@ -807,7 +820,7 @@ m18x_cpu_configuration_print(master)
* CMMU initialization routine
*/
void
-m18x_cmmu_init()
+m8820x_cmmu_init()
{
unsigned tmp, cmmu_num;
union cpupid id;
@@ -818,33 +831,33 @@ m18x_cmmu_init()
}
for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++){
- if (m18x_cmmu_alive(cmmu_num)) {
- id.cpupid = cmmu[cmmu_num].cmmu_regs->idr;
+ if (m8820x_cmmu_alive(cmmu_num)) {
+ id.cpupid = m8820x_cmmu[cmmu_num].cmmu_regs->idr;
- cpu_cmmu[cmmu[cmmu_num].cmmu_cpu].pair[cmmu[cmmu_num].which] =
- &cmmu[cmmu_num];
+ cpu_cmmu[m8820x_cmmu[cmmu_num].cmmu_cpu].pair[m8820x_cmmu[cmmu_num].which] =
+ &m8820x_cmmu[cmmu_num];
/*
* Reset cache data....
* as per M88200 Manual (2nd Ed.) section 3.11.
*/
for (tmp = 0; tmp < 255; tmp++) {
- cmmu[cmmu_num].cmmu_regs->sar = tmp << 4;
- cmmu[cmmu_num].cmmu_regs->cssp = 0x3f0ff000;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp << 4;
+ m8820x_cmmu[cmmu_num].cmmu_regs->cssp = 0x3f0ff000;
}
/* 88204 has additional cache to clear */
if (id.m88200.type == M88204) {
for (tmp = 0; tmp < 255; tmp++) {
- cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
- cmmu[cmmu_num].cmmu_regs->cssp1 = 0x3f0ff000;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
+ m8820x_cmmu[cmmu_num].cmmu_regs->cssp1 = 0x3f0ff000;
}
for (tmp = 0; tmp < 255; tmp++) {
- cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
- cmmu[cmmu_num].cmmu_regs->cssp2 = 0x3f0ff000;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
+ m8820x_cmmu[cmmu_num].cmmu_regs->cssp2 = 0x3f0ff000;
}
for (tmp = 0; tmp < 255; tmp++) {
- cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
- cmmu[cmmu_num].cmmu_regs->cssp3 = 0x3f0ff000;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
+ m8820x_cmmu[cmmu_num].cmmu_regs->cssp3 = 0x3f0ff000;
}
}
@@ -856,7 +869,7 @@ m18x_cmmu_init()
! CMMU_SCTR_PE | /* not parity enable */
! CMMU_SCTR_SE | /* not snoop enable */
! CMMU_SCTR_PR ; /* not priority arbitration */
- cmmu[cmmu_num].cmmu_regs->sctr = tmp;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp;
tmp =
(0x00000 << 12) | /* segment table base address */
@@ -864,31 +877,31 @@ m18x_cmmu_init()
AREA_D_G | /* global */
AREA_D_CI | /* cache inhibit */
! AREA_D_TE ; /* not translation enable */
- cmmu[cmmu_num].cmmu_regs->sapr =
- cmmu[cmmu_num].cmmu_regs->uapr = tmp;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sapr =
+ m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp;
#ifdef SHADOW_BATC
- cmmu[cmmu_num].batc[0] =
- cmmu[cmmu_num].batc[1] =
- cmmu[cmmu_num].batc[2] =
- cmmu[cmmu_num].batc[3] =
- cmmu[cmmu_num].batc[4] =
- cmmu[cmmu_num].batc[5] =
- cmmu[cmmu_num].batc[6] =
- cmmu[cmmu_num].batc[7] = 0;
+ m8820x_cmmu[cmmu_num].batc[0] =
+ m8820x_cmmu[cmmu_num].batc[1] =
+ m8820x_cmmu[cmmu_num].batc[2] =
+ m8820x_cmmu[cmmu_num].batc[3] =
+ m8820x_cmmu[cmmu_num].batc[4] =
+ m8820x_cmmu[cmmu_num].batc[5] =
+ m8820x_cmmu[cmmu_num].batc[6] =
+ m8820x_cmmu[cmmu_num].batc[7] = 0;
#endif
- cmmu[cmmu_num].cmmu_regs->bwp[0] =
- cmmu[cmmu_num].cmmu_regs->bwp[1] =
- cmmu[cmmu_num].cmmu_regs->bwp[2] =
- cmmu[cmmu_num].cmmu_regs->bwp[3] =
- cmmu[cmmu_num].cmmu_regs->bwp[4] =
- cmmu[cmmu_num].cmmu_regs->bwp[5] =
- cmmu[cmmu_num].cmmu_regs->bwp[6] =
- cmmu[cmmu_num].cmmu_regs->bwp[7] = 0;
- cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_CACHE_INV_ALL;
- cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_SUPER_ALL;
- cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_USER_ALL;
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[0] =
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[1] =
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[2] =
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[3] =
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[4] =
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[5] =
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[6] =
+ m8820x_cmmu[cmmu_num].cmmu_regs->bwp[7] = 0;
+ m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_CACHE_INV_ALL;
+ m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_SUPER_ALL;
+ m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_USER_ALL;
}
}
/*
@@ -913,12 +926,12 @@ m18x_cmmu_init()
! CMMU_SCTR_PE | /* not parity enable */
! CMMU_SCTR_PR ; /* not priority arbitration */
}
- m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0);
+ m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0);
+ m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL,
cpu, DATA_CMMU, CMMU_ACS_SUPER, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL,
cpu, INST_CMMU, CMMU_ACS_SUPER, 0);
}
@@ -943,13 +956,13 @@ m18x_cmmu_init()
/*
REGS(cpu, INST_CMMU).sapr = tmp;
*/
- m18x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL,
cpu, INST_CMMU, 0, 0);
/*
REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL;
*/
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL,
cpu, DATA_CMMU, CMMU_ACS_SUPER, 0);
}
}
@@ -958,11 +971,12 @@ m18x_cmmu_init()
* Just before poweroff or reset....
*/
void
-m18x_cmmu_shutdown_now()
+m8820x_cmmu_shutdown_now()
{
unsigned tmp;
unsigned cmmu_num;
+ CMMU_LOCK;
/*
* Now set some state as we like...
*/
@@ -978,7 +992,7 @@ m18x_cmmu_shutdown_now()
! CMMU_SCTR_PR ; /* priority arbitration */
}
- cmmu[cmmu_num].cmmu_regs->sctr = tmp;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp;
tmp =
(0x00000 << 12) | /* segment table base address */
@@ -987,9 +1001,10 @@ m18x_cmmu_shutdown_now()
AREA_D_CI | /* cache inhibit */
! AREA_D_TE ; /* translation disable */
- cmmu[cmmu_num].cmmu_regs->sapr = tmp;
- cmmu[cmmu_num].cmmu_regs->uapr = tmp;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sapr = tmp;
+ m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp;
}
+ CMMU_UNLOCK;
}
#define PARITY_ENABLE
@@ -997,23 +1012,25 @@ m18x_cmmu_shutdown_now()
* enable parity
*/
void
-m18x_cmmu_parity_enable()
+m8820x_cmmu_parity_enable()
{
#ifdef PARITY_ENABLE
register int cmmu_num;
+ CMMU_LOCK;
for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
- if (m18x_cmmu_alive(cmmu_num)) {
+ if (m8820x_cmmu_alive(cmmu_num)) {
register unsigned val1 =
- m18x_cmmu_get(cmmu_num, CMMU_SCTR);
+ m8820x_cmmu_get(cmmu_num, CMMU_SCTR);
/*
- cmmu[cmmu_num].cmmu_regs->sctr |= CMMU_SCTR_PE;
+ m8820x_cmmu[cmmu_num].cmmu_regs->sctr |= CMMU_SCTR_PE;
*/
- m18x_cmmu_set(CMMU_SCTR, val1 | CMMU_SCTR_PE,
+ m8820x_cmmu_set(CMMU_SCTR, val1 | CMMU_SCTR_PE,
NUM_CMMU, cmmu_num, 0, 0, 0);
}
}
+ CMMU_UNLOCK;
#endif /* PARITY_ENABLE */
}
@@ -1025,18 +1042,19 @@ m18x_cmmu_parity_enable()
#define ILLADDRESS U(0x0F000000) /* any faulty address */
unsigned
-m18x_cmmu_cpu_number()
+m8820x_cmmu_cpu_number()
{
register unsigned cmmu_no;
int i;
-
+
+ CMMU_LOCK;
for (i=0; i < 10; i++) {
/* clear CMMU p-bus status registers */
for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) {
- if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE &&
- cmmu[cmmu_no].which == DATA_CMMU)
- cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0;
+ if (m8820x_cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE &&
+ m8820x_cmmu[cmmu_no].which == DATA_CMMU)
+ m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0;
}
/* access faulting address */
@@ -1044,18 +1062,19 @@ m18x_cmmu_cpu_number()
/* check which CMMU reporting the fault */
for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) {
- if (cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE &&
- cmmu[cmmu_no].which == DATA_CMMU &&
- cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) {
- if (cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) {
- cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; /* to be clean */
- cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED;
- return cmmu[cmmu_no].cmmu_cpu;
+ if (m8820x_cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE &&
+ m8820x_cmmu[cmmu_no].which == DATA_CMMU &&
+ m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) {
+ if (m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) {
+ m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0; /* to be clean */
+ m8820x_cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED;
+ return m8820x_cmmu[cmmu_no].cmmu_cpu;
}
}
}
}
- panic("m18x_cmmu_cpu_number: could not determine my cpu number");
+ panic("m8820x_cmmu_cpu_number: could not determine my cpu number");
+ CMMU_UNLOCK;
return 0; /* to make compiler happy */
}
@@ -1063,27 +1082,9 @@ m18x_cmmu_cpu_number()
* Functions that actually modify CMMU registers.
*/
-void
-m18x_cmmu_remote_set(cpu, r, data, x)
- unsigned cpu, r, data, x;
-{
- *(volatile unsigned *)(r + (char*)&REGS(cpu,data)) = x;
-}
-
-/*
- * cmmu_cpu_lock should be held when called if read
- * the CMMU_SCR or CMMU_SAR.
- */
-unsigned
-m18x_cmmu_remote_get(cpu, r, data)
- unsigned cpu, r, data;
-{
- return (*(volatile unsigned *)(r + (char*)&REGS(cpu,data)));
-}
-
/* Needs no locking - read only registers */
unsigned
-m18x_cmmu_get_idr(data)
+m8820x_cmmu_get_idr(data)
unsigned data;
{
int cpu;
@@ -1092,71 +1093,65 @@ m18x_cmmu_get_idr(data)
}
void
-m18x_cmmu_set_sapr(ap)
+m8820x_cmmu_set_sapr(ap)
unsigned ap;
{
int cpu;
cpu = cpu_number();
+ CMMU_LOCK;
if (cache_policy & CACHE_INH)
ap |= AREA_D_CI;
- /*
- REGS(cpu, INST_CMMU).sapr = ap;
- REGS(cpu, DATA_CMMU).sapr = ap;
- */
- m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL,
cpu, 0, CMMU_ACS_SUPER, 0);
+ CMMU_UNLOCK;
}
void
-m18x_cmmu_remote_set_sapr(cpu, ap)
+m8820x_cmmu_remote_set_sapr(cpu, ap)
unsigned cpu, ap;
{
+ CMMU_LOCK;
if (cache_policy & CACHE_INH)
ap |= AREA_D_CI;
-
- /*
- REGS(cpu, INST_CMMU).sapr = ap;
- REGS(cpu, DATA_CMMU).sapr = ap;
- */
- m18x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL,
cpu, 0, CMMU_ACS_SUPER, 0);
+ CMMU_UNLOCK;
}
void
-m18x_cmmu_set_uapr(ap)
+m8820x_cmmu_set_uapr(ap)
unsigned ap;
{
+ register int s = splhigh();
int cpu;
+
cpu = cpu_number();
-
- /* this functionality also mimiced in m18x_cmmu_pmap_activate() */
- /*
- REGS(cpu, INST_CMMU).uapr = ap;
- REGS(cpu, DATA_CMMU).uapr = ap;
- */
- m18x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL,
+
+ CMMU_LOCK;
+ /* this functionality also mimiced in m8820x_cmmu_pmap_activate() */
+ m8820x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL,
cpu, 0, CMMU_ACS_USER, 0);
+ CMMU_UNLOCK;
+ splx(s);
}
/*
* Set batc entry number entry_no to value in
* the data or instruction cache depending on data.
*
- * Except for the cmmu_init, this function, m18x_cmmu_set_pair_batc_entry,
- * and m18x_cmmu_pmap_activate are the only functions which may set the
+ * Except for the cmmu_init, this function, m8820x_cmmu_set_pair_batc_entry,
+ * and m8820x_cmmu_pmap_activate are the only functions which may set the
* batc values.
*/
void
-m18x_cmmu_set_batc_entry(cpu, entry_no, data, value)
+m8820x_cmmu_set_batc_entry(cpu, entry_no, data, value)
unsigned cpu, entry_no;
unsigned data; /* 1 = data, 0 = instruction */
unsigned value; /* the value to stuff into the batc */
{
- /*
- REGS(cpu,data).bwp[entry_no] = value;
- */
- m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
+ CMMU_LOCK;
+ m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
cpu, data, CMMU_ACS_USER, 0);
#ifdef SHADOW_BATC
CMMU(cpu,data)->batc[entry_no] = value;
@@ -1165,6 +1160,7 @@ m18x_cmmu_set_batc_entry(cpu, entry_no, data, value)
REGS(cpu,data).scr = CMMU_FLUSH_SUPER_ALL;
REGS(cpu,data).scr = CMMU_FLUSH_USER_ALL;
#endif
+ CMMU_UNLOCK;
}
/*
@@ -1172,23 +1168,17 @@ m18x_cmmu_set_batc_entry(cpu, entry_no, data, value)
* the data and instruction cache for the named CPU.
*/
void
-m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value)
+m8820x_cmmu_set_pair_batc_entry(cpu, entry_no, value)
unsigned cpu, entry_no;
unsigned value; /* the value to stuff into the batc */
{
-
- /*
- REGS(cpu,DATA_CMMU).bwp[entry_no] = value;
- */
- m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
+ CMMU_LOCK;
+ m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
cpu, DATA_CMMU, CMMU_ACS_USER, 0);
#ifdef SHADOW_BATC
CMMU(cpu,DATA_CMMU)->batc[entry_no] = value;
#endif
- /*
- REGS(cpu,INST_CMMU).bwp[entry_no] = value;
- */
- m18x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
cpu, INST_CMMU, CMMU_ACS_USER, 0);
#ifdef SHADOW_BATC
CMMU(cpu,INST_CMMU)->batc[entry_no] = value;
@@ -1200,6 +1190,7 @@ m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value)
REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_SUPER_ALL;
REGS(cpu,DATA_CMMU).scr = CMMU_FLUSH_USER_ALL;
#endif
+ CMMU_UNLOCK;
}
/*
@@ -1208,46 +1199,31 @@ m18x_cmmu_set_pair_batc_entry(cpu, entry_no, value)
/*
* flush any tlb
- * Some functionality mimiced in m18x_cmmu_pmap_activate.
+ * Some functionality mimiced in m8820x_cmmu_pmap_activate.
*/
void
-m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size)
+m8820x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size)
unsigned cpu, kernel;
vm_offset_t vaddr;
int size;
{
register int s = splhigh();
+ CMMU_LOCK;
if (cpu > max_cpus) {
cpu = cpu_number();
}
if ((unsigned)size > PAGE_SIZE) {
- /*
- REGS(cpu, INST_CMMU).scr =
- REGS(cpu, DATA_CMMU).scr =
- kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL;
- */
-
- m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL, ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL, ACCESS_VAL,
cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, 0);
} else { /* a page or smaller */
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)vaddr;
- REGS(cpu, DATA_CMMU).sar = (unsigned)vaddr;
- */
- m18x_cmmu_set(CMMU_SAR, vaddr, ADDR_VAL|ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SAR, vaddr, ADDR_VAL|ACCESS_VAL,
cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr);
-
- /*
- REGS(cpu, INST_CMMU).scr =
- REGS(cpu, DATA_CMMU).scr =
- kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE;
- */
- m18x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE, ADDR_VAL|ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE, ADDR_VAL|ACCESS_VAL,
cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr);
}
-
+ CMMU_UNLOCK;
splx(s);
}
@@ -1255,14 +1231,14 @@ m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size)
* flush my personal tlb
*/
void
-m18x_cmmu_flush_tlb(kernel, vaddr, size)
+m8820x_cmmu_flush_tlb(kernel, vaddr, size)
unsigned kernel;
vm_offset_t vaddr;
int size;
{
int cpu;
cpu = cpu_number();
- m18x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
+ m8820x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
}
/*
@@ -1271,30 +1247,22 @@ m18x_cmmu_flush_tlb(kernel, vaddr, size)
* Only called from pmap.c's _pmap_activate().
*/
void
-m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
+m8820x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
unsigned cpu, uapr;
batc_template_t i_batc[BATC_MAX];
batc_template_t d_batc[BATC_MAX];
{
int entry_no;
+ CMMU_LOCK;
-
- /* the following is from m18x_cmmu_set_uapr */
- /*
- REGS(cpu, INST_CMMU).uapr = uapr;
- REGS(cpu, DATA_CMMU).uapr = uapr;
- */
- m18x_cmmu_set(CMMU_UAPR, uapr, ACCESS_VAL,
+ /* the following is from m8820x_cmmu_set_uapr */
+ m8820x_cmmu_set(CMMU_UAPR, uapr, ACCESS_VAL,
cpu, 0, CMMU_ACS_USER, 0);
for (entry_no = 0; entry_no < BATC_MAX; entry_no++) {
- /*
- REGS(cpu,INST_CMMU).bwp[entry_no] = i_batc[entry_no].bits;
- REGS(cpu,DATA_CMMU).bwp[entry_no] = d_batc[entry_no].bits;
- */
- m18x_cmmu_set(CMMU_BWP(entry_no), i_batc[entry_no].bits, MODE_VAL|ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_BWP(entry_no), i_batc[entry_no].bits, MODE_VAL|ACCESS_VAL,
cpu, INST_CMMU, CMMU_ACS_USER, 0);
- m18x_cmmu_set(CMMU_BWP(entry_no), d_batc[entry_no].bits, MODE_VAL|ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_BWP(entry_no), d_batc[entry_no].bits, MODE_VAL|ACCESS_VAL,
cpu, DATA_CMMU, CMMU_ACS_USER, 0);
#ifdef SHADOW_BATC
CMMU(cpu,INST_CMMU)->batc[entry_no] = i_batc[entry_no].bits;
@@ -1302,18 +1270,14 @@ m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
#endif
}
-
/*
* Flush the user TLB.
* IF THE KERNEL WILL EVER CARE ABOUT THE BATC ENTRIES,
* THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL.
*/
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_USER_ALL;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_USER_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_USER_ALL, ACCESS_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_USER_ALL, ACCESS_VAL,
cpu, 0, CMMU_ACS_USER, 0);
+ CMMU_UNLOCK;
}
/*
@@ -1334,72 +1298,41 @@ m18x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
* flush both Instruction and Data caches
*/
void
-m18x_cmmu_flush_remote_cache(cpu, physaddr, size)
+m8820x_cmmu_flush_remote_cache(cpu, physaddr, size)
int cpu;
vm_offset_t physaddr;
int size;
{
register int s = splhigh();
-
+ CMMU_LOCK;
#if !defined(BROKEN_MMU_MASK)
if (size < 0 || size > NBSG ) {
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0,
cpu, 0, 0, 0);
} else if (size <= 16) {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL,
cpu, 0, 0, (unsigned)physaddr);
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE , ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE , ADDR_VAL,
cpu, 0, 0, (unsigned)physaddr);
} else if (size <= NBPG) {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL,
cpu, 0, 0, (unsigned)physaddr);
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE , ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE , ADDR_VAL,
cpu, 0, 0, (unsigned)physaddr);
} else {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, 0,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, 0,
cpu, 0, 0, 0);
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, 0,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, 0,
cpu, 0, 0, 0);
}
#else
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0,
cpu, 0, 0, 0);
#endif /* !BROKEN_MMU_MASK */
+ CMMU_UNLOCK;
splx(s);
}
@@ -1407,77 +1340,53 @@ m18x_cmmu_flush_remote_cache(cpu, physaddr, size)
* flush both Instruction and Data caches
*/
void
-m18x_cmmu_flush_cache(physaddr, size)
+m8820x_cmmu_flush_cache(physaddr, size)
vm_offset_t physaddr;
int size;
{
int cpu = cpu_number();
- m18x_cmmu_flush_remote_cache(cpu, physaddr, size);
+ m8820x__cmmu_flush_remote_cache(cpu, physaddr, size);
}
/*
* flush Instruction caches
*/
void
-m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size)
+m8820x_cmmu_flush_remote_inst_cache(cpu, physaddr, size)
int cpu;
vm_offset_t physaddr;
int size;
{
register int s = splhigh();
-
-
+ CMMU_LOCK;
#if !defined(BROKEN_MMU_MASK)
if (size < 0 || size > NBSG ) {
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
} else if (size <= 16) {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
} else if (size <= NBPG) {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
} else {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
cpu, INST_CMMU, 0, 0);
}
#else
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
#endif /* !BROKEN_MMU_MASK */
+ CMMU_UNLOCK;
splx(s);
}
@@ -1485,67 +1394,51 @@ m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size)
* flush Instruction caches
*/
void
-m18x_cmmu_flush_inst_cache(physaddr, size)
+m8820x_cmmu_flush_inst_cache(physaddr, size)
vm_offset_t physaddr;
int size;
{
int cpu;
cpu = cpu_number();
- m18x_cmmu_flush_remote_inst_cache(cpu, physaddr, size);
+ m8820x_cmmu_flush_remote_inst_cache(cpu, physaddr, size);
}
void
-m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size)
+m8820x_cmmu_flush_remote_data_cache(cpu, physaddr, size)
int cpu;
vm_offset_t physaddr;
int size;
{
register int s = splhigh();
+ CMMU_LOCK;
#if !defined(BROKEN_MMU_MASK)
if (size < 0 || size > NBSG ) {
- /*
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
} else if (size <= 16) {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
} else if (size <= NBPG) {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
} else {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
}
#else
- /*
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
#endif /* !BROKEN_MMU_MASK */
+ CMMU_UNLOCK;
splx(s);
}
@@ -1553,274 +1446,184 @@ m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size)
* flush data cache
*/
void
-m18x_cmmu_flush_data_cache(physaddr, size)
+m8820x_cmmu_flush_data_cache(physaddr, size)
vm_offset_t physaddr;
int size;
{
int cpu;
cpu = cpu_number();
- m18x_cmmu_flush_remote_data_cache(cpu, physaddr, size);
+ m8820x_cmmu_flush_remote_data_cache(cpu, physaddr, size);
}
/*
* sync dcache (and icache too)
*/
-void
-m18x_cmmu_sync_cache(physaddr, size)
+static void
+m8820x_cmmu_sync_cache(physaddr, size)
vm_offset_t physaddr;
int size;
{
register int s = splhigh();
int cpu;
+
+ CMMU_LOCK;
cpu = cpu_number();
#if !defined(BROKEN_MMU_MASK)
if (size < 0 || size > NBSG ) {
- /*
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
} else if (size <= 16) {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_LINE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
} else if (size <= NBPG) {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_PAGE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
} else {
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
}
#else
- /*
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CB_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
#endif /* !BROKEN_MMU_MASK */
splx(s);
+ CMMU_UNLOCK;
}
-void
-m18x_cmmu_sync_inval_cache(physaddr, size)
+static void
+m8820x_cmmu_sync_inval_cache(physaddr, size)
vm_offset_t physaddr;
int size;
{
register int s = splhigh();
int cpu;
cpu = cpu_number();
+ CMMU_LOCK;
#if !defined(BROKEN_MMU_MASK)
if (size < 0 || size > NBSG ) {
- /*
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
} else if (size <= 16) {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_LINE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
} else if (size <= NBPG) {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_PAGE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
} else {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
}
#else
- /*
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_CBI_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
#endif /* !BROKEN_MMU_MASK */
+ CMMU_UNLOCK;
splx(s);
}
-void
-m18x_cmmu_inval_cache(physaddr, size)
+static void
+m8820x_cmmu_inval_cache(physaddr, size)
vm_offset_t physaddr;
int size;
{
register int s = splhigh();
int cpu;
cpu = cpu_number();
+ CMMU_LOCK;
#if !defined(BROKEN_MMU_MASK)
if (size < 0 || size > NBSG ) {
- /*
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
} else if (size <= 16) {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_LINE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
} else if (size <= NBPG) {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_PAGE;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
} else {
- /*
- REGS(cpu, DATA_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, INST_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL,
cpu, INST_CMMU, 0, 0);
- /*
- REGS(cpu, INST_CMMU).sar = (unsigned)physaddr;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_SEGMENT;
- */
- m18x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
+ m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
cpu, DATA_CMMU, 0, (unsigned)physaddr);
- m18x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
}
#else
- /*
- REGS(cpu, DATA_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL;
- REGS(cpu, INST_CMMU).scr = CMMU_FLUSH_CACHE_INV_ALL;
- */
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
cpu, DATA_CMMU, 0, 0);
- m18x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
+ m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
cpu, INST_CMMU, 0, 0);
#endif /* !BROKEN_MMU_MASK */
-
+ CMMU_UNLOCK;
splx(s);
}
void
-m18x_dma_cachectl(va, size, op)
+m8820x_dma_cachectl(va, size, op)
vm_offset_t va;
int size, op;
{
@@ -1834,11 +1637,11 @@ m18x_dma_cachectl(va, size, op)
count = size;
if (op == DMA_CACHE_SYNC)
- m18x_cmmu_sync_cache(kvtop(va), count);
+ m8820x_cmmu_sync_cache(kvtop(va), count);
else if (op == DMA_CACHE_SYNC_INVAL)
- m18x_cmmu_sync_inval_cache(kvtop(va), count);
+ m8820x_cmmu_sync_inval_cache(kvtop(va), count);
else
- m18x_cmmu_inval_cache(kvtop(va), count);
+ m8820x_cmmu_inval_cache(kvtop(va), count);
va = (vm_offset_t)((int)va + count);
size -= count;
@@ -1846,11 +1649,11 @@ m18x_dma_cachectl(va, size, op)
#else
if (op == DMA_CACHE_SYNC)
- m18x_cmmu_sync_cache(kvtop(va), size);
+ m8820x_cmmu_sync_cache(kvtop(va), size);
else if (op == DMA_CACHE_SYNC_INVAL)
- m18x_cmmu_sync_inval_cache(kvtop(va), size);
+ m8820x_cmmu_sync_inval_cache(kvtop(va), size);
else
- m18x_cmmu_inval_cache(kvtop(va), size);
+ m8820x_cmmu_inval_cache(kvtop(va), size);
#endif /* !BROKEN_MMU_MASK */
}
@@ -1930,7 +1733,7 @@ union batcu {
* If cmmu == -1, the data cmmu for the current cpu is used.
*/
void
-m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
+m8820x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
unsigned address, supervisor_flag, verbose_flag;
int cmmu_num;
{
@@ -2010,7 +1813,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
return;
}
- if (cmmu[cmmu_num].cmmu_alive == 0) {
+ if (m8820x_cmmu[cmmu_num].cmmu_alive == 0) {
DEBUG_MSG("warning: cmmu %d is not alive.\n", cmmu_num);
#if 0
return;
@@ -2018,24 +1821,24 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
}
if (!verbose_flag) {
- if (!(cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE))
+ if (!(m8820x_cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE))
DEBUG_MSG("WARNING: snooping not enabled for CMMU#%d.\n",
cmmu_num);
} else {
int i;
for (i=0; i<MAX_CMMUS; i++)
- if ((i == cmmu_num || cmmu[i].cmmu_alive) &&
- (verbose_flag>1 || !(cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) {
+ if ((i == cmmu_num || m8820x_cmmu[i].cmmu_alive) &&
+ (verbose_flag>1 || !(m8820x_cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) {
DEBUG_MSG("CMMU#%d (cpu %d %s) snooping %s\n", i,
- cmmu[i].cmmu_cpu, cmmu[i].which ? "data" : "inst",
- (cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF");
+ m8820x_cmmu[i].cmmu_cpu, m8820x_cmmu[i].which ? "data" : "inst",
+ (m8820x_cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF");
}
}
if (supervisor_flag)
- value = cmmu[cmmu_num].cmmu_regs->sapr;
+ value = m8820x_cmmu[cmmu_num].cmmu_regs->sapr;
else
- value = cmmu[cmmu_num].cmmu_regs->uapr;
+ value = m8820x_cmmu[cmmu_num].cmmu_regs->uapr;
}
@@ -2046,7 +1849,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
int i;
union batcu batc;
for (i = 0; i < 8; i++) {
- batc.bits = cmmu[cmmu_num].batc[i];
+ batc.bits = m8820x_cmmu[cmmu_num].batc[i];
if (batc.field.v == 0) {
if (verbose_flag>1)
DEBUG_MSG("cmmu #%d batc[%d] invalid.\n", cmmu_num, i);
@@ -2070,7 +1873,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
#endif /* 0 */
{
union ssr ssr;
- struct cmmu_regs *cmmu_regs = cmmu[cmmu_num].cmmu_regs;
+ struct cmmu_regs *cmmu_regs = m8820x_cmmu[cmmu_num].cmmu_regs;
cmmu_regs->sar = address;
cmmu_regs->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER;
ssr.bits = cmmu_regs->ssr;
@@ -2265,7 +2068,7 @@ m18x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
}
void
-m18x_cmmu_cache_state(addr, supervisor_flag)
+m8820x_cmmu_cache_state(addr, supervisor_flag)
unsigned addr, supervisor_flag;
{
static char *vv_name[4] =
@@ -2277,12 +2080,12 @@ m18x_cmmu_cache_state(addr, supervisor_flag)
union cssp cssp;
struct cmmu_regs *R;
unsigned tag, line;
- if (!cmmu[cmmu_num].cmmu_alive)
+ if (!m8820x_cmmu[cmmu_num].cmmu_alive)
continue;
- R = cmmu[cmmu_num].cmmu_regs;
+ R = m8820x_cmmu[cmmu_num].cmmu_regs;
DEBUG_MSG("cmmu #%d %s cmmu for cpu %d.\n", cmmu_num,
- cmmu[cmmu_num].which ? "data" : "inst",
- cmmu[cmmu_num].cmmu_cpu);
+ m8820x_cmmu[cmmu_num].which ? "data" : "inst",
+ m8820x_cmmu[cmmu_num].cmmu_cpu);
R->sar = addr;
R->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER;
@@ -2319,20 +2122,22 @@ m18x_cmmu_cache_state(addr, supervisor_flag)
}
+#endif /* DDB */
+
void
-m18x_show_cmmu_info(addr)
+m8820x_show_cmmu_info(addr)
unsigned addr;
{
int cmmu_num;
- m18x_cmmu_cache_state(addr, 1);
+ m8820x_cmmu_cache_state(addr, 1);
for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++)
- if (cmmu[cmmu_num].cmmu_alive) {
+ if (m8820x_cmmu[cmmu_num].cmmu_alive) {
DEBUG_MSG("cmmu #%d %s cmmu for cpu %d: ", cmmu_num,
- cmmu[cmmu_num].which ? "data" : "inst",
- cmmu[cmmu_num].cmmu_cpu);
- m18x_cmmu_show_translation(addr, 1, 0, cmmu_num);
+ m8820x_cmmu[cmmu_num].which ? "data" : "inst",
+ m8820x_cmmu[cmmu_num].cmmu_cpu);
+ m8820x_cmmu_show_translation(addr, 1, 0, cmmu_num);
}
}
-#endif /* DDB */
+#endif /* M88100 */
diff --git a/sys/arch/mvme88k/mvme88k/machdep.c b/sys/arch/mvme88k/mvme88k/machdep.c
index 0f841fa6b5c..0b3b8dc7eca 100644
--- a/sys/arch/mvme88k/mvme88k/machdep.c
+++ b/sys/arch/mvme88k/mvme88k/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.71 2001/12/08 18:05:59 miod Exp $ */
+/* $OpenBSD: machdep.c,v 1.72 2001/12/13 08:55:52 smurph Exp $ */
/*
* Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
* Copyright (c) 1996 Nivas Madhur
@@ -85,13 +85,11 @@
#include <machine/board.h>
#include <machine/bug.h>
#include <machine/bugio.h>
-#include <machine/cmmu.h>
+#include <machine/cmmu.h> /* CMMU stuff */
#include <machine/cpu.h>
#include <machine/cpu_number.h>
#include <machine/kcore.h>
#include <machine/locore.h>
-#include <machine/m88100.h> /* DMT_VALID */
-#include <machine/m882xx.h> /* CMMU stuff */
#include <machine/prom.h>
#include <machine/reg.h>
#include <machine/trap.h>
@@ -102,6 +100,7 @@
#include <mvme88k/dev/sysconreg.h>
#include <mvme88k/dev/pcctworeg.h>
+#include <mvme88k/dev/busswreg.h>
#include "assym.h" /* EF_EPSR, etc. */
#include "ksyms.h"
@@ -122,11 +121,12 @@ struct intrhand *intr_handlers[256];
vm_offset_t interrupt_stack[MAX_CPUS] = {0};
/* machine dependant function pointers. */
-struct funcp mdfp;
+struct md_p md;
/* prototypes */
void m88100_Xfp_precise __P((void));
void m88110_Xfp_precise __P((void));
+void set_tcfp __P((void));
void setupiackvectors __P((void));
void regdump __P((struct trapframe *f));
void dumpsys __P((void));
@@ -135,9 +135,12 @@ vm_offset_t size_memory __P((void));
int getcpuspeed __P((void));
int getscsiid __P((void));
void identifycpu __P((void));
-void save_u_area __P((struct proc *, vm_offset_t));
-void load_u_area __P((struct proc *));
+void save_u_area __P((struct proc *p, vm_offset_t va));
+void load_u_area __P((struct proc *p));
void dumpconf __P((void));
+void m187_ext_int __P((u_int v, struct m88100_saved_state *eframe));
+void m188_ext_int __P((u_int v, struct m88100_saved_state *eframe));
+void m197_ext_int __P((u_int v, struct m88100_saved_state *eframe));
volatile unsigned char *ivec[] = {
(unsigned char *)0xFFFE0003, /* not used, no such thing as int 0 */
@@ -164,18 +167,9 @@ volatile unsigned int *int_mask_reg[MAX_CPUS] = {
};
#endif
-#if defined(MVME187) || defined(MVME197)
-u_char *int_mask_level = (u_char *)INT_MASK_LEVEL;
-u_char *int_pri_level = (u_char *)INT_PRI_LEVEL;
-#endif /* defined(MVME187) || defined(MVME197) */
-
-#if defined(MVME187) || defined(MVME197)
-volatile u_char *pcc2intr_mask;
-volatile u_char *pcc2intr_ipl;
volatile vm_offset_t bugromva;
volatile vm_offset_t sramva;
volatile vm_offset_t obiova;
-#endif /* defined(MVME187) || defined(MVME197) */
#ifdef MVME188
volatile vm_offset_t utilva;
#endif
@@ -229,7 +223,6 @@ caddr_t allocsys __P((caddr_t));
*/
char machine[] = MACHINE; /* cpu "architecture" */
char cpu_model[120];
-extern unsigned master_cpu;
struct bugenv bugargs;
@@ -248,9 +241,11 @@ struct kernel {
extern char *esym;
#endif
-int boothowto; /* read in locore.S */
-int bootdev; /* read in locore.S */
-int cputyp;
+int boothowto; /* set in locore.S */
+int bootdev; /* set in locore.S */
+int cputyp; /* set in locore.S */
+int brdtyp; /* set in locore.S */
+int cpumod = 0; /* set in mvme_bootstrap.S */
int cpuspeed = 25; /* 25 MHZ XXX should be read from NVRAM */
vm_offset_t first_addr = 0;
@@ -282,7 +277,8 @@ static struct consdev bootcons = {
bootcnpollc,
NULL,
makedev(14,0),
- 1};
+ 1
+};
/*
* Console initialization: called early on from main,
@@ -351,10 +347,11 @@ size_memory()
break;
*look = save;
}
- if ((look > (unsigned int *)0x01FFF000) && (cputyp == CPU_188)) {
+ if ((look > (unsigned int *)0x01FFF000) && (brdtyp == BRD_188)) {
/* temp hack to fake 32Meg on MVME188 */
look = (unsigned int *)0x01FFF000;
}
+
physmem = btoc(trunc_page((unsigned)look)); /* in pages */
return (trunc_page((unsigned)look));
}
@@ -394,11 +391,10 @@ getscsiid()
}
void
-identifycpu()
+identifycpu(void)
{
cpuspeed = getcpuspeed();
- sprintf(cpu_model, "Motorola MVME%x %dMhz", cputyp, cpuspeed);
- printf("\nModel: %s\n", cpu_model);
+ printf("\nModel: Motorola MVME%x %dMhz\n", brdtyp, cpuspeed);
}
/*
@@ -439,17 +435,17 @@ cpu_initclocks()
#ifdef DEBUG
printf("cpu_initclocks(): ");
#endif
- if (mdfp.clock_init_func != NULL) {
+ if (md.clock_init_func != NULL) {
#ifdef DEBUG
printf("[interval clock] ");
#endif
- (*mdfp.clock_init_func)();
+ (*md.clock_init_func)();
}
- if (mdfp.statclock_init_func != NULL) {
+ if (md.statclock_init_func != NULL) {
#ifdef DEBUG
printf("[statistics clock]");
#endif
- (*mdfp.statclock_init_func)();
+ (*md.statclock_init_func)();
}
#ifdef DEBUG
printf("\n");
@@ -488,7 +484,7 @@ cpu_startup()
printf(version);
identifycpu();
printf("real mem = %d\n", ctob(physmem));
-
+
/*
* Find out how much space we need, allocate it,
* and then give everything true virtual addresses.
@@ -517,14 +513,27 @@ cpu_startup()
/*
* Grab machine dependant memory spaces
*/
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME187
- case CPU_187:
+ case BRD_187:
+ /*
+ * Grab the SRAM space that we hardwired in pmap_bootstrap
+ */
+ sramva = SRAM_START;
+ uvm_map(kernel_map, (vaddr_t *)&sramva, SRAM_SIZE,
+ NULL, UVM_UNKNOWN_OFFSET,UVM_MAPFLAG(UVM_PROT_NONE,
+ UVM_PROT_NONE,
+ UVM_INH_NONE,
+ UVM_ADV_NORMAL, 0));
+
+ if (sramva != SRAM_START) {
+ printf("sramva %x: SRAM not free\n", sramva);
+ panic("bad sramva");
+ }
#endif
#ifdef MVME197
- case CPU_197:
+ case BRD_197:
#endif
-
#if defined(MVME187) || defined(MVME197)
/*
* Grab the BUGROM space that we hardwired in pmap_bootstrap
@@ -542,21 +551,6 @@ cpu_startup()
}
/*
- * Grab the SRAM space that we hardwired in pmap_bootstrap
- */
- sramva = SRAM_START;
- uvm_map(kernel_map, (vaddr_t *)&sramva, SRAM_SIZE,
- NULL, UVM_UNKNOWN_OFFSET, 0, UVM_MAPFLAG(UVM_PROT_NONE,
- UVM_PROT_NONE,
- UVM_INH_NONE,
- UVM_ADV_NORMAL, 0));
-
- if (sramva != SRAM_START) {
- printf("sramva %x: SRAM not free\n", sramva);
- panic("bad sramva");
- }
-
- /*
* Grab the OBIO space that we hardwired in pmap_bootstrap
*/
obiova = OBIO_START;
@@ -572,7 +566,7 @@ cpu_startup()
break;
#endif
#ifdef MVME188
- case CPU_188:
+ case BRD_188:
/*
* Grab the UTIL space that we hardwired in pmap_bootstrap
*/
@@ -764,9 +758,6 @@ allocsys(v)
* Set registers on exec.
* Clear all except sp and pc.
*/
-
-/* MVME197 TODO list :-) smurph */
-
void
setregs(p, pack, stack, retval)
struct proc *p;
@@ -804,19 +795,34 @@ setregs(p, pack, stack, retval)
}
#endif /* 0 */
bzero((caddr_t)tf, sizeof *tf);
- tf->epsr = PSR_USER; /* user mode, interrupts enabled, fp enabled */
-/* tf->epsr = PSR_USER | PSR_MXM;*/ /* user mode, interrupts enabled, fp enabled, MXM Mask */
+
+ if (cputyp == CPU_88110) {
+ /*
+ * user mode, serialize mem, interrupts enabled,
+ * graphics unit, fp enabled
+ */
+ tf->epsr = PSR_SRM | PSR_SFD;
+ } else {
+ /*
+ * user mode, interrupts enabled,
+ * no graphics unit, fp enabled
+ */
+ tf->epsr = PSR_SFD | PSR_SFD2;
+ }
/*
* We want to start executing at pack->ep_entry. The way to
* do this is force the processor to fetch from ep_entry. Set
* NIP to something bogus and invalid so that it will be a NOOP.
* And set sfip to ep_entry with valid bit on so that it will be
- * fetched.
+ * fetched. mc88110 - just set exip to pack->ep_entry.
*/
-
- tf->snip = pack->ep_entry & ~3;
- tf->sfip = (pack->ep_entry & ~3) | FIP_V;
+ if (cputyp == CPU_88110) {
+ tf->exip = pack->ep_entry & ~3;
+ } else {
+ tf->snip = pack->ep_entry & ~3;
+ tf->sfip = (pack->ep_entry & ~3) | FIP_V;
+ }
tf->r[2] = stack;
tf->r[31] = stack;
retval[1] = 0;
@@ -851,7 +857,6 @@ int sigpid = 0;
/*
* Send an interrupt to process.
*/
-/* MVME197 TODO list :-) smurph */
void
sendsig(catcher, sig, mask, code, type, val)
sig_t catcher;
@@ -894,7 +899,7 @@ sendsig(catcher, sig, mask, code, type, val)
#ifdef DEBUG
if ((sigdebug & SDB_FOLLOW) ||
- (sigdebug & SDB_KSTACK) && p->p_pid == sigpid)
+ ((sigdebug & SDB_KSTACK) && (p->p_pid == sigpid)))
printf("sendsig(%d): sig %d ssp %x usp %x scp %x\n",
p->p_pid, sig, &oonstack, fp, &fp->sf_sc);
#endif
@@ -918,23 +923,46 @@ sendsig(catcher, sig, mask, code, type, val)
*/
bcopy((caddr_t)tf->r, (caddr_t)sf.sf_sc.sc_regs,
sizeof(sf.sf_sc.sc_regs));
- sf.sf_sc.sc_xip = tf->sxip & ~3;
- sf.sf_sc.sc_nip = tf->snip & ~3;
- sf.sf_sc.sc_fip = tf->sfip & ~3;
+ if (cputyp != CPU_88110) {
+ /* mc88100 */
+ sf.sf_sc.sc_xip = tf->sxip & ~3;
+ sf.sf_sc.sc_nip = tf->snip & ~3;
+ sf.sf_sc.sc_fip = tf->sfip & ~3;
+ } else {
+ /* mc88110 */
+ sf.sf_sc.sc_xip = tf->exip & ~3;
+ sf.sf_sc.sc_nip = tf->enip & ~3;
+ sf.sf_sc.sc_fip = 0;
+ }
sf.sf_sc.sc_ps = tf->epsr;
sf.sf_sc.sc_sp = tf->r[31];
sf.sf_sc.sc_fpsr = tf->fpsr;
sf.sf_sc.sc_fpcr = tf->fpcr;
- sf.sf_sc.sc_ssbr = tf->ssbr;
- sf.sf_sc.sc_dmt0 = tf->dmt0;
- sf.sf_sc.sc_dmd0 = tf->dmd0;
- sf.sf_sc.sc_dma0 = tf->dma0;
- sf.sf_sc.sc_dmt1 = tf->dmt1;
- sf.sf_sc.sc_dmd1 = tf->dmd1;
- sf.sf_sc.sc_dma1 = tf->dma1;
- sf.sf_sc.sc_dmt2 = tf->dmt2;
- sf.sf_sc.sc_dmd2 = tf->dmd2;
- sf.sf_sc.sc_dma2 = tf->dma2;
+ if (cputyp != CPU_88110) {
+ /* mc88100 */
+ sf.sf_sc.sc_ssbr = tf->ssbr;
+ sf.sf_sc.sc_dmt0 = tf->dmt0;
+ sf.sf_sc.sc_dmd0 = tf->dmd0;
+ sf.sf_sc.sc_dma0 = tf->dma0;
+ sf.sf_sc.sc_dmt1 = tf->dmt1;
+ sf.sf_sc.sc_dmd1 = tf->dmd1;
+ sf.sf_sc.sc_dma1 = tf->dma1;
+ sf.sf_sc.sc_dmt2 = tf->dmt2;
+ sf.sf_sc.sc_dmd2 = tf->dmd2;
+ sf.sf_sc.sc_dma2 = tf->dma2;
+ } else {
+ /* mc88110 */
+ sf.sf_sc.sc_dsr = tf->dsr;
+ sf.sf_sc.sc_dlar = tf->dlar;
+ sf.sf_sc.sc_dpar = tf->dpar;
+ sf.sf_sc.sc_isr = tf->isr;
+ sf.sf_sc.sc_ilar = tf->ilar;
+ sf.sf_sc.sc_ipar = tf->ipar;
+ sf.sf_sc.sc_isap = tf->isap;
+ sf.sf_sc.sc_dsap = tf->dsap;
+ sf.sf_sc.sc_iuap = tf->iuap;
+ sf.sf_sc.sc_duap = tf->duap;
+ }
sf.sf_sc.sc_fpecr = tf->fpecr;
sf.sf_sc.sc_fphs1 = tf->fphs1;
sf.sf_sc.sc_fpls1 = tf->fpls1;
@@ -962,12 +990,19 @@ sendsig(catcher, sig, mask, code, type, val)
* Signal trampoline code is at base of user stack.
*/
addr = (int)PS_STRINGS - szsigcode;
- tf->snip = (addr & ~3) | NIP_V;
- tf->sfip = (tf->snip + 4) | FIP_V;
+ if (cputyp != CPU_88110) {
+ /* mc88100 */
+ tf->snip = (addr & ~3) | NIP_V;
+ tf->sfip = (tf->snip + 4) | FIP_V;
+ } else {
+ /* mc88110 */
+ tf->exip = (addr & ~3);
+ tf->enip = (tf->exip + 4);
+ }
tf->r[31] = (unsigned)fp;
#ifdef DEBUG
if ((sigdebug & SDB_FOLLOW) ||
- (sigdebug & SDB_KSTACK) && p->p_pid == sigpid)
+ ((sigdebug & SDB_KSTACK) && p->p_pid == sigpid))
printf("sendsig(%d): sig %d returns\n", p->p_pid, sig);
#endif
}
@@ -982,10 +1017,8 @@ sendsig(catcher, sig, mask, code, type, val)
* psl to gain improper priviledges or to cause
* a machine fault.
*/
-/* ARGSUSED */
-
-/* MVME197 TODO list :-) smurph */
+/* ARGSUSED */
int
sys_sigreturn(p, v, retval)
struct proc *p;
@@ -1030,25 +1063,47 @@ register_t *retval;
* bcopy(sc_reg to tf, sizeof sigcontext - 2 words)
* XXX nivas
*/
-
bcopy((caddr_t)scp->sc_regs, (caddr_t)tf->r, sizeof(scp->sc_regs));
- tf->sxip = (scp->sc_xip) | XIP_V;
- tf->snip = (scp->sc_nip) | NIP_V;
- tf->sfip = (scp->sc_fip) | FIP_V;
+ if (cputyp != CPU_88110) {
+ /* mc88100 */
+ tf->sxip = (scp->sc_xip) | XIP_V;
+ tf->snip = (scp->sc_nip) | NIP_V;
+ tf->sfip = (scp->sc_fip) | FIP_V;
+ } else {
+ /* mc88110 */
+ tf->exip = (scp->sc_xip);
+ tf->enip = (scp->sc_nip);
+ tf->sfip = 0;
+ }
tf->epsr = scp->sc_ps;
tf->r[31] = scp->sc_sp;
tf->fpsr = scp->sc_fpsr;
tf->fpcr = scp->sc_fpcr;
- tf->ssbr = scp->sc_ssbr;
- tf->dmt0 = scp->sc_dmt0;
- tf->dmd0 = scp->sc_dmd0;
- tf->dma0 = scp->sc_dma0;
- tf->dmt1 = scp->sc_dmt1;
- tf->dmd1 = scp->sc_dmd1;
- tf->dma1 = scp->sc_dma1;
- tf->dmt2 = scp->sc_dmt2;
- tf->dmd2 = scp->sc_dmd2;
- tf->dma2 = scp->sc_dma2;
+ if (cputyp != CPU_88110) {
+ /* mc88100 */
+ tf->ssbr = scp->sc_ssbr;
+ tf->dmt0 = scp->sc_dmt0;
+ tf->dmd0 = scp->sc_dmd0;
+ tf->dma0 = scp->sc_dma0;
+ tf->dmt1 = scp->sc_dmt1;
+ tf->dmd1 = scp->sc_dmd1;
+ tf->dma1 = scp->sc_dma1;
+ tf->dmt2 = scp->sc_dmt2;
+ tf->dmd2 = scp->sc_dmd2;
+ tf->dma2 = scp->sc_dma2;
+ } else {
+ /* mc88110 */
+ tf->dsr = scp->sc_dsr;
+ tf->dlar = scp->sc_dlar;
+ tf->dpar = scp->sc_dpar;
+ tf->isr = scp->sc_isr;
+ tf->ilar = scp->sc_ilar;
+ tf->ipar = scp->sc_ipar;
+ tf->isap = scp->sc_isap;
+ tf->dsap = scp->sc_dsap;
+ tf->iuap = scp->sc_iuap;
+ tf->duap = scp->sc_duap;
+ }
tf->fpecr = scp->sc_fpecr;
tf->fphs1 = scp->sc_fphs1;
tf->fpls1 = scp->sc_fpls1;
@@ -1158,7 +1213,7 @@ cpu_kcore_hdr_t cpu_kcore_hdr;
* reduce the chance that swapping trashes it.
*/
void
-dumpconf()
+dumpconf(void)
{
int nblks; /* size of dump area */
int maj;
@@ -1324,9 +1379,9 @@ setupiackvectors()
* map a page in for phys address 0xfffe0000 (M187) and set the
* addresses for various levels.
*/
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME187
- case CPU_187:
+ case BRD_187:
#ifdef MAP_VEC /* do for MVME188 too */
vaddr = (u_char *)iomap_mapin(M187_IACK, NBPG, 1);
#else
@@ -1335,7 +1390,7 @@ setupiackvectors()
break;
#endif /* MVME187 */
#ifdef MVME188
- case CPU_188:
+ case BRD_188:
#ifdef MAP_VEC /* do for MVME188 too */
vaddr = (u_char *)iomap_mapin(M188_IACK, NBPG, 1);
#else
@@ -1350,11 +1405,11 @@ setupiackvectors()
ivec[6] = vaddr + 0x18;
ivec[7] = vaddr + 0x1c;
ivec[8] = vaddr + 0x20; /* for self inflicted interrupts */
- *ivec[8] = M188_IVEC; /* supply a vector for m188ih */
+ *ivec[8] = M188_IVEC; /* supply a vector base for m188ih */
break;
#endif /* MVME188 */
#ifdef MVME197
- case CPU_197:
+ case BRD_197:
#ifdef MAP_VEC /* do for MVME188 too */
vaddr = (u_char *)iomap_mapin(M197_IACK, NBPG, 1);
#else
@@ -1368,7 +1423,7 @@ setupiackvectors()
#endif
#if defined(MVME187) || defined(MVME197)
- if (cputyp != CPU_188) {
+ if (brdtyp != BRD_188) {
ivec[0] = vaddr + 0x03; /* We dont use level 0 */
ivec[1] = vaddr + 0x07;
ivec[2] = vaddr + 0x0b;
@@ -1692,9 +1747,9 @@ out_m188:
* the routine.
*/
-#if defined(MVME187) || defined(MVME197)
+#ifdef MVME187
void
-sbc_ext_int(u_int v, struct m88100_saved_state *eframe)
+m187_ext_int(u_int v, struct m88100_saved_state *eframe)
{
register u_char mask, level;
register struct intrhand *intr;
@@ -1702,8 +1757,8 @@ sbc_ext_int(u_int v, struct m88100_saved_state *eframe)
u_char vec;
/* get level and mask */
- asm volatile("ld.b %0,%1" : "=r" (mask) : "" (*pcc2intr_mask));
- asm volatile("ld.b %0,%1" : "=r" (level) : "" (*pcc2intr_ipl));
+ asm volatile("ld.b %0,%1" : "=r" (mask) : "" (*md.intr_mask));
+ asm volatile("ld.b %0,%1" : "=r" (level) : "" (*md.intr_ipl));
/*
* It is really bizarre for the mask and level to the be the same.
@@ -1793,15 +1848,117 @@ sbc_ext_int(u_int v, struct m88100_saved_state *eframe)
disable_interrupt();
out:
-#ifdef MVME187
- if (cputyp != CPU_197) {
- if (eframe->dmt0 & DMT_VALID) {
- trap18x(T_DATAFLT, eframe);
- data_access_emulation((unsigned *)eframe);
- eframe->dmt0 &= ~DMT_VALID;
+ if (eframe->dmt0 & DMT_VALID) {
+ trap(T_DATAFLT, eframe);
+ data_access_emulation((unsigned *)eframe);
+ eframe->dmt0 &= ~DMT_VALID;
+ }
+ mask = eframe->mask;
+
+ /*
+ * Restore the mask level to what it was when the interrupt
+ * was taken.
+ */
+ setipl((u_char)mask);
+}
+#endif /* MVME187 */
+
+#ifdef MVME197
+void
+m197_ext_int(u_int v, struct m88100_saved_state *eframe)
+{
+ register u_char mask, level, src;
+ register struct intrhand *intr;
+ int ret;
+ u_char vec;
+
+ /* get src and mask */
+ asm volatile("ld.b %0,%1" : "=r" (mask) : "" (*md.intr_mask));
+ asm volatile("ld.b %0,%1" : "=r" (src) : "" (*md.intr_src));
+
+ if (v == T_NON_MASK) {
+ /* This is the abort switch */
+ level = IPL_NMI;
+ vec = BS_ABORTVEC;
+ } else {
+ /* get level */
+ asm volatile("ld.b %0,%1" : "=r" (level) : "" (*md.intr_ipl));
+ }
+
+ /*
+ * Interrupting level cannot be 0--0 doesn't produce an interrupt.
+ * Weird! XXX nivas
+ */
+
+ if (level == 0) {
+ printf("Bogons... level %x and mask %x\n", level, mask);
+ goto m197beatit;
+ }
+
+ /* and block interrupts at level or lower */
+ setipl((u_char)level);
+ /* and stash it away in the trap frame */
+ eframe->mask = mask;
+
+ if (level > 7 || (char)level < 0) {
+ panic("int level (%x) is not between 0 and 7", level);
+ }
+
+ if (v != T_NON_MASK) {
+ /* generate IACK and get the vector */
+ asm volatile("tb1 0, r0, 0");
+ if (guarded_access(ivec[level], 1, &vec) == EFAULT) {
+ printf("Unable to get vector for this interrupt (level %x)\n", level);
+ goto m197out;
}
+ asm volatile("tb1 0, r0, 0");
+ asm volatile("tb1 0, r0, 0");
+ asm volatile("tb1 0, r0, 0");
}
-#endif
+
+ if (vec > 0xFF) {
+ panic("interrupt vector %x greater than 255", vec);
+ }
+
+ enable_interrupt();
+
+ if ((intr = intr_handlers[vec]) == 0) {
+ /* increment intr counter */
+ intrcnt[M88K_SPUR_IRQ]++;
+ printf("Spurious interrupt (level %x and vec %x)\n",
+ level, vec);
+ }
+ if (intr && intr->ih_ipl != level) {
+ panic("Handler ipl %x not the same as level %x. vec = 0x%x",
+ intr->ih_ipl, level, vec);
+ }
+
+ /*
+ * Walk through all interrupt handlers in the chain for the
+ * given vector, calling each handler in turn, till some handler
+ * returns a value != 0.
+ */
+
+ for (ret = 0; intr; intr = intr->ih_next) {
+ if (intr->ih_wantframe != 0)
+ ret = (*intr->ih_fn)((void *)eframe);
+ else
+ ret = (*intr->ih_fn)(intr->ih_arg);
+ if (ret){
+ /* increment intr counter */
+ intrcnt[level]++;
+ break;
+ }
+ }
+
+ if (ret == 0) {
+ printf("Unclaimed interrupt (level %x and vec %x)\n",
+ level, vec);
+ }
+
+ disable_interrupt();
+
+m197out:
mask = eframe->mask;
/*
@@ -1809,8 +1966,11 @@ out:
* was taken.
*/
setipl((u_char)mask);
+
+m197beatit:
+ return;
}
-#endif /* defined(MVME187) || defined(MVME197) */
+#endif
int
cpu_exec_aout_makecmds(p, epp)
@@ -2102,13 +2262,13 @@ regdump(struct trapframe *f)
printf("R24-29: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
R(24),R(25),R(26),R(27),R(28),R(29));
printf("R30-31: 0x%08x 0x%08x\n",R(30),R(31));
- if (cputyp == CPU_197) {
- printf("exip %x enip %x\n", f->sxip, f->snip);
+ if (cputyp == CPU_88110) {
+ printf("exip %x enip %x\n", f->exip, f->enip);
} else {
printf("sxip %x snip %x sfip %x\n", f->sxip, f->snip, f->sfip);
}
-#if defined(MVME187) || defined(MVME188)
- if (f->vector == 0x3 && cputyp != CPU_197) {
+#ifdef M88100
+ if (f->vector == 0x3 && cputyp != CPU_88110) {
/* print dmt stuff for data access fault */
printf("dmt0 %x dmd0 %x dma0 %x\n", f->dmt0, f->dmd0, f->dma0);
printf("dmt1 %x dmd1 %x dma1 %x\n", f->dmt1, f->dmd1, f->dma1);
@@ -2116,50 +2276,31 @@ regdump(struct trapframe *f)
printf("fault type %d\n", (f->dpfsr >> 16) & 0x7);
dae_print((unsigned *)f);
}
- if (longformat && cputyp != CPU_197) {
- printf("fpsr %x ", f->fpsr);
- printf("fpcr %x ", f->fpcr);
- printf("epsr %x ", f->epsr);
- printf("ssbr %x\n", f->ssbr);
- printf("fpecr %x ", f->fpecr);
- printf("fphs1 %x ", f->fphs1);
- printf("fpls1 %x ", f->fpls1);
- printf("fphs2 %x ", f->fphs2);
- printf("fpls2 %x\n", f->fpls2);
- printf("fppt %x ", f->fppt);
- printf("fprh %x ", f->fprh);
- printf("fprl %x ", f->fprl);
- printf("fpit %x\n", f->fpit);
- printf("vector %d ", f->vector);
- printf("mask %x ", f->mask);
- printf("mode %x ", f->mode);
- printf("scratch1 %x ", f->scratch1);
- printf("cpu %x\n", f->cpu);
+ if (longformat && cputyp != CPU_88110) {
+ printf("fpsr %x fpcr %x epsr %x ssbr %x\n",
+ f->fpsr, f->fpcr, f->epsr, f->ssbr);
+ printf("fpecr %x fphs1 %x fpls1 %x fphs2 %x fpls2 %x\n",
+ f->fpecr, f->fphs1, f->fpls1, f->fphs2, f->fpls2);
+ printf("fppt %x fprh %x fprl %x fpit %x\n",
+ f->fppt, f->fprh, f->fprl, f->fpit);
+ printf("vector %d mask %x mode %x scratch1 %x cpu %x\n",
+ f->vector, f->mask, f->mode, f->scratch1, f->cpu);
}
#endif
-#ifdef MVME197
- if (longformat && cputyp == CPU_197) {
- printf("fpsr %x ", f->fpsr);
- printf("fpcr %x ", f->fpcr);
- printf("fpecr %x ", f->fpecr);
- printf("epsr %x\n", f->epsr);
- printf("dsap %x ", f->dmt1);
- printf("dsr %x ", f->dsr);
- printf("dlar %x ", f->dlar);
- printf("dpar %x\n", f->dpar);
- printf("isap %x ", f->dmt0);
- printf("isr %x ", f->isr);
- printf("ilar %x ", f->ilar);
- printf("ipar %x\n", f->ipar);
- printf("vector %d ", f->vector);
- printf("mask %x ", f->mask);
- printf("mode %x ", f->mode);
- printf("scratch1 %x ", f->scratch1);
- printf("cpu %x\n", f->cpu);
+#ifdef M88110
+ if (longformat && cputyp == CPU_88110) {
+ printf("fpsr %x fpcr %x fpecr %x epsr %x\n",
+ f->fpsr, f->fpcr, f->fpecr, f->epsr);
+ printf("dsap %x duap %x dsr %x dlar %x dpar %x\n",
+ f->dsap, f->duap, f->dsr, f->dlar, f->dpar);
+ printf("isap %x iuap %x isr %x ilar %x ipar %x\n",
+ f->isap, f->iuap, f->isr, f->ilar, f->ipar);
+ printf("vector %d mask %x mode %x scratch1 %x cpu %x\n",
+ f->vector, f->mask, f->mode, f->scratch1, f->cpu);
}
#endif
#ifdef MVME188
- if (cputyp == CPU_188 ) {
+ if (brdtyp == BRD_188 ) {
unsigned int istr, cur_mask;
istr = *(volatile int *)IST_REG;
@@ -2175,6 +2316,7 @@ regdump(struct trapframe *f)
* Called from locore.S during boot,
* this is the first C code that's run.
*/
+#define ILLADDRESS U(0x0F000000) /* any faulty address */
void
mvme_bootstrap()
@@ -2184,27 +2326,42 @@ mvme_bootstrap()
extern void set_tcfp __P((void));
struct bugbrdid brdid;
+
+ cold = 1; /* we are still booting */
+
+ /*
+ * Must initialize p_addr before autoconfig or
+ * the fault handler will get a NULL reference.
+ * Do this early so that we can take a data or
+ * instruction fault and survive it. XXX smurph
+ */
+ proc0.p_addr = proc0paddr;
+ curproc = &proc0;
+ curpcb = &proc0paddr->u_pcb;
/* zreo out the machine dependant function pointers */
- bzero(&mdfp, sizeof(struct funcp));
+ bzero(&md, sizeof(struct md_p));
buginit(); /* init the bug routines */
bugbrdid(&brdid);
- cputyp = brdid.brdno;
+ brdtyp = brdid.brdno;
/* to support the M8120. It's based off of MVME187 */
- if (cputyp == 0x8120)
- cputyp = CPU_187;
+ if (brdtyp == BRD_8120)
+ brdtyp = BRD_187;
/*
- * set up interrupt and fp exception handlers
- * based on the machine.
+ * set up interrupt, fp exception handlers
+ * and cmmu pointers based on the machine.
*/
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME188
- case CPU_188:
- mdfp.interrupt_func = &m188_ext_int;
- mdfp.fp_precise_func = &m88100_Xfp_precise;
+ case BRD_188:
+ cmmu = &cmmu8820x;
+ md.interrupt_func = &m188_ext_int;
+ md.fp_precise_func = &m88100_Xfp_precise;
+ md.trap_func = &m88100_trap;
+ md.syscall_func = &m88100_syscall;
/* clear and disable all interrupts */
*int_mask_reg[0] = 0;
*int_mask_reg[1] = 0;
@@ -2213,15 +2370,27 @@ mvme_bootstrap()
break;
#endif /* MVME188 */
#ifdef MVME187
- case CPU_187:
- mdfp.interrupt_func = &sbc_ext_int;
- mdfp.fp_precise_func = &m88100_Xfp_precise;
+ case BRD_187:
+ cmmu = &cmmu8820x;
+ md.interrupt_func = &m187_ext_int;
+ md.fp_precise_func = &m88100_Xfp_precise;
+ md.trap_func = &m88100_trap;
+ md.syscall_func = &m88100_syscall;
+ md.intr_mask = (u_char *)M187_IMASK;
+ md.intr_ipl = (u_char *)M187_ILEVEL;
+ md.intr_src = NULL;
break;
#endif /* MVME187 */
#ifdef MVME197
- case CPU_197:
- mdfp.interrupt_func = &sbc_ext_int;
- mdfp.fp_precise_func = &m88110_Xfp_precise;
+ case BRD_197:
+ cmmu = &cmmu88110;
+ md.interrupt_func = &m197_ext_int;
+ md.fp_precise_func = &m88110_Xfp_precise;
+ md.trap_func = &m88110_trap;
+ md.syscall_func = &m88110_syscall;
+ md.intr_mask = (u_char *)M197_IMASK;
+ md.intr_ipl = (u_char *)M197_ILEVEL;
+ md.intr_src = (u_char *)M197_ISRC;
set_tcfp(); /* Set Time Critical Floating Point Mode */
break;
#endif /* MVME197 */
@@ -2237,6 +2406,7 @@ mvme_bootstrap()
first_addr = round_page(first_addr);
last_addr = size_memory();
+
cmmu_parity_enable();
setup_board_config();
@@ -2246,7 +2416,7 @@ mvme_bootstrap()
printf("CPU%d is master CPU\n", master_cpu);
#ifdef notevenclose
- if (cputyp == CPU_188 && (boothowto & RB_MINIROOT)) {
+ if (brdtyp == BRD_188 && (boothowto & RB_MINIROOT)) {
int i;
for (i=0; i<MAX_CPUS; i++) {
if (!spin_cpu(i))
@@ -2260,13 +2430,13 @@ mvme_bootstrap()
* Steal MSGBUFSIZE at the top of physical memory for msgbuf
*/
avail_end -= round_page(MSGBUFSIZE);
+
#ifdef DEBUG
- printf("MVME%x boot: memory from 0x%x to 0x%x\n", cputyp, avail_start, avail_end);
+ printf("MVME%x boot: memory from 0x%x to 0x%x\n", brdtyp, avail_start, avail_end);
#endif
pmap_bootstrap((vm_offset_t)trunc_page((unsigned)&kernelstart) /* = loadpt */,
&avail_start, &avail_end, &virtual_avail,
&virtual_end);
-
/*
* Tell the VM system about available physical memory.
* mvme88k only has one segment.
@@ -2274,14 +2444,6 @@ mvme_bootstrap()
uvm_page_physload(atop(avail_start), atop(avail_end),
atop(avail_start), atop(avail_end),VM_FREELIST_DEFAULT);
- /*
- * Must initialize p_addr before autoconfig or
- * the fault handler will get a NULL reference.
- */
- proc0.p_addr = proc0paddr;
- curproc = &proc0;
- curpcb = &proc0paddr->u_pcb;
-
/* Initialize cached PTEs for u-area mapping. */
save_u_area(&proc0, (vm_offset_t)proc0paddr);
diff --git a/sys/arch/mvme88k/mvme88k/pmap.c b/sys/arch/mvme88k/mvme88k/pmap.c
index c3534965394..80b92940e2f 100644
--- a/sys/arch/mvme88k/mvme88k/pmap.c
+++ b/sys/arch/mvme88k/mvme88k/pmap.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap.c,v 1.52 2001/12/12 19:34:23 miod Exp $ */
+/* $OpenBSD: pmap.c,v 1.53 2001/12/13 08:55:52 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
* All rights reserved.
@@ -63,7 +63,6 @@
#include <machine/board.h>
#include <machine/cmmu.h>
#include <machine/cpu_number.h>
-#include <machine/m882xx.h> /* CMMU stuff */
#include <machine/pmap_table.h>
#include <machine/pte.h>
@@ -118,7 +117,7 @@ extern vm_offset_t virtual_avail, virtual_end;
#define CD_CHKM 0x4000000 /* check_map */
#define CD_ALL 0x0FFFFFC
-int pmap_con_dbg = CD_NONE;
+int pmap_con_dbg = CD_NONE; /* CD_FULL | CD_NORM | CD_BOOT | CD_MAP; */
#endif /* DEBUG */
struct pool pmappool, pvpool;
@@ -165,7 +164,7 @@ kpdt_entry_t kpdt_free;
#define M1x7_PDT_SIZE 0
#endif
-#define OBIO_PDT_SIZE ((cputyp == CPU_188) ? M188_PDT_SIZE : M1x7_PDT_SIZE)
+#define OBIO_PDT_SIZE ((brdtyp == BRD_188) ? M188_PDT_SIZE : M1x7_PDT_SIZE)
#define MAX_KERNEL_PDT_SIZE (KERNEL_PDT_SIZE + OBIO_PDT_SIZE)
/*
@@ -331,6 +330,8 @@ extern vm_offset_t bugromva;
extern vm_offset_t sramva;
extern vm_offset_t obiova;
+/* FORWARDS */
+unsigned int m88k_protection __P((pmap_t map, vm_prot_t prot));
void flush_atc_entry __P((long, vm_offset_t, boolean_t));
pt_entry_t *pmap_expand_kmap __P((vm_offset_t, vm_prot_t));
void pmap_free_tables __P((pmap_t));
@@ -348,12 +349,7 @@ void pmap_set_batc __P((pmap_t, boolean_t, int, vm_offset_t, vm_offset_t,
boolean_t, boolean_t, boolean_t, boolean_t, boolean_t, boolean_t));
pt_entry_t *pmap_pte __P((pmap_t, vm_offset_t));
void pmap_remove_all __P((vm_offset_t));
-
-/*
- * PTE field macros
- */
-
-#define m88k_protection(prot) ((prot) & VM_PROT_WRITE ? PG_RW : PG_RO)
+void check_map __P((pmap_t map, vm_offset_t s, vm_offset_t e, char *who));
/*
* Routine: FLUSH_ATC_ENTRY
@@ -390,6 +386,33 @@ flush_atc_entry(long users, vm_offset_t va, boolean_t kernel)
}
/*
+ * Convert machine-independent protection code to M88K protection bits.
+ */
+
+unsigned int
+m88k_protection(pmap_t map, vm_prot_t prot)
+{
+ pte_template_t p;
+
+ p.bits = 0;
+ p.pte.prot = (prot & VM_PROT_WRITE) ? 0 : 1;
+#ifdef M88110
+ if (cputyp == CPU_88110) {
+ p.pte.pg_used = 1;
+ /* if the map is the kernel's map and since this
+ * is not a paged kernel, we go ahead and mark
+ * the page as modified to avoid an exception
+ * upon writing to the page the first time. XXX smurph
+ */
+ if (map == kernel_pmap) {
+ p.pte.modified = p.pte.prot ? 0 : 1;
+ }
+ }
+#endif
+ return (p.bits);
+} /* m88k_protection */
+
+/*
* Routine: PMAP_PTE
*
* Function:
@@ -415,7 +438,6 @@ pt_entry_t *
pmap_pte(pmap_t map, vm_offset_t virt)
{
sdt_entry_t *sdt;
-
#ifdef DIAGNOSTIC
/*XXX will this change if physical memory is not contiguous? */
/* take a look at PDTIDX XXXnivas */
@@ -430,7 +452,7 @@ pmap_pte(pmap_t map, vm_offset_t virt)
if (!SDT_VALID(sdt))
return (PT_ENTRY_NULL);
else
- return ((pt_entry_t *)(((sdt + SDT_ENTRIES)->table_addr)<<PDT_SHIFT) +
+ return ((pt_entry_t *)(((sdt+SDT_ENTRIES)->table_addr)<<PDT_SHIFT) +
PDTIDX(virt));
} /* pmap_pte */
@@ -482,7 +504,7 @@ pmap_expand_kmap(vm_offset_t virt, vm_prot_t prot)
if ((pmap_con_dbg & (CD_KMAP | CD_FULL)) == (CD_KMAP | CD_FULL))
printf("(pmap_expand_kmap :%x) v %x\n", curproc,virt);
#endif
- aprot = m88k_protection(prot);
+ aprot = m88k_protection(map, prot);
/* segment table entry derivate from map and virt. */
sdt = SDTENT(map, virt);
@@ -495,8 +517,9 @@ pmap_expand_kmap(vm_offset_t virt, vm_prot_t prot)
return (PT_ENTRY_NULL);
}
kpdt_free = kpdt_free->next;
-
+ /* physical table */
((sdt_entry_template_t *)sdt)->bits = kpdt_ent->phys | aprot | DT_VALID;
+ /* virtual table */
((sdt_entry_template_t *)(sdt + SDT_ENTRIES))->bits = (vm_offset_t)kpdt_ent | aprot | DT_VALID;
(unsigned)(kpdt_ent->phys) = 0;
(unsigned)(kpdt_ent->next) = 0;
@@ -558,9 +581,6 @@ pmap_map(virt, start, end, prot, cmode)
unsigned num_phys_pages;
pt_entry_t *pte;
pte_template_t template;
-#ifdef MVME197
- static int m197_atc_initialized = FALSE;
-#endif
#ifdef DEBUG
if ((pmap_con_dbg & (CD_MAP | CD_NORM)) == (CD_MAP | CD_NORM))
@@ -573,14 +593,13 @@ pmap_map(virt, start, end, prot, cmode)
panic("pmap_map: start greater than end address");
#endif
- aprot = m88k_protection(prot);
-
+ aprot = m88k_protection(kernel_pmap, prot);
+
template.bits = trunc_page(start) | aprot | cmode | DT_VALID;
-
+
npages = atop(round_page(end) - trunc_page(start));
for (num_phys_pages = npages; num_phys_pages > 0; num_phys_pages--) {
-
if ((pte = pmap_pte(kernel_pmap, virt)) == PT_ENTRY_NULL)
if ((pte = pmap_expand_kmap(virt, VM_PROT_READ|VM_PROT_WRITE)) == PT_ENTRY_NULL)
panic("pmap_map: Cannot allocate pte table");
@@ -591,23 +610,10 @@ pmap_map(virt, start, end, prot, cmode)
printf("(pmap_map :%x) pte @ 0x%x already valid\n", curproc, (unsigned)pte);
#endif
*pte = template.pte;
-#ifdef MVME197
- /* hack for MVME197 */
- if (cputyp == CPU_197 && m197_atc_initialized == FALSE) {
- int i;
-
- for (i = 0; i < 32; i++)
- m197_load_patc(i, virt,
- (vm_offset_t)template.bits, 1);
- m197_atc_initialized = TRUE;
- }
-#endif
virt += PAGE_SIZE;
template.bits += PAGE_SIZE;
}
-
return (virt);
-
} /* pmap_map() */
/*
@@ -677,7 +683,7 @@ pmap_map_batc(virt, start, end, prot, cmode)
panic("pmap_map_batc: start greater than end address");
#endif
- aprot = m88k_protection(prot);
+ aprot = m88k_protection(kernel_pmap, prot);
template.bits = trunc_page(start) | aprot | DT_VALID | cmode;
phys = start;
batctmp.bits = 0;
@@ -692,7 +698,6 @@ pmap_map_batc(virt, start, end, prot, cmode)
trunc_page(start));
while (num_phys_pages > 0) {
-
#ifdef DEBUG
if ((pmap_con_dbg & (CD_MAPB | CD_FULL)) == (CD_MAPB | CD_FULL))
printf("(pmap_map_batc :%x) num_phys_pg=%x, virt=%x, aligne V=%d, phys=%x, aligne P=%d\n", curproc,
@@ -749,9 +754,7 @@ pmap_map_batc(virt, start, end, prot, cmode)
template.bits += PAGE_SIZE;
num_phys_pages--;
}
-
return (round_page(virt));
-
} /* pmap_map_batc() */
/*
@@ -829,7 +832,6 @@ pmap_cache_ctrl(pmap_t pmap, vm_offset_t s, vm_offset_t e, unsigned mode)
printf("(cache_ctrl) pte@0x%08x\n",(unsigned)pte);
}
#endif /* DEBUG */
-
/*
* Invalidate pte temporarily to avoid being written back
* the modified bit and/or the reference bit by other cpu.
@@ -846,11 +848,8 @@ pmap_cache_ctrl(pmap_t pmap, vm_offset_t s, vm_offset_t e, unsigned mode)
if (cpu_sets[cpu])
cmmu_flush_remote_cache(cpu, ptoa(pte->pfn),
PAGE_SIZE);
-
}
-
PMAP_UNLOCK(pmap, spl);
-
} /* pmap_cache_ctrl */
/*
@@ -915,13 +914,13 @@ pmap_bootstrap(vm_offset_t load_start,
kpdt_phys,
s_text,
e_text,
- kernel_pmap_size;
+ kernel_pmap_size,
+ pdt_size;
apr_template_t apr_data;
pt_entry_t *pte;
int i;
pmap_table_t ptable;
extern char *kernelstart, *etext;
- extern void cmmu_go_virt(void);
#ifdef DEBUG
if ((pmap_con_dbg & (CD_BOOT | CD_NORM)) == (CD_BOOT | CD_NORM)) {
@@ -966,8 +965,8 @@ pmap_bootstrap(vm_offset_t load_start,
#ifdef DEBUG
if ((pmap_con_dbg & (CD_BOOT | CD_FULL)) == (CD_BOOT | CD_FULL)) {
- printf("kernel_pmap->sdt_paddr = %x\n",kernel_pmap->sdt_paddr);
- printf("kernel_pmap->sdt_vaddr = %x\n",kernel_pmap->sdt_vaddr);
+ printf("kernel_pmap->sdt_paddr = 0x%x\n",kernel_pmap->sdt_paddr);
+ printf("kernel_pmap->sdt_vaddr = 0x%x\n",kernel_pmap->sdt_vaddr);
}
/* init double-linked list of pmap structure */
kernel_pmap->next = kernel_pmap;
@@ -986,30 +985,52 @@ pmap_bootstrap(vm_offset_t load_start,
* Just to be consistent, we will maintain the shadow table for
* kernel pmap also.
*/
-
kernel_pmap_size = 2*SDT_SIZE;
+
#ifdef DEBUG
- printf("kernel segment table from 0x%x to 0x%x\n", kernel_pmap->sdt_vaddr,
- kernel_pmap->sdt_vaddr + kernel_pmap_size);
+ if ((pmap_con_dbg & (CD_BOOT | CD_FULL)) == (CD_BOOT | CD_FULL)) {
+ printf(" kernel segment start = 0x%x\n", kernel_pmap->sdt_paddr);
+ printf("kernel segment table size = 0x%x\n", kernel_pmap_size);
+ printf(" kernel segment end = 0x%x\n", ((unsigned)kernel_pmap->sdt_paddr) + kernel_pmap_size);
+ }
#endif
- /* save pointers to where page table entries start in physical memory */
- kpdt_phys = (*phys_start + kernel_pmap_size);
- kpdt_virt = (kpdt_entry_t)(*virt_start + kernel_pmap_size);
- kernel_pmap_size += MAX_KERNEL_PDT_SIZE;
+ /* init all segment descriptors to zero */
+ bzero(kernel_pmap->sdt_vaddr, kernel_pmap_size);
+
*phys_start += kernel_pmap_size;
*virt_start += kernel_pmap_size;
-
- /* init all segment and page descriptor to zero */
- bzero(kernel_pmap->sdt_vaddr, kernel_pmap_size);
+
+ /* make sure page tables are page aligned!! XXX smurph */
+ *phys_start = round_page(*phys_start);
+ *virt_start = round_page(*virt_start);
+
+ /* save pointers to where page table entries start in physical memory */
+ kpdt_phys = *phys_start;
+ kpdt_virt = (kpdt_entry_t)*virt_start;
+
+ pdt_size = MAX_KERNEL_PDT_SIZE;
+ /* might as well round up to a page - XXX smurph */
+ pdt_size = round_page(pdt_size);
+ kernel_pmap_size += pdt_size;
+ *phys_start += pdt_size;
+ *virt_start += pdt_size;
+
+ /* init all page descriptors to zero */
+ bzero((void *)kpdt_phys, pdt_size);
#ifdef DEBUG
- printf("kernel page table to 0x%x\n", kernel_pmap->sdt_vaddr + kernel_pmap_size);
+ if ((pmap_con_dbg & (CD_BOOT | CD_FULL)) == (CD_BOOT | CD_FULL)) {
+ printf("--------------------------------------\n");
+ printf(" kernel page start = 0x%x\n", kpdt_phys);
+ printf(" kernel page table size = 0x%x\n", pdt_size);
+ printf(" kernel page end = 0x%x\n", *phys_start);
+ }
#endif
#ifdef DEBUG
if ((pmap_con_dbg & (CD_BOOT | CD_FULL)) == (CD_BOOT | CD_FULL)) {
- printf("kpdt_phys = %x\n",kpdt_phys);
- printf("kpdt_virt = %x\n",kpdt_virt);
- printf("end of kpdt at (virt)0x%08x ; (phys)0x%08x\n",
+ printf("kpdt_phys = 0x%x\n",kpdt_phys);
+ printf("kpdt_virt = 0x%x\n",kpdt_virt);
+ printf("end of kpdt at (virt)0x%08x, (phys)0x%08x\n",
*virt_start,*phys_start);
}
#endif
@@ -1017,7 +1038,7 @@ pmap_bootstrap(vm_offset_t load_start,
* init the kpdt queue
*/
kpdt_free = kpdt_virt;
- for (i = MAX_KERNEL_PDT_SIZE/PDT_SIZE; i > 0; i--) {
+ for (i = pdt_size/PDT_SIZE; i > 0; i--) {
kpdt_virt->next = (kpdt_entry_t)((vm_offset_t)kpdt_virt + PDT_SIZE);
kpdt_virt->phys = kpdt_phys;
kpdt_virt = kpdt_virt->next;
@@ -1042,15 +1063,24 @@ pmap_bootstrap(vm_offset_t load_start,
#endif
/* map the first 64k (BUG ROM) read only, cache inhibited (? XXX) */
- vaddr = PMAPER(0, 0, 0x10000, VM_PROT_WRITE | VM_PROT_READ, CACHE_INH);
+ vaddr = PMAPER(0,
+ 0,
+ 0x10000,
+ VM_PROT_WRITE | VM_PROT_READ,
+ CACHE_INH);
/* map the kernel text read only */
vaddr = PMAPER((vm_offset_t)trunc_page(((unsigned)&kernelstart)),
- s_text, e_text,
- VM_PROT_WRITE | VM_PROT_READ, CACHE_GLOBAL); /* shouldn't it be RO? XXX*/
-
- vaddr = PMAPER(vaddr, e_text, (vm_offset_t)kmap,
- VM_PROT_WRITE | VM_PROT_READ, CACHE_GLOBAL);
+ s_text,
+ e_text,
+ VM_PROT_WRITE | VM_PROT_READ,
+ CACHE_GLOBAL); /* shouldn't it be RO? XXX*/
+
+ vaddr = PMAPER(vaddr,
+ e_text,
+ (vm_offset_t)kmap,
+ VM_PROT_WRITE | VM_PROT_READ,
+ CACHE_GLOBAL);
/*
* Map system segment & page tables - should be cache inhibited?
* 88200 manual says that CI bit is driven on the Mbus while accessing
@@ -1070,9 +1100,14 @@ pmap_bootstrap(vm_offset_t load_start,
VM_PROT_WRITE | VM_PROT_READ, CACHE_INH);
if (vaddr != *virt_start) {
+ /*
+ * This should never happen because we now round the PDT
+ * table size up to a page boundry in the quest to get
+ * mc88110 working. - XXX smurph
+ */
#ifdef DEBUG
if ((pmap_con_dbg & (CD_BOOT | CD_FULL)) == (CD_BOOT | CD_FULL)) {
- printf("1:vaddr %x *virt_start %x *phys_start %x\n", vaddr,
+ printf("1:vaddr %x *virt_start 0x%x *phys_start 0x%x\n", vaddr,
*virt_start, *phys_start);
}
#endif
@@ -1087,7 +1122,7 @@ pmap_bootstrap(vm_offset_t load_start,
* used by the 1x7 ethernet driver. Remove this when that is fixed.
* XXX -nivas
*/
- if (cputyp != CPU_188) { /* != CPU_188 */
+ if (brdtyp != BRD_188) { /* != BRD_188 */
*phys_start = vaddr;
etherlen = ETHERPAGES * NBPG;
etherbuf = (void *)vaddr;
@@ -1147,7 +1182,7 @@ pmap_bootstrap(vm_offset_t load_start,
}
#endif
- for (; ptable->size != 0xffffffffU; ptable++)
+ for (; ptable->size != 0xffffffffU; ptable++){
if (ptable->size) {
/*
* size-1, 'cause pmap_map rounds up to next pagenumber
@@ -1157,15 +1192,15 @@ pmap_bootstrap(vm_offset_t load_start,
ptable->phys_start + (ptable->size - 1),
ptable->prot, ptable->cacheability);
}
-
- /*
- * Allocate all the submaps we need. Note that SYSMAP just allocates
- * kernel virtual address with no physical backing memory. The idea
- * is physical memory will be mapped at this va before using that va.
- * This means that if different physical pages are going to be mapped
- * at different times, we better do a tlb flush before using it -
- * else we will be referencing the wrong page.
- */
+ }
+ /*
+ * Allocate all the submaps we need. Note that SYSMAP just allocates
+ * kernel virtual address with no physical backing memory. The idea
+ * is physical memory will be mapped at this va before using that va.
+ * This means that if different physical pages are going to be mapped
+ * at different times, we better do a tlb flush before using it -
+ * else we will be referencing the wrong page.
+ */
#define SYSMAP(c, p, v, n) \
({ \
@@ -1184,7 +1219,7 @@ pmap_bootstrap(vm_offset_t load_start,
SYSMAP(struct msgbuf *, msgbufmap, msgbufp, btoc(MSGBUFSIZE));
*virt_start = virt;
-
+
/*
* Set translation for UPAGES at UADDR. The idea is we want to
* have translations set up for UADDR. Later on, the ptes for
@@ -1202,7 +1237,6 @@ pmap_bootstrap(vm_offset_t load_start,
if ((pte = pmap_pte(kernel_pmap, virt)) == PT_ENTRY_NULL)
pmap_expand_kmap(virt, VM_PROT_READ|VM_PROT_WRITE|(CACHE_GLOBAL << 16));
}
-
/*
* Switch to using new page tables
*/
@@ -1210,7 +1244,7 @@ pmap_bootstrap(vm_offset_t load_start,
apr_data.bits = 0;
apr_data.field.st_base = atop(kernel_pmap->sdt_paddr);
apr_data.field.wt = 1;
- apr_data.field.g = 1;
+ apr_data.field.g = 0;
apr_data.field.ci = 0;
apr_data.field.te = 1; /* Translation enable */
#ifdef DEBUG
@@ -1229,11 +1263,6 @@ pmap_bootstrap(vm_offset_t load_start,
if (cpu_sets[i]) {
/* Invalidate entire kernel TLB. */
cmmu_flush_remote_tlb(i, 1, 0, -1);
-#ifdef DEBUG
- if ((pmap_con_dbg & (CD_BOOT | CD_FULL)) == (CD_BOOT | CD_FULL)) {
- printf("After cmmu_flush_remote_tlb()\n");
- }
-#endif
/* still physical */
/*
* Set valid bit to DT_INVALID so that the very first
@@ -1250,7 +1279,7 @@ pmap_bootstrap(vm_offset_t load_start,
cmmu_remote_set_sapr(i, apr_data.bits);
#ifdef DEBUG
if ((pmap_con_dbg & (CD_BOOT | CD_FULL)) == (CD_BOOT | CD_FULL)) {
- printf("After cmmu_remote_set_sapr()\n");
+ printf("Processor %d running virtual.\n", i);
}
#endif
SETBIT_CPUSET(i, &kernel_pmap->cpus_using);
@@ -1420,7 +1449,7 @@ pmap_zero_page(vm_offset_t phys)
srcpte = pmap_pte(kernel_pmap, srcva);
template.bits = trunc_page(phys)
- | m88k_protection(VM_PROT_READ | VM_PROT_WRITE)
+ | m88k_protection(kernel_pmap, VM_PROT_READ | VM_PROT_WRITE)
| DT_VALID | CACHE_GLOBAL;
SPLVM(spl);
@@ -1479,10 +1508,9 @@ pmap_pinit(pmap_t p)
}
#endif
- segdt = (sdt_entry_t *)uvm_km_zalloc(kernel_map, s);
+ segdt = (sdt_entry_t *)uvm_km_zalloc(kernel_map, s);
if (segdt == NULL)
- panic("pmap_create: kmem_alloc failure");
-
+ panic("pmap_create: kmem_alloc failure");
/*
* Initialize pointer to segment table both virtual and physical.
@@ -1502,7 +1530,7 @@ pmap_pinit(pmap_t p)
#endif
#ifdef MVME188
- if (cputyp == CPU_188) {
+ if (brdtyp == BRD_188) {
/*
* memory for page tables should be CACHE DISABLED on MVME188
*/
@@ -2277,7 +2305,7 @@ pmap_protect(pmap_t pmap, vm_offset_t s, vm_offset_t e, vm_prot_t prot)
panic("pmap_protect: start grater than end address");
#endif
- maprot.bits = m88k_protection(prot);
+ maprot.bits = m88k_protection(pmap, prot);
ap = maprot.pte.prot;
PMAP_LOCK(pmap, spl);
@@ -2405,7 +2433,7 @@ pmap_expand(pmap_t map, vm_offset_t v)
pmap_extract(kernel_pmap, pdt_vaddr, &pdt_paddr);
#ifdef MVME188
- if (cputyp == CPU_188) {
+ if (brdtyp == BRD_188) {
/*
* the page for page tables should be CACHE DISABLED on MVME188
*/
@@ -2554,7 +2582,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_offset_t pa,
printf("(pmap_enter :%x) pmap %x va %x pa %x\n", curproc, pmap, va, pa);
}
#endif
- ap = m88k_protection(prot);
+ ap = m88k_protection(pmap, prot);
/*
* Must allocate a new pvlist entry while we're unlocked;
@@ -3003,9 +3031,9 @@ pmap_collect(pmap_t pmap)
/*
* we can safely deallocated the page map(s)
*/
- for (sdt = sdtp; sdt < (sdtp + PDT_TABLE_GROUP_SIZE); sdt++) {
- ((sdt_entry_template_t *) sdt) -> bits = 0;
- ((sdt_entry_template_t *) sdt+SDT_ENTRIES) -> bits = 0;
+ for (sdt = sdtp; sdt < (sdtp+PDT_TABLE_GROUP_SIZE); sdt++) {
+ ((sdt_entry_template_t *) sdt)->bits = 0;
+ ((sdt_entry_template_t *)(sdt+SDT_ENTRIES))->bits = 0;
}
/*
@@ -3768,32 +3796,32 @@ cache_flush_loop(int mode, vm_offset_t pa, int size)
case FLUSH_CACHE: /* All caches, all CPUs */
ncpus = max_cpus;
- cfunc = cmmu_flush_remote_cache;
+ cfunc = cmmu->cmmu_flush_remote_cache_func;
break;
case FLUSH_CODE_CACHE: /* Instruction caches, all CPUs */
ncpus = max_cpus;
- cfunc = cmmu_flush_remote_inst_cache;
+ cfunc = cmmu->cmmu_flush_remote_inst_cache_func;
break;
case FLUSH_DATA_CACHE: /* Data caches, all CPUs */
ncpus = max_cpus;
- cfunc = cmmu_flush_remote_data_cache;
+ cfunc = cmmu->cmmu_flush_remote_data_cache_func;
break;
case FLUSH_LOCAL_CACHE: /* Both caches, my CPU */
ncpus = 1;
- cfunc = cmmu_flush_remote_cache;
+ cfunc = cmmu->cmmu_flush_remote_cache_func;
break;
case FLUSH_LOCAL_CODE_CACHE: /* Instruction cache, my CPU */
ncpus = 1;
- cfunc = cmmu_flush_remote_inst_cache;
+ cfunc = cmmu->cmmu_flush_remote_inst_cache_func;
break;
case FLUSH_LOCAL_DATA_CACHE: /* Data cache, my CPU */
ncpus = 1;
- cfunc = cmmu_flush_remote_data_cache;
+ cfunc = cmmu->cmmu_flush_remote_data_cache_func;
break;
}
@@ -4351,7 +4379,7 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot)
PMAP_LOCK(kernel_pmap, spl);
users = kernel_pmap->cpus_using;
- ap = m88k_protection(prot);
+ ap = m88k_protection(kernel_pmap, prot);
/*
* Expand pmap to include this pte.
diff --git a/sys/arch/mvme88k/mvme88k/pmap_table.c b/sys/arch/mvme88k/mvme88k/pmap_table.c
index 1a1c79f1c03..a1b9555574d 100644
--- a/sys/arch/mvme88k/mvme88k/pmap_table.c
+++ b/sys/arch/mvme88k/mvme88k/pmap_table.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap_table.c,v 1.9 2001/11/06 19:53:15 miod Exp $ */
+/* $OpenBSD: pmap_table.c,v 1.10 2001/12/13 08:55:52 smurph Exp $ */
/*
* Mach Operating System
@@ -31,7 +31,7 @@
#include <sys/types.h>
#include <machine/board.h>
#include <sys/param.h>
-#include <machine/m882xx.h> /* CMMU stuff */
+#include <machine/cmmu.h> /* CMMU stuff */
#include <uvm/uvm_extern.h>
#include <machine/pmap_table.h> /* pmap_table.h*/
@@ -63,7 +63,6 @@ static pmap_table_entry m188_board_table[] = {
#ifdef MVME197
static pmap_table_entry m197_board_table[] = {
{ BUGROM_START, BUGROM_START, BUGROM_SIZE, RW, CI},
- { SRAM_START , SRAM_START , SRAM_SIZE , RW, CG},
{ OBIO_START , OBIO_START , OBIO_SIZE , RW, CI},
{ 0 , 0 , 0xffffffff , 0 , 0},
};
@@ -76,19 +75,19 @@ pmap_table_build(endoftext)
unsigned int i;
pmap_table_t bt, pbt;
- switch (cputyp) {
+ switch (brdtyp) {
#ifdef MVME187
- case CPU_187:
+ case BRD_187:
bt = m187_board_table;
break;
#endif
#ifdef MVME188
- case CPU_188:
+ case BRD_188:
bt = m188_board_table;
break;
#endif
#ifdef MVME197
- case CPU_197:
+ case BRD_197:
bt = m197_board_table;
break;
#endif
diff --git a/sys/arch/mvme88k/mvme88k/process.S b/sys/arch/mvme88k/mvme88k/process.S
index fba27137d36..03c4e35b83c 100644
--- a/sys/arch/mvme88k/mvme88k/process.S
+++ b/sys/arch/mvme88k/mvme88k/process.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: process.S,v 1.12 2001/11/18 01:43:33 miod Exp $ */
+/* $OpenBSD: process.S,v 1.13 2001/12/13 08:55:52 smurph Exp $ */
/*
* Copyright (c) 1996 Nivas Madhur
* All rights reserved.
@@ -247,7 +247,7 @@ Lsw2:
or r2, r0, r9 /* r2 = p */
or r14, r0, r9 /* save p in r14 */
subu r31, r31,48
- /* r2 = pmap, r3 = pcb, r4 = cpu number */
+ /* r2 = (proc *p) */
bsr _pmap_activate /* _pmap_activate(proc *p)*/
addu r31, r31,48
or r9, r0, r14 /* restore p saved in r14 */
@@ -259,16 +259,18 @@ Lswnochg:
bsr.n _load_u_area /* load_u_area(p) */
or r2, r0, r9
addu r31, r31,48
- /* flush tlb of any user addresses */
- or r2, r0, 0 /* 0 = user space */
+
+ /* flush tlb of any user addresses */
+ or r2, r0, 0 /* 0 = user space */
or r3, r0, 0 /* start at addr 0 */
subu r31, r31,48
/* r2 = 1 : kernel ? user, r3 = address, r4 = size */
/* cmmu_flush_tlb(0, 0, 0xffff) */
- bsr.n _cmmu_flush_tlb
+ bsr.n _md_cmmu_flush_tlb
or r4, r0, 0xffff /* cmmu_flush_tlb flushes entire tlb */
/* for sizes > 4096 */
addu r31, r31,48
+
or.u r10, r0, hi16(_curpcb)
ld r10, r10, lo16(_curpcb)
/* XXX Is this correct/necessary? */
diff --git a/sys/arch/mvme88k/mvme88k/trap.c b/sys/arch/mvme88k/mvme88k/trap.c
index 0aac5bca96e..37120c846aa 100644
--- a/sys/arch/mvme88k/mvme88k/trap.c
+++ b/sys/arch/mvme88k/mvme88k/trap.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: trap.c,v 1.27 2001/11/28 16:13:29 art Exp $ */
+/* $OpenBSD: trap.c,v 1.28 2001/12/13 08:55:52 smurph Exp $ */
/*
* Copyright (c) 1998 Steve Murphree, Jr.
* Copyright (c) 1996 Nivas Madhur
@@ -57,11 +57,14 @@
#include <machine/asm_macro.h> /* enable/disable interrupts */
#include <machine/bugio.h> /* bugreturn() */
-#include <machine/cpu.h> /* DMT_VALID, etc. */
+#include <machine/cpu.h>
+#include <machine/asm_macro.h> /* enable/disable interrupts */
#include <machine/locore.h>
-#include <machine/m88100.h> /* DMT_VALID, etc. */
-#ifdef MVME197
-#include <machine/m88110.h> /* DMT_VALID, etc. */
+#ifdef M88100
+#include <machine/m88100.h>
+#endif
+#ifdef M88110
+#include <machine/m88110.h>
#endif
#include <machine/pcb.h> /* FIP_E, etc. */
#include <machine/psl.h> /* FIP_E, etc. */
@@ -71,10 +74,12 @@
#include <machine/db_machdep.h>
#include <ddb/db_output.h> /* db_printf() */
#else
-#define PC_REGS(regs) ((regs->sxip & 2) ? regs->sxip & ~3 : \
- (regs->snip & 2 ? regs->snip & ~3 : regs->sfip & ~3))
-#define inst_return(I) (((I)&0xfffffbffU) == 0xf400c001U ? TRUE : FALSE)
-#define inst_call(I) ({ unsigned i = (I); \
+ #define PC_REGS(regs) cputyp == CPU_88110 ? (regs->exip & ~3) :\
+ ((regs->sxip & 2) ? regs->sxip & ~3 : \
+ (regs->snip & 2 ? regs->snip & ~3 : regs->sfip & ~3))
+
+ #define inst_return(I) (((I)&0xfffffbffU) == 0xf400c001U ? TRUE : FALSE)
+ #define inst_call(I) ({ unsigned i = (I); \
((((i) & 0xf8000000U) == 0xc8000000U || /*bsr*/ \
((i) & 0xfffffbe0U) == 0xf400c800U) /*jsr*/ \
? TRUE : FALSE) \
@@ -101,6 +106,9 @@ unsigned traptrace = 0;
extern int procfs_domem __P((struct proc *, struct proc *, void *, struct uio *));
extern void regdump __P((struct trapframe *f));
+void error_fatal __P((struct m88100_saved_state *frame));
+void error_fault __P((struct m88100_saved_state *frame));
+void error_reset __P((struct m88100_saved_state *frame));
char *trap_type[] = {
"Reset",
@@ -162,16 +170,18 @@ panictrap(int type, struct m88100_saved_state *frame)
static int panicing = 0;
if (panicing++ == 0) {
- if (type == 2) { /* instruction exception */
- DEBUG_MSG("\nInstr access fault (%s) v = %x, frame %x\n",
- pbus_exception_type[(frame->ipfsr >> 16) & 0x7],
- frame->sxip & ~3, frame);
- } else if (type == 3) { /* data access exception */
- DEBUG_MSG("\nData access fault (%s) v = %x, frame %x\n",
- pbus_exception_type[(frame->dpfsr >> 16) & 0x7],
- frame->sxip & ~3, frame);
- } else
- DEBUG_MSG("\ntrap type %d, v = %x, frame %x\n", type, frame->sxip & ~3, frame);
+ if (cputyp != CPU_88110) {
+ if (type == 2) { /* instruction exception */
+ DEBUG_MSG("\nInstr access fault (%s) v = %x, frame %x\n",
+ pbus_exception_type[(frame->ipfsr >> 16) & 0x7],
+ frame->sxip & ~3, frame);
+ } else if (type == 3) { /* data access exception */
+ DEBUG_MSG("\nData access fault (%s) v = %x, frame %x\n",
+ pbus_exception_type[(frame->dpfsr >> 16) & 0x7],
+ frame->sxip & ~3, frame);
+ } else
+ DEBUG_MSG("\ntrap type %d, v = %x, frame %x\n", type, frame->sxip & ~3, frame);
+ }
regdump(frame);
}
if ((u_int)type < trap_types)
@@ -180,13 +190,13 @@ panictrap(int type, struct m88100_saved_state *frame)
/*NOTREACHED*/
}
-#if defined(MVME187) || defined(MVME188)
+#ifdef M88100
unsigned last_trap[4] = {0,0,0,0};
unsigned last_vector = 0;
/*ARGSUSED*/
void
-trap18x(unsigned type, struct m88100_saved_state *frame)
+m88100_trap(unsigned type, struct m88100_saved_state *frame)
{
struct proc *p;
u_quad_t sticks = 0;
@@ -198,7 +208,7 @@ trap18x(unsigned type, struct m88100_saved_state *frame)
unsigned nss, fault_addr;
struct vmspace *vm;
union sigval sv;
- int result;
+ int result = 0;
int sig = 0;
unsigned pc = PC_REGS(frame); /* get program counter (sxip) */
@@ -270,8 +280,8 @@ trap18x(unsigned type, struct m88100_saved_state *frame)
case T_INT+T_USER:
/* This function pointer is set in machdep.c
It calls m188_ext_int or sbc_ext_int depending
- on the value of cputyp - smurph */
- (*mdfp.interrupt_func)(T_INT, frame);
+ on the value of brdtyp - smurph */
+ (*md.interrupt_func)(T_INT, frame);
return;
case T_MISALGNFLT:
@@ -351,7 +361,7 @@ trap18x(unsigned type, struct m88100_saved_state *frame)
(frame->sxip & ~3) >= (unsigned)&guarded_access_start &&
(frame->sxip & ~3) <= (unsigned)&guarded_access_end) {
- frame->snip = ((unsigned)&guarded_access_bad ) | FIP_V;
+ frame->snip = ((unsigned)&guarded_access_bad ) | NIP_V;
frame->sfip = ((unsigned)&guarded_access_bad + 4) | FIP_V;
frame->sxip = 0;
/* We sort of resolved the fault ourselves because
@@ -455,7 +465,7 @@ outtahere:
/* User mode instruction access fault */
/* FALLTHRU */
case T_DATAFLT+T_USER:
- user_fault:
+user_fault:
if (type == T_INSTFLT+T_USER) {
fault_addr = frame->sxip & XIP_ADDR;
} else {
@@ -674,12 +684,13 @@ outtahere:
userret(p, frame, sticks);
}
-#endif /* defined(MVME187) || defined(MVME188) */
+#endif /* m88100 */
+unsigned v_fault = 0;
-#ifdef MVME197
+#ifdef M88110
/*ARGSUSED*/
void
-trap197(unsigned type, struct m88100_saved_state *frame)
+m88110_trap(unsigned type, struct m88100_saved_state *frame)
{
struct proc *p;
u_quad_t sticks = 0;
@@ -691,167 +702,89 @@ trap197(unsigned type, struct m88100_saved_state *frame)
unsigned nss, fault_addr;
struct vmspace *vm;
union sigval sv;
- int result;
+ int s; /* IPL */
+ int result = 0; /* Assume Success */
int sig = 0;
- unsigned pc = PC_REGS(frame); /* get program counter (sxip) */
- unsigned user = 0, write = 0, data = 0;
-
+ unsigned pc = PC_REGS(frame); /* get program counter (exip) */
+ unsigned user = 0, data = 0;
+ pt_entry_t *pte;
extern struct vm_map *kernel_map;
extern unsigned guarded_access_start;
extern unsigned guarded_access_end;
+ extern pt_entry_t *pmap_pte __P((pmap_t, vm_offset_t));
uvmexp.traps++;
if ((p = curproc) == NULL)
p = &proc0;
-
+#if 0
+ if (type != T_INT) {
+ printf("m88110_trap 0x%x ", type);
+ }
+#endif
+
if (USERMODE(frame->epsr)) {
sticks = p->p_sticks;
type += T_USER;
p->p_md.md_tf = frame; /* for ptrace/signals */
fault_type = 0;
fault_code = 0;
+ user = 1;
}
- printf("m197_trap 0x%x ", type);
+
switch (type) {
default:
panictrap(frame->vector, frame);
/*NOTREACHED*/
case T_197_READ+T_USER:
- user = 1;
case T_197_READ:
- va = (vm_offset_t) frame->dlar;
- /* if it was a user read, handle in context of the user */
- if ((frame->dsr & CMMU_DSR_SU) && !user) {
- map = kernel_map;
- } else {
- vm = p->p_vmspace;
- map = &vm->vm_map;
- }
- result = m197_table_search(map->pmap, va, CMMU_READ, user, CMMU_DATA);
- if (result) {
- switch (result) {
- case 4: /* Seg Fault */
- frame->dsr |= CMMU_DSR_SI | CMMU_DSR_RW;
- break;
- case 5: /* Page Fault */
- frame->dsr |= CMMU_DSR_PI | CMMU_DSR_RW;
- break;
- case 6: /* Supervisor Violation */
- frame->dsr |= CMMU_DSR_SP | CMMU_DSR_RW;
- break;
- }
- /* table search failed and we are going to report a data fault */
- if (user) {
- type = T_DATAFLT+T_USER;
- goto m197_user_fault;
- } else {
- type = T_DATAFLT;
- goto m197_data_fault;
- }
- } else {
- return; /* PATC sucessfully loaded */
- }
- break;
+ DEBUG_MSG("DMMU read miss: Hardware Table Searches should be enabled!\n");
+ panictrap(frame->vector, frame);
+ /*NOTREACHED*/
case T_197_WRITE+T_USER:
- user = 1;
case T_197_WRITE:
- /* if it was a user read, handle in context of the user */
- if ((frame->dsr & CMMU_DSR_SU) && !user) {
- map = kernel_map;
- } else {
- vm = p->p_vmspace;
- map = &vm->vm_map;
- }
- va = (vm_offset_t) frame->dlar;
- result = m197_table_search(map->pmap, va, CMMU_WRITE, user, CMMU_DATA);
- if (result) {
- switch (result) {
- case 4: /* Seg Fault */
- frame->dsr |= CMMU_DSR_SI;
- break;
- case 5: /* Page Fault */
- frame->dsr |= CMMU_DSR_PI;
- break;
- case 6: /* Supervisor Violation */
- frame->dsr |= CMMU_DSR_SP;
- break;
- case 7: /* Write Violation */
- frame->dsr |= CMMU_DSR_WE;
- break;
- }
- /* table search failed and we are going to report a data fault */
- if (user) {
- type = T_DATAFLT+T_USER;
- goto m197_user_fault;
- } else {
- type = T_DATAFLT;
- goto m197_data_fault;
- }
- } else {
- return; /* PATC sucessfully loaded */
- }
- break;
+ DEBUG_MSG("DMMU write miss: Hardware Table Searches should be enabled!\n");
+ panictrap(frame->vector, frame);
+ /*NOTREACHED*/
case T_197_INST+T_USER:
- user = 1;
case T_197_INST:
- /* if it was a user read, handle in context of the user */
- if ((frame->isr & CMMU_ISR_SU) && !user) {
- map = kernel_map;
- } else {
- vm = p->p_vmspace;
- map = &vm->vm_map;
- }
- va = (vm_offset_t) frame->sxip;
- result = m197_table_search(map->pmap, va, CMMU_READ, user, CMMU_INST);
- if (result) {
- switch (result) {
- case 4: /* Seg Fault */
- frame->isr |= CMMU_ISR_SI;
- break;
- case 5: /* Page Fault */
- frame->isr |= CMMU_ISR_PI;
- break;
- case 6: /* Supervisor Violation */
- frame->isr |= CMMU_ISR_SP;
- break;
- }
- /* table search failed and we are going to report a data fault */
- if (user) {
- type = T_INSTFLT+T_USER;
- goto m197_user_fault;
- } else {
- type = T_INSTFLT;
- goto m197_inst_fault;
- }
- } else {
- return; /* PATC sucessfully loaded */
- }
- break;
- #if defined(DDB)
+ DEBUG_MSG("IMMU miss: Hardware Table Searches should be enabled!\n");
+ panictrap(frame->vector, frame);
+ /*NOTREACHED*/
+#if defined(DDB)
+ case T_KDB_TRACE:
+ frame->mask = spl(); /* get current spl for reg dump */
+ s = db_splhigh();
+ db_enable_interrupt();
+ ddb_break_trap(T_KDB_TRACE,(db_regs_t*)frame);
+ db_disable_interrupt();
+ db_splx(s);
+ return;
case T_KDB_BREAK:
/*FALLTHRU*/
case T_KDB_BREAK+T_USER:
- {
- int s = db_splhigh();
- db_enable_interrupt();
- ddb_break_trap(T_KDB_BREAK,(db_regs_t*)frame);
- db_disable_interrupt();
- db_splx(s);
- return;
- }
+ frame->mask = spl(); /* get current spl for reg dump */
+ s = db_splhigh();
+ db_enable_interrupt();
+ ddb_break_trap(T_KDB_BREAK,(db_regs_t*)frame);
+ db_disable_interrupt();
+ db_splx(s);
+ return;
case T_KDB_ENTRY:
/*FALLTHRU*/
case T_KDB_ENTRY+T_USER:
- {
- int s = db_splhigh();
- db_enable_interrupt();
- ddb_entry_trap(T_KDB_ENTRY,(db_regs_t*)frame);
- db_disable_interrupt();
- db_splx(s);
- return;
+ frame->mask = spl(); /* get current spl for reg dump */
+ s = db_splhigh();
+ db_enable_interrupt();
+ ddb_entry_trap(T_KDB_ENTRY,(db_regs_t*)frame);
+ db_disable_interrupt();
+ if (frame->enip) {
+ frame->exip = frame->enip;
+ } else {
+ frame->exip += 4;
}
-
+ db_splx(s);
+ return;
#if 0
case T_ILLFLT:
{
@@ -866,26 +799,33 @@ trap197(unsigned type, struct m88100_saved_state *frame)
#endif /* 0 */
#endif /* DDB */
case T_ILLFLT:
- DEBUG_MSG("test trap "
- "page fault @ 0x%08x\n", frame->sxip);
+ DEBUG_MSG("Unimplemented opcode!\n");
panictrap(frame->vector, frame);
break;
-
+ case T_NON_MASK:
+ case T_NON_MASK+T_USER:
+ /* This function pointer is set in machdep.c
+ It calls m197_ext_int - smurph */
+ (*md.interrupt_func)(T_NON_MASK, frame);
+ return;
+ case T_INT:
+ case T_INT+T_USER:
+ (*md.interrupt_func)(T_INT, frame);
+ return;
case T_MISALGNFLT:
DEBUG_MSG("kernel misaligned "
- "access exception @ 0x%08x\n", frame->sxip);
+ "access exception @ 0x%08x\n", frame->exip);
panictrap(frame->vector, frame);
- break;
+ /*NOTREACHED*/
case T_INSTFLT:
- m197_inst_fault:
/* kernel mode instruction access fault.
* Should never, never happen for a non-paged kernel.
*/
DEBUG_MSG("kernel mode instruction "
- "page fault @ 0x%08x\n", frame->sxip);
+ "page fault @ 0x%08x\n", frame->exip);
panictrap(frame->vector, frame);
- break;
+ /*NOTREACHED*/
case T_DATAFLT:
/* kernel mode data fault */
@@ -893,7 +833,6 @@ trap197(unsigned type, struct m88100_saved_state *frame)
* If the faulting address is in user space, handle it in
* the context of the user process. Else, use kernel map.
*/
- m197_data_fault:
if (type == T_DATAFLT) {
fault_addr = frame->dlar;
if (frame->dsr & CMMU_DSR_RW) {
@@ -902,19 +841,18 @@ trap197(unsigned type, struct m88100_saved_state *frame)
} else {
ftype = VM_PROT_READ|VM_PROT_WRITE;
fault_code = VM_PROT_WRITE;
- write = 1;
}
data = 1;
} else {
- fault_addr = frame->sxip & XIP_ADDR;
+ fault_addr = frame->exip & XIP_ADDR;
ftype = VM_PROT_READ;
fault_code = VM_PROT_READ;
}
-
+
va = trunc_page((vm_offset_t)fault_addr);
vm = p->p_vmspace;
map = &vm->vm_map;
-
+
/* data fault on a kernel address... */
if (type == T_DATAFLT) {
if (frame->dsr & CMMU_DSR_SU) {
@@ -933,34 +871,27 @@ trap197(unsigned type, struct m88100_saved_state *frame)
if (p->p_addr->u_pcb.pcb_onfault == (int)fubail ||
p->p_addr->u_pcb.pcb_onfault == (int)subail)
- goto m197_outtahere;
+ goto m88110_outtahere;
/* data fault on the user address */
if (type == T_DATAFLT && (frame->dsr & CMMU_DSR_SU) == 0) {
type = T_DATAFLT + T_USER;
- goto m197_user_fault;
+ goto m88110_user_fault;
}
/*
- * If it is a guarded access, bus error is OK.
+ * If it is a guarded access, bus error is OK.
*/
if ((frame->dsr & CMMU_DSR_BE) && /* bus error */
- (frame->sxip & ~3) >= (unsigned)&guarded_access_start &&
- (frame->sxip & ~3) <= (unsigned)&guarded_access_end) {
+ (frame->exip & ~3) >= (unsigned)&guarded_access_start &&
+ (frame->exip & ~3) <= (unsigned)&guarded_access_end) {
return;
}
-
/*
- * On a segment or a page fault, call vm_fault() to resolve
- * the fault.
+ * On a segment or a page fault, call vm_fault() to resolve
+ * the fault.
*/
- result = m197_table_search(map->pmap, va, write, 1, data);
-#ifdef todo
- switch (result) {
- case :
- }
-#endif
if (type == T_DATAFLT) {
if ((frame->dsr & CMMU_DSR_SI) /* seg fault */
|| (frame->dsr & CMMU_DSR_PI)) { /* page fault */
@@ -969,6 +900,25 @@ trap197(unsigned type, struct m88100_saved_state *frame)
return;
}
}
+ if (frame->dsr & CMMU_DSR_WE) { /* write fault */
+ /* This could be a write protection fault or an
+ * exception to set the used and modified bits
+ * in the pte. Basicly, if we got a write error,
+ * then we already have a pte entry that faulted
+ * in from a previous seg fault or page fault.
+ * Get the pte and check the status of the
+ * modified and valid bits to determine if this
+ * indeed a real write fault. XXX smurph
+ */
+ pte = pmap_pte(map->pmap, va);
+ if (pte == PT_ENTRY_NULL)
+ panic("NULL pte on write fault??");
+ if (!pte->modified && !pte->prot) {
+ /* Set modified bit and try the write again. */
+ pte->modified = 1;
+ return;
+ }
+ }
} else {
if ((frame->isr & CMMU_ISR_SI) /* seg fault */
|| (frame->isr & CMMU_ISR_PI)) { /* page fault */
@@ -984,16 +934,16 @@ trap197(unsigned type, struct m88100_saved_state *frame)
if (!p->p_addr->u_pcb.pcb_onfault)
panictrap(frame->vector, frame);
- m197_outtahere:
- frame->sxip = ((unsigned)p->p_addr->u_pcb.pcb_onfault);
+m88110_outtahere:
+ frame->exip = ((unsigned)p->p_addr->u_pcb.pcb_onfault);
return;
case T_INSTFLT+T_USER:
/* User mode instruction access fault */
/*FALLTHRU*/
case T_DATAFLT+T_USER:
- m197_user_fault:
+m88110_user_fault:
if (type == T_INSTFLT+T_USER) {
- fault_addr = frame->sxip & XIP_ADDR;
+ fault_addr = frame->exip & XIP_ADDR;
ftype = VM_PROT_READ;
fault_code = VM_PROT_READ;
} else {
@@ -1012,26 +962,52 @@ trap197(unsigned type, struct m88100_saved_state *frame)
vm = p->p_vmspace;
map = &vm->vm_map;
-
/* Call vm_fault() to resolve non-bus error faults */
if (type == T_DATAFLT+T_USER) {
- if ((frame->dsr & CMMU_DSR_SI) /* seg fault */
- || (frame->dsr & CMMU_DSR_PI)) { /* page fault */
+
+ if (frame->dsr & (CMMU_DSR_SI | /* seg fault */
+ CMMU_DSR_PI)) { /* page fault */
result = uvm_fault(map, va, 0, ftype);
- if (result == 0) {
+ v_fault++;
+ } else if (frame->dsr & CMMU_DSR_BE) { /* bus error */
+ result = EFAULT;
+ } else if ((frame->dsr & CMMU_DSR_CP)
+ || (frame->dsr & CMMU_DSR_WA)) {
+ result = 0;
+ } else if (frame->dsr & CMMU_DSR_WE) { /* write fault */
+ /* This could be a write protection fault or an
+ * exception to set the used and modified bits
+ * in the pte. Basicly, if we got a write error,
+ * then we already have a pte entry that faulted
+ * in from a previous seg fault or page fault.
+ * Get the pte and check the status of the
+ * modified and valid bits to determine if this
+ * indeed a real write fault. XXX smurph
+ */
+ pte = pmap_pte(map->pmap, va);
+ if (pte == PT_ENTRY_NULL)
+ panic("NULL pte on write fault??");
+ if (!pte->modified && !pte->prot) {
+ /* Set modified bit and try the write again. */
+ pte->modified = 1;
return;
+ } else {
+ /* This must be a real write protection fault */
+ result = uvm_fault(map, va, 0, ftype);
}
}
} else {
- if ((frame->isr & CMMU_ISR_SI) /* seg fault */
+ if ((frame->isr & CMMU_ISR_SI) /* seg fault */
|| (frame->isr & CMMU_ISR_PI)) { /* page fault */
result = uvm_fault(map, va, 0, ftype);
- if (result == 0) {
- return;
- }
+ v_fault++;
+ } else if ((frame->isr & CMMU_ISR_BE)
+ || (frame->isr & CMMU_ISR_SP)
+ || (frame->isr & CMMU_ISR_TBE)) { /* bus error */
+ result = EACCES;
}
}
-
+
if ((caddr_t)va >= vm->vm_maxsaddr) {
if (result == 0) {
nss = btoc(USRSTACK - va);/* XXX check this */
@@ -1042,11 +1018,14 @@ trap197(unsigned type, struct m88100_saved_state *frame)
}
if (result != 0) {
+#ifdef DEBUG
+ printf("Access failed! result = %d\n");
+ frame->mode = v_fault;
+ regdump(frame);
+ Debugger();
+#endif
sig = result == EACCES ? SIGBUS : SIGSEGV;
- fault_type = result == EACCES ? BUS_ADRERR
- : SEGV_MAPERR;
- } else {
- return;
+ fault_type = result == EACCES ? BUS_ADRERR : SEGV_MAPERR;
}
break;
case T_MISALGNFLT+T_USER:
@@ -1135,9 +1114,6 @@ trap197(unsigned type, struct m88100_saved_state *frame)
uio.uio_procp = curproc;
}
- frame->sfip = frame->snip; /* set up next FIP */
- frame->snip = frame->sxip; /* set up next NIP */
- frame->snip |= 2; /* set valid bit */
p->p_md.md_ss_addr = 0;
sig = SIGTRAP;
fault_type = TRAP_BRKPT;
@@ -1149,8 +1125,6 @@ trap197(unsigned type, struct m88100_saved_state *frame)
* breakpoint debugging. When we get this trap, we just
* return a signal which gets caught by the debugger.
*/
- frame->sfip = frame->snip; /* set up the next FIP */
- frame->snip = frame->sxip; /* set up the next NIP */
sig = SIGTRAP;
fault_type = TRAP_BRKPT;
break;
@@ -1178,6 +1152,7 @@ trap197(unsigned type, struct m88100_saved_state *frame)
* deliver signal.
*/
frame->dsr = 0;
+ frame->isr = 0;
}
userret(p, frame, sticks);
}
@@ -1193,6 +1168,32 @@ test_trap(struct m88100_saved_state *frame)
}
void
+error_fatal(struct m88100_saved_state *frame)
+{
+ switch (frame->vector) {
+ case 0:
+ DEBUG_MSG("\n[RESET EXCEPTION (Really Bad News[tm]) frame 0x%08x]\n", frame);
+ DEBUG_MSG("This is usually caused by a branch to a NULL function pointer.\n");
+ DEBUG_MSG("e.g. jump to address 0. Use the debugger trace command to track it down.\n");
+ break;
+ default:
+ DEBUG_MSG("\n[ERROR EXCEPTION (Bad News[tm]) frame 0x%08x]\n", frame);
+ DEBUG_MSG("This is usually an exception within an exception. The trap\n");
+ DEBUG_MSG("frame shadow registers you are about to see are invalid.\n");
+ DEBUG_MSG("(read totaly useless) But R1 to R31 might be interesting.\n");
+ break;
+ }
+ regdump((struct trapframe*)frame);
+#if DDB
+ Debugger();
+ DEBUG_MSG("You really can't restart after exception %d!\n", frame->vector);
+ Debugger();
+#endif /* DDB */
+ bugreturn(); /* This gets us to Bug instead of a loop forever */
+
+}
+
+void
error_fault(struct m88100_saved_state *frame)
{
DEBUG_MSG("\n[ERROR EXCEPTION (Bad News[tm]) frame 0x%08x]\n", frame);
@@ -1200,7 +1201,7 @@ error_fault(struct m88100_saved_state *frame)
DEBUG_MSG("frame shadow registers you are about to see are invalid.\n");
DEBUG_MSG("(read totaly useless) But R1 to R31 might be interesting.\n");
regdump((struct trapframe*)frame);
-#if defined(MVME187) || defined(MVME188)
+#ifdef M88100
DEBUG_MSG("trap trace %d -> %d -> %d -> %d ", last_trap[0], last_trap[1], last_trap[2], last_trap[3]);
DEBUG_MSG("last exception vector = %d\n", last_vector);
#endif
@@ -1226,8 +1227,9 @@ error_reset(struct m88100_saved_state *frame)
bugreturn(); /* This gets us to Bug instead of a loop forever */
}
+#ifdef M88100
void
-syscall(register_t code, struct m88100_saved_state *tf)
+m88100_syscall(register_t code, struct m88100_saved_state *tf)
{
register int i, nsys, *ap, nap;
register struct sysent *callp;
@@ -1313,9 +1315,9 @@ syscall(register_t code, struct m88100_saved_state *tf)
* ld r11, r31, 36
* ld r12, r31, 40
* or r13, r0, <code>
- * tb0 0, r0, <128> <- xip
- * br err <- nip
- * jmp r1 <- fip
+ * tb0 0, r0, <128> <- sxip
+ * br err <- snip
+ * jmp r1 <- sfip
* err: or.u r3, r0, hi16(errno)
* st r2, r3, lo16(errno)
* subu r2, r0, 1
@@ -1352,7 +1354,7 @@ syscall(register_t code, struct m88100_saved_state *tf)
tf->r[2] = rval[0];
tf->r[3] = rval[1];
tf->epsr &= ~PSR_C;
- tf->snip = tf->sfip & ~FIP_E;
+ tf->snip = tf->sfip & ~NIP_E;
tf->sfip = tf->snip + 4;
} else if (error > 0) {
/* error != ERESTART && error != EJUSTRETURN*/
@@ -1366,7 +1368,7 @@ syscall(register_t code, struct m88100_saved_state *tf)
* will end up reexecuting the trap.
*/
tf->epsr &= ~PSR_C;
- tf->sfip = tf->snip & ~NIP_E;
+ tf->sfip = tf->snip & ~FIP_E;
tf->snip = tf->sxip & ~NIP_E;
} else {
/* if (error == EJUSTRETURN), leave the ip's alone */
@@ -1381,11 +1383,12 @@ syscall(register_t code, struct m88100_saved_state *tf)
ktrsysret(p, code, error, rval[0]);
#endif
}
+#endif /* M88100 */
-#ifdef MVME197
+#ifdef M88110
/* Instruction pointers opperate differently on mc88110 */
void
-m197_syscall(register_t code, struct m88100_saved_state *tf)
+m88110_syscall(register_t code, struct m88100_saved_state *tf)
{
register int i, nsys, *ap, nap;
register struct sysent *callp;
@@ -1471,29 +1474,30 @@ m197_syscall(register_t code, struct m88100_saved_state *tf)
* ld r11, r31, 36
* ld r12, r31, 40
* or r13, r0, <code>
- * tb0 0, r0, <128> <- sxip
- * br err <- snip
- * jmp r1
+ * tb0 0, r0, <128> <- exip
+ * br err <- enip
+ * jmp r1
* err: or.u r3, r0, hi16(errno)
* st r2, r3, lo16(errno)
* subu r2, r0, 1
* jmp r1
*
- * So, when we take syscall trap, sxip/snip will be as
+ * So, when we take syscall trap, exip/enip will be as
* shown above.
* Given this,
* 1. If the system call returned 0, need to jmp r1.
- * sxip += 8
+ * exip += 8
* 2. If the system call returned an errno > 0, increment
- * sxip += 4 and plug the value in r2. This will have us
+ * exip += 4 and plug the value in r2. This will have us
* executing "br err" on return to user space.
* 3. If the system call code returned ERESTART,
- * we need to rexecute the trap instruction. leave xip as is.
+ * we need to rexecute the trap instruction. leave exip as is.
* 4. If the system call returned EJUSTRETURN, just return.
- * sxip += 8
+ * exip += 4
*/
if (error == 0) {
+ printf("syscall success!\n");
/*
* If fork succeeded and we are the child, our stack
* has moved and the pointer tf is no longer valid,
@@ -1506,25 +1510,27 @@ m197_syscall(register_t code, struct m88100_saved_state *tf)
tf->r[2] = rval[0];
tf->r[3] = rval[1];
tf->epsr &= ~PSR_C;
- tf->sxip += 8;
- tf->sxip &= ~3;
+ tf->exip += 8;
+ tf->exip &= ~3;
} else if (error > 0) {
+ printf("syscall error %d!\n", error);
/* error != ERESTART && error != EJUSTRETURN*/
tf->r[2] = error;
tf->epsr |= PSR_C; /* fail */
- tf->sxip += 4;
- tf->sxip &= ~3;
+ tf->exip += 4;
+ tf->exip &= ~3;
} else if (error == ERESTART) {
+ printf("syscall restart!\n");
/*
- * If (error == ERESTART), back up the pipe line. This
- * will end up reexecuting the trap.
+ * If (error == ERESTART), reexecute the trap.
*/
- tf->epsr &= ~PSR_C;
+ tf->epsr &= ~PSR_C;
} else {
+ printf("syscall just return!\n");
/* if (error == EJUSTRETURN) */
tf->epsr &= ~PSR_C;
- tf->sxip += 8;
- tf->sxip &= ~3;
+ tf->exip += 4;
+ tf->exip &= ~3;
}
#ifdef SYSCALL_DEBUG
scdebug_ret(p, code, error, rval);
@@ -1552,15 +1558,12 @@ child_return(arg)
tf->r[2] = 0;
tf->r[3] = 0;
tf->epsr &= ~PSR_C;
-#ifdef MVME197
- if (cputyp == CPU_197) {
- tf->sxip += 8;
- tf->sxip &= ~3;
- } else
-#endif
- {
+ if (cputyp != CPU_88110) {
tf->snip = tf->sfip & ~3;
tf->sfip = tf->snip + 4;
+ } else {
+ tf->exip += 8;
+ tf->exip &= ~3;
}
userret(p, tf, p->p_sticks);
diff --git a/sys/arch/mvme88k/mvme88k/vm_machdep.c b/sys/arch/mvme88k/mvme88k/vm_machdep.c
index 682d657c21a..f33bfe1bccd 100644
--- a/sys/arch/mvme88k/mvme88k/vm_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/vm_machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: vm_machdep.c,v 1.41 2001/12/08 02:24:06 art Exp $ */
+/* $OpenBSD: vm_machdep.c,v 1.42 2001/12/13 08:55:52 smurph Exp $ */
/*
* Copyright (c) 1998 Steve Murphree, Jr.
@@ -434,7 +434,6 @@ int
badvaddr(vm_offset_t va, int size)
{
register int x;
-
if (badaddr(va, size)) {
return -1;
}
@@ -449,8 +448,10 @@ badvaddr(vm_offset_t va, int size)
case 4:
x = *(volatile unsigned long *)va;
break;
+ default:
+ return -1;
}
- return(x);
+ return(0);
}
int
diff --git a/sys/arch/mvme88k/stand/bugcrt/bugcrt.c b/sys/arch/mvme88k/stand/bugcrt/bugcrt.c
index 667ae0596d1..1fc418c6224 100644
--- a/sys/arch/mvme88k/stand/bugcrt/bugcrt.c
+++ b/sys/arch/mvme88k/stand/bugcrt/bugcrt.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: bugcrt.c,v 1.6 2001/01/13 05:19:01 smurph Exp $ */
+/* $OpenBSD: bugcrt.c,v 1.7 2001/12/13 08:55:52 smurph Exp $ */
/*
* This is the startup file for single stage bootstraps or the first
@@ -36,6 +36,8 @@ start()
asm("| enable SFU1");
asm(" ldcr r25,cr1");
asm(" xor r25,r25,0x8");
+ asm(" set r25,r25,1<25>"); /* bit 25 is Serialize */
+ asm(" set r25,r25,1<29>"); /* bit 29 is Serial mode execution */
asm(" stcr r25,cr1");
#endif
diff --git a/sys/arch/mvme88k/stand/bugcrt/crt.c b/sys/arch/mvme88k/stand/bugcrt/crt.c
index 7776e42b364..e24b5597a96 100644
--- a/sys/arch/mvme88k/stand/bugcrt/crt.c
+++ b/sys/arch/mvme88k/stand/bugcrt/crt.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: crt.c,v 1.2 2001/02/01 03:38:23 smurph Exp $ */
+/* $OpenBSD: crt.c,v 1.3 2001/12/13 08:55:52 smurph Exp $ */
#include <sys/types.h>
#include <machine/prom.h>
@@ -33,6 +33,8 @@ start()
asm("| enable SFU1");
asm(" ldcr r25,cr1");
asm(" clr r25,r25,1<3>"); /* bit 3 is SFU1D */
+ asm(" set r25,r25,1<25>"); /* bit 25 is Serialize */
+ asm(" set r25,r25,1<29>"); /* bit 29 is Serial mode execution */
asm(" stcr r25,cr1");
bugargs.dev_lun = dev_lun;