Quote a few errata to explain why odd things are done in oddly ways on 88110.

3 files changed, 42 insertions, 6 deletions

diff --git a/sys/arch/mvme88k/dev/busswreg.h b/sys/arch/mvme88k/dev/busswreg.h
index b88f10d5c15..15a31df42ca 100644
--- a/sys/arch/mvme88k/dev/busswreg.h
+++ b/sys/arch/mvme88k/dev/busswreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: busswreg.h,v 1.7 2005/12/11 21:31:36 miod Exp $ */
+/*	$OpenBSD: busswreg.h,v 1.8 2007/11/22 05:53:57 miod Exp $ */
 
 /*
  * Memory map for BusSwitch chip found in mvme197 boards.
@@ -60,8 +60,8 @@
 #define	BS_TCTRL2	0x0063
 #define	BS_LEVEL	0x0064
 #define	BS_MASK		0x0065
-#define	BS_ISEL0	0x0066
-#define	BS_ISEL1	0x0067
+#define	BS_ISEL0	0x0066	/* do not access on 197LE!!! */
+#define	BS_ISEL1	0x0067	/* do not access on 197LE!!! */
 #define	BS_ABORT	0x0068
 #define	BS_CPINT	0x0069
 #define	BS_TINT1	0x006a
diff --git a/sys/arch/mvme88k/include/m88110.h b/sys/arch/mvme88k/include/m88110.h
index a3edd8df00d..d04f3cc24e4 100644
--- a/sys/arch/mvme88k/include/m88110.h
+++ b/sys/arch/mvme88k/include/m88110.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.h,v 1.18 2007/11/17 05:36:23 miod Exp $ */
+/*	$OpenBSD: m88110.h,v 1.19 2007/11/22 05:53:57 miod Exp $ */
 
 #ifndef	__MACHINE_M88110_H__
 #define	__MACHINE_M88110_H__
@@ -173,6 +173,17 @@ u_int get_dsr(void);
 #define line_addr(x)	(paddr_t)((x) & ~CLINE_MASK)
 #define page_addr(x)	(paddr_t)((x) & ~PAGE_MASK)
 
+/*
+ * 88110 general information #22:
+ * ``Issuing a command to flush and invalidate the data cache while the
+ *   dcache is disabled (CEN = 0 in dctl) will cause problems.  Do not
+ *   flush a disabled data cache.  In general, there is no reason to
+ *   perform this operation with the cache disabled, since it may be
+ *   incoherent with the proper state of memory.  Before 5.0 the flush
+ *   command was treated like a nop when the cache was disabled.  This
+ *   is no longer the case.''
+ */
+
 static __inline__ void mc88110_flush_data_line(paddr_t x)
 {
 	u_int dctl = get_dctl();
diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c
index a3116a62483..d6d64fdf4cd 100644
--- a/sys/arch/mvme88k/mvme88k/m88110.c
+++ b/sys/arch/mvme88k/mvme88k/m88110.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.c,v 1.42 2007/11/22 05:47:46 miod Exp $	*/
+/*	$OpenBSD: m88110.c,v 1.43 2007/11/22 05:53:57 miod Exp $	*/
 /*
  * Copyright (c) 1998 Steve Murphree, Jr.
  * All rights reserved.
@@ -193,7 +193,13 @@ m88110_initialize_cpu(cpuid_t cpu)
 	/* clear PATCs */
 	patc_clear();
 
-	/* Do NOT enable ICTL_PREN (branch prediction) */
+	/*
+	 * 88110 errata #1:
+	 * ``Under certain conditions involving exceptions, with branch
+	 *   prediction enabled, the CPU may hang.
+	 *   Suggested fix: Clear the PREN bit of the ICTL.  This will
+	 *   disable branch prediction.''
+	 */
 	set_ictl(BATC_32M
 		 | CMMU_ICTL_DID	/* Double instruction disable */
 		 | CMMU_ICTL_MEN
@@ -201,6 +207,25 @@ m88110_initialize_cpu(cpuid_t cpu)
 		 | CMMU_ICTL_BEN
 		 | CMMU_ICTL_HTEN);
 
+	/*
+	 * 88110 errata #10 (4.2) or #2 (5.1.1):
+	 * ``Under some circumstances, the 88110 may incorrectly latch data
+	 *   as it comes from the bus.
+	 *   [...]
+	 *   It is the data matching mechanism that may give corrupt data to
+	 *   the register files.
+	 *   Suggested fix: Set the Data Matching Disable bit (bit 2) of the
+	 *   DCTL.  This bit is not documented in the user's manual. This bit
+	 *   is only present for debug purposes and its functionality should
+	 *   not be depended upon long term.''
+	 *
+	 * 88110 errata #5 (5.1.1):
+	 * ``Setting the xmem bit in the dctl register to perform st/ld
+	 *   xmems can cause the cpu to hang if a st instruction follows the
+	 *   xmem.
+	 *   Work-Around: do not set the xmem bit in dctl, or separate st
+	 *   from xmem instructions.''
+	 */
 	set_dctl(BATC_32M
                  | CMMU_DCTL_RSVD1	/* Data Matching Disable */
                  | CMMU_DCTL_MEN