Rework {get,set,raise}ipl() to minimize psr modification, especially on

boards such as mvme1[89]7 where spl changes can be atomic.

4 files changed, 58 insertions, 57 deletions

diff --git a/sys/arch/mvme88k/mvme88k/m187_machdep.c b/sys/arch/mvme88k/mvme88k/m187_machdep.c
index b61990d34d9..5e3b2a4a5a6 100644
--- a/sys/arch/mvme88k/mvme88k/m187_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/m187_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m187_machdep.c,v 1.15 2007/05/14 16:59:43 miod Exp $	*/
+/*	$OpenBSD: m187_machdep.c,v 1.16 2007/11/17 05:32:05 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -205,21 +205,35 @@ m187_getipl(void)
 u_int
 m187_setipl(u_int level)
 {
-	unsigned curspl;
+	u_int curspl, psr;
 
+	psr = get_psr();
+	set_psr(psr | PSR_IND);
 	curspl = *(u_int8_t *)M187_IMASK & 0x07;
 	*(u_int8_t *)M187_IMASK = level;
+	/*
+	 * We do not flush the pipeline here, because interrupts are disabled,
+	 * and set_psr() will synchronize the pipeline.
+	 */
+	set_psr(psr);
 	return curspl;
 }
 
 u_int
 m187_raiseipl(u_int level)
 {
-	unsigned curspl;
+	u_int curspl, psr;
 
+	psr = get_psr();
+	set_psr(psr | PSR_IND);
 	curspl = *(u_int8_t *)M187_IMASK & 0x07;
 	if (curspl < level)
 		*(u_int8_t *)M187_IMASK = level;
+	/*
+	 * We do not flush the pipeline here, because interrupts are disabled,
+	 * and set_psr() will synchronize the pipeline.
+	 */
+	set_psr(psr);
 	return curspl;
 }
 
diff --git a/sys/arch/mvme88k/mvme88k/m188_machdep.c b/sys/arch/mvme88k/mvme88k/m188_machdep.c
index 04897781664..31b6bdef70d 100644
--- a/sys/arch/mvme88k/mvme88k/m188_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/m188_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m188_machdep.c,v 1.40 2007/11/14 23:14:14 miod Exp $	*/
+/*	$OpenBSD: m188_machdep.c,v 1.41 2007/11/17 05:32:05 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -159,7 +159,7 @@ void	m188_startup(void);
  */
 unsigned int int_mask_reg[] = { 0, 0, 0, 0 };
 
-unsigned int m188_curspl[] = { IPL_NONE, IPL_NONE, IPL_NONE, IPL_NONE};
+u_int m188_curspl[] = { IPL_NONE, IPL_NONE, IPL_NONE, IPL_NONE };
 
 /*
  * external interrupt masks per spl.
@@ -256,7 +256,8 @@ m188_reset()
 }
 
 /*
- * return next safe spl to reenable interrupts.
+ * Return the next ipl >= ``curlevel'' at which we can reenable interrupts
+ * while keeping ``mask'' masked.
  */
 u_int
 safe_level(u_int mask, u_int curlevel)
@@ -306,9 +307,12 @@ m188_setipl(u_int level)
 		mask |= SWI_CLOCK_IPI_MASK(cpu);
 #endif
 
-	*(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask;
 	m188_curspl[cpu] = level;
-
+	*(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask;
+	/*
+	 * We do not flush the pipeline here, because interrupts are disabled,
+	 * and set_psr() will synchronize the pipeline.
+	 */
 	set_psr(psr);
 
 	return curspl;
@@ -339,10 +343,13 @@ m188_raiseipl(u_int level)
 			mask |= SWI_CLOCK_IPI_MASK(cpu);
 #endif
 
-		*(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask;
 		m188_curspl[cpu] = level;
+		*(u_int32_t *)MVME188_IEN(cpu) = int_mask_reg[cpu] = mask;
 	}
-
+	/*
+	 * We do not flush the pipeline here, because interrupts are disabled,
+	 * and set_psr() will synchronize the pipeline.
+	 */
 	set_psr(psr);
 
 	return curspl;
@@ -484,7 +491,7 @@ m188_ext_int(u_int v, struct trapframe *eframe)
 	u_int cpu = cpu_number();
 #endif
 	unsigned int cur_mask, ign_mask;
-	unsigned int level, old_spl;
+	u_int level, old_spl;
 	struct intrhand *intr;
 	intrhand_t *list;
 	int ret, intbit;
diff --git a/sys/arch/mvme88k/mvme88k/m197_machdep.c b/sys/arch/mvme88k/mvme88k/m197_machdep.c
index 671b4a43eea..6a33e498703 100644
--- a/sys/arch/mvme88k/mvme88k/m197_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/m197_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m197_machdep.c,v 1.14 2007/05/14 16:59:43 miod Exp $	*/
+/*	$OpenBSD: m197_machdep.c,v 1.15 2007/11/17 05:32:05 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -246,21 +246,35 @@ m197_getipl(void)
 u_int
 m197_setipl(u_int level)
 {
-	u_int curspl;
+	u_int curspl, psr;
 
+	psr = get_psr();
+	set_psr(psr | PSR_IND);
 	curspl = *(u_int8_t *)M197_IMASK & 0x07;
 	*(u_int8_t *)M197_IMASK = level;
+	/*
+	 * We do not flush the pipeline here, because interrupts are disabled,
+	 * and set_psr() will synchronize the pipeline.
+	 */
+	set_psr(psr);
 	return curspl;
 }
 
 u_int
 m197_raiseipl(u_int level)
 {
-	u_int curspl;
+	u_int curspl, psr;
 
+	psr = get_psr();
+	set_psr(psr | PSR_IND);
 	curspl = *(u_int8_t *)M197_IMASK & 0x07;
 	if (curspl < level)
 		*(u_int8_t *)M197_IMASK = level;
+	/*
+	 * We do not flush the pipeline here, because interrupts are disabled,
+	 * and set_psr() will synchronize the pipeline.
+	 */
+	set_psr(psr);
 	return curspl;
 }
 
diff --git a/sys/arch/mvme88k/mvme88k/machdep.c b/sys/arch/mvme88k/mvme88k/machdep.c
index d364c9a94b8..cf5975048e9 100644
--- a/sys/arch/mvme88k/mvme88k/machdep.c
+++ b/sys/arch/mvme88k/mvme88k/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.201 2007/11/15 21:23:16 miod Exp $	*/
+/* $OpenBSD: machdep.c,v 1.202 2007/11/17 05:32:05 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -95,7 +95,6 @@ void	consinit(void);
 void	dumpconf(void);
 void	dumpsys(void);
 int	getcpuspeed(struct mvmeprom_brdid *);
-u_int	getipl(void);
 void	identifycpu(void);
 void	mvme_bootstrap(void);
 void	mvme88k_vector_init(u_int32_t *, u_int32_t *);
@@ -105,8 +104,6 @@ void	secondary_main(void);
 vaddr_t	secondary_pre_main(void);
 void	_doboot(void);
 
-extern void setlevel(unsigned int);
-
 extern void	m187_bootstrap(void);
 extern vaddr_t	m187_memsize(void);
 extern void	m187_startup(void);
@@ -1114,53 +1111,22 @@ bootcnputc(dev, c)
 		bugoutchr(c);
 }
 
-u_int
+int
 getipl(void)
 {
-	u_int curspl, psr;
-
-	disable_interrupt(psr);
-	curspl = (*md_getipl)();
-	set_psr(psr);
-	return curspl;
+	return (int)(*md_getipl)();
 }
 
-unsigned
-setipl(unsigned level)
+int
+setipl(int level)
 {
-	u_int curspl, psr;
-
-	disable_interrupt(psr);
-	curspl = (*md_setipl)(level);
-
-	/*
-	 * The flush pipeline is required to make sure the above change gets
-	 * through the data pipe and to the hardware; otherwise, the next
-	 * bunch of instructions could execute at the wrong spl protection.
-	 */
-	flush_pipeline();
-
-	set_psr(psr);
-	return curspl;
+	return (int)(*md_setipl)((u_int)level);
 }
 
-unsigned
-raiseipl(unsigned level)
+int
+raiseipl(int level)
 {
-	u_int curspl, psr;
-
-	disable_interrupt(psr);
-	curspl = (*md_raiseipl)(level);
-
-	/*
-	 * The flush pipeline is required to make sure the above change gets
-	 * through the data pipe and to the hardware; otherwise, the next
-	 * bunch of instructions could execute at the wrong spl protection.
-	 */
-	flush_pipeline();
-
-	set_psr(psr);
-	return curspl;
+	return (int)(*md_raiseipl)((u_int)level);
 }
 
 #ifdef MULTIPROCESSOR