More cmmu routines cleanup:

- remove unused routines (which were mostly here for debugging anyway)
- do not include <machine/m88*.h> from <machine/cmmu.h> but rather only
  from the modules which need them
- try to simplify the MVME187 codepath in the 8820x code, whenever possible

5 files changed, 869 insertions, 1307 deletions

diff --git a/sys/arch/mvme88k/include/cmmu.h b/sys/arch/mvme88k/include/cmmu.h
index 368e3191b0c..ab00a3482c5 100644
--- a/sys/arch/mvme88k/include/cmmu.h
+++ b/sys/arch/mvme88k/include/cmmu.h
@@ -1,27 +1,27 @@
-/*	$OpenBSD: cmmu.h,v 1.13 2003/09/26 22:27:25 miod Exp $ */
-/* 
+/*	$OpenBSD: cmmu.h,v 1.14 2003/10/05 20:35:22 miod Exp $ */
+/*
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
  * All Rights Reserved.
- * 
+ *
  * Permission to use, copy, modify and distribute this software and its
  * documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
- * 
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
+ *
  * Carnegie Mellon requests users of this software to return to
- * 
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
- * 
- * any improvements or extensions that they make and grant Carnegie Mellon 
+ *
+ * any improvements or extensions that they make and grant Carnegie Mellon
  * the rights to redistribute these changes.
  */
 
@@ -30,28 +30,6 @@
 
 #include <machine/mmu.h>
 
-/* Area Description */
-#define AREA_D_WT	0x00000200	/* write through */
-#define AREA_D_G	0x00000080	/* global */
-#define AREA_D_CI	0x00000040	/* cache inhibit */
-#define AREA_D_TE	0x00000001	/* translation enable */
-
-/* Segment Description */
-#define SEG_D_WT	0x00000200	/* write through */
-#define SEG_D_SP	0x00000100	/* supervisor protection */
-#define SEG_D_G		0x00000080	/* global */
-#define SEG_D_CI	0x00000040	/* cache inhibit */
-#define SEG_D_WP	0x00000004	/* write protect */
-#define SEG_D_V		0x00000001	/* valid */
-
-/*
- * Flags for cmmu_flush_tlb
- */
-#define FLUSH_KERNEL    1
-#define FLUSH_USER      0
-#define FLUSH_ALL       ((vm_offset_t)~0)
-
-
 #ifndef	_LOCORE
 /*
  * Prototypes and stuff for cmmu.c.
@@ -63,8 +41,8 @@ extern unsigned cache_policy;
 extern int max_cpus, max_cmmus;
 
 /*
- * This lock protects the cmmu SAR and SCR's; other ports 
- * can be accessed without locking it 
+ * This lock protects the cmmu SAR and SCR's; other ports
+ * can be accessed without locking it
  *
  * May be used from "db_interface.c".
  */
@@ -76,64 +54,48 @@ extern struct simplelock cmmu_cpu_lock;
 /* machine dependant cmmu function pointer structure */
 struct cmmu_p {
 	void (*cmmu_init_func)(void);
-	void (*show_apr_func)(unsigned);
 	void (*setup_board_config_func)(void);
-	void (*setup_cmmu_config_func)(void);
-	void (*cmmu_dump_config_func)(void);
 	void (*cpu_configuration_print_func)(int);
 	void (*cmmu_shutdown_now_func)(void);
 	void (*cmmu_parity_enable_func)(void);
 	unsigned (*cmmu_cpu_number_func)(void);
-	unsigned (*cmmu_get_idr_func)(unsigned);
-	void (*cmmu_set_sapr_func)(unsigned);
 	void (*cmmu_remote_set_sapr_func)(unsigned, unsigned);
 	void (*cmmu_set_uapr_func)(unsigned);
-	void (*cmmu_set_batc_entry_func)(unsigned, unsigned, unsigned, unsigned);
 	void (*cmmu_set_pair_batc_entry_func)(unsigned, unsigned, unsigned);
-	void (*cmmu_flush_remote_tlb_func)(unsigned, unsigned, vm_offset_t, int);
-	void (*cmmu_flush_tlb_func)(unsigned, vm_offset_t, int);
+	void (*cmmu_flush_remote_tlb_func)(unsigned, unsigned, vaddr_t, vsize_t);
+	void (*cmmu_flush_tlb_func)(unsigned, vaddr_t, vsize_t);
 	void (*cmmu_pmap_activate_func)(unsigned, unsigned,
 	    u_int32_t i_batc[BATC_MAX], u_int32_t d_batc[BATC_MAX]);
-	void (*cmmu_flush_remote_cache_func)(int, vm_offset_t, int);
-	void (*cmmu_flush_cache_func)(vm_offset_t, int);
-	void (*cmmu_flush_remote_inst_cache_func)(int, vm_offset_t, int);
-	void (*cmmu_flush_inst_cache_func)(vm_offset_t, int);
-	void (*cmmu_flush_remote_data_cache_func)(int, vm_offset_t, int);
-	void (*cmmu_flush_data_cache_func)(vm_offset_t, int);
-	void (*dma_cachectl_func)(vm_offset_t, int, int);
-#ifdef DDB
-	unsigned (*cmmu_get_by_mode_func)(int, int);
+	void (*cmmu_flush_remote_cache_func)(int, paddr_t, psize_t);
+	void (*cmmu_flush_cache_func)(paddr_t, psize_t);
+	void (*cmmu_flush_remote_inst_cache_func)(int, paddr_t, psize_t);
+	void (*cmmu_flush_inst_cache_func)(paddr_t, psize_t);
+	void (*cmmu_flush_remote_data_cache_func)(int, paddr_t, psize_t);
+	void (*cmmu_flush_data_cache_func)(paddr_t, psize_t);
+	void (*dma_cachectl_func)(vaddr_t, vsize_t, int);
+	/* DDB only */
+	void (*cmmu_dump_config_func)(void);
 	void (*cmmu_show_translation_func)(unsigned, unsigned, unsigned, int);
-	void (*cmmu_cache_state_func)(unsigned, unsigned);
-	void (*show_cmmu_info_func)(unsigned);
-#endif /* end if DDB */
+	/* DEBUG only */
+	void (*show_apr_func)(unsigned);
 };
 
 /* THE pointer! */
 extern struct cmmu_p *cmmu;
 
-extern struct cmmu_p cmmu88110;
-extern struct cmmu_p cmmu8820x;
-
 /* The macros... */
-#define cmmu_init (cmmu->cmmu_init_func)
-#define show_apr(ap) (cmmu->show_apr_func)(ap)
+#define cmmu_init		(cmmu->cmmu_init_func)
 #define setup_board_config	(cmmu->setup_board_config_func)
-#define	setup_cmmu_config 	(cmmu->setup_cmmu_config_func)
-#define	cmmu_dump_config	(cmmu->cmmu_dump_config_func)
 #define	cpu_configuration_print(a)	(cmmu->cpu_configuration_print_func)(a)
 #define	cmmu_shutdown_now	(cmmu->cmmu_shutdown_now_func)
 #define	cmmu_parity_enable	(cmmu->cmmu_parity_enable_func)
 #define	cmmu_cpu_number		(cmmu->cmmu_cpu_number_func)
-#define	cmmu_get_idr(a)		(cmmu->cmmu_get_idr_func)(a)
-#define	cmmu_set_sapr(a)	(cmmu->cmmu_set_sapr_func)(a)
 #define	cmmu_remote_set_sapr(a, b)	(cmmu->cmmu_remote_set_sapr_func)(a, b)
 #define	cmmu_set_uapr(a)	(cmmu->cmmu_set_uapr_func)(a)
-#define	cmmu_set_batc_entry(a, b, c, d) 	(cmmu->cmmu_set_batc_entry_func)(a, b, c, d)
 #define	cmmu_set_pair_batc_entry(a, b, c)	(cmmu->cmmu_set_pair_batc_entry_func)(a, b, c)
 #define	cmmu_flush_remote_tlb(a, b, c, d) 	(cmmu->cmmu_flush_remote_tlb_func)(a, b, c, d)
 #define	cmmu_flush_tlb(a, b, c)	(cmmu->cmmu_flush_tlb_func)(a, b, c)
-#define	cmmu_pmap_activate(a, b, c, d) 	(cmmu->cmmu_pmap_activate_func)(a, b, c, d) 
+#define	cmmu_pmap_activate(a, b, c, d) 	(cmmu->cmmu_pmap_activate_func)(a, b, c, d)
 #define	cmmu_flush_remote_cache(a, b, c)	(cmmu->cmmu_flush_remote_cache_func)(a, b, c)
 #define	cmmu_flush_cache(a, b)	(cmmu->cmmu_flush_cache_func)(a, b)
 #define	cmmu_flush_remote_inst_cache(a, b, c)	(cmmu->cmmu_flush_remote_inst_cache_func)(a, b, c)
@@ -141,22 +103,11 @@ extern struct cmmu_p cmmu8820x;
 #define	cmmu_flush_remote_data_cache(a, b, c)	(cmmu->cmmu_flush_remote_data_cache_func)(a, b, c)
 #define	cmmu_flush_data_cache(a, b)	(cmmu->cmmu_flush_data_cache_func)(a, b)
 #define	dma_cachectl(a, b, c)	(cmmu->dma_cachectl_func)(a, b, c)
-#ifdef DDB
-#define	cmmu_get_by_mode(a, b)	(cmmu->cmmu_get_by_mode_func)(a, b)
+#define	cmmu_dump_config	(cmmu->cmmu_dump_config_func)
 #define	cmmu_show_translation(a, b, c, d)	(cmmu->cmmu_show_translation_func)(a, b, c, d)
-#define	cmmu_cache_state(a, b)	(cmmu->cmmu_cache_state_func)(a, b)
-#define	show_cmmu_info(a)	(cmmu->show_cmmu_info_func)(a)
-#endif /* end if DDB */
+#define show_apr(ap)		(cmmu->show_apr_func)(ap)
 
 #endif	/* _LOCORE */
 
-#ifdef M88100
-#include <machine/m8820x.h>
-#endif /* M88100 */
-#ifdef M88110
-#include <machine/m88110.h>
-#include <machine/m88410.h>
-#endif /* M88110 */
-
 #endif	/* _MACHINE_CMMU_H_ */
 
diff --git a/sys/arch/mvme88k/include/m88110.h b/sys/arch/mvme88k/include/m88110.h
index bcd4b0436b1..a3d895af714 100644
--- a/sys/arch/mvme88k/include/m88110.h
+++ b/sys/arch/mvme88k/include/m88110.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.h,v 1.14 2003/09/26 22:27:25 miod Exp $ */
+/*	$OpenBSD: m88110.h,v 1.15 2003/10/05 20:35:22 miod Exp $ */
 
 #ifndef	__MACHINE_M88110_H__
 #define	__MACHINE_M88110_H__
@@ -125,45 +125,6 @@
 
 #ifndef	_LOCORE
 
-/*
- * Prototypes from "mvme88k/mvme88k/m88110_cmmu.c"
- */
-void m88110_show_apr(unsigned);
-void m88110_show_sctr(unsigned);
-void m88110_setup_board_config(void);
-void m88110_setup_cmmu_config(void);
-void m88110_cmmu_dump_config(void);
-void m88110_cpu_configuration_print(int);
-void m88110_cmmu_shutdown_now(void);
-void m88110_cmmu_parity_enable(void);
-unsigned m88110_cmmu_cpu_number(void);
-unsigned m88110_cmmu_get_idr(unsigned);
-void m88110_cmmu_set_sapr(unsigned);
-void m88110_cmmu_remote_set_sapr(unsigned, unsigned);
-void m88110_cmmu_set_uapr(unsigned);
-void m88110_cmmu_set_batc_entry(unsigned, unsigned, unsigned, unsigned);
-void m88110_cmmu_set_pair_batc_entry(unsigned, unsigned, unsigned);
-void m88110_cmmu_flush_remote_tlb(unsigned, unsigned, vm_offset_t, int);
-void m88110_cmmu_flush_tlb(unsigned, vm_offset_t, int);
-void m88110_cmmu_pmap_activate(unsigned, unsigned, 
-    u_int32_t i_batc[BATC_MAX], u_int32_t d_batc[BATC_MAX]);
-void m88110_cmmu_flush_remote_cache(int, vm_offset_t, int);
-void m88110_cmmu_flush_cache(vm_offset_t, int);
-void m88110_cmmu_flush_remote_inst_cache(int, vm_offset_t, int);
-void m88110_cmmu_flush_inst_cache(vm_offset_t, int);
-void m88110_cmmu_flush_remote_data_cache(int, vm_offset_t, int);
-void m88110_cmmu_flush_data_cache(vm_offset_t, int);
-void m88110_dma_cachectl(vm_offset_t, int, int);
-
-#if DDB
-unsigned m88110_cmmu_get_by_mode(int, int);
-void m88110_cmmu_show_translation(unsigned, unsigned, unsigned, int);
-void m88110_cmmu_cache_state(unsigned, unsigned);
-void m88110_show_cmmu_info(unsigned);
-#endif
-
-void m88110_cmmu_init(void);
-
 void set_icmd(unsigned value);
 void set_ictl(unsigned value);
 void set_isar(unsigned value);
@@ -217,23 +178,23 @@ unsigned get_dpar(void);
 
 /* Cache inlines */
 
-#define line_addr(x)	(vm_offset_t)((x) & ~CLINE_MASK)
-#define page_addr(x)	(vm_offset_t)((x) & ~PAGE_MASK)
+#define line_addr(x)	(paddr_t)((x) & ~CLINE_MASK)
+#define page_addr(x)	(paddr_t)((x) & ~PAGE_MASK)
 
-static __inline__ void mc88110_flush_data_line(vm_offset_t x)
+static __inline__ void mc88110_flush_data_line(paddr_t x)
 {
 	unsigned dctl = get_dctl();
 	if (dctl & CMMU_DCTL_CEN){
-		set_dsar(line_addr(x)); 
+		set_dsar(line_addr(x));
 		set_dcmd(CMMU_DCMD_FLUSH_LINE);
 	}
 }
 
-static __inline__ void mc88110_flush_data_page(vm_offset_t x)
+static __inline__ void mc88110_flush_data_page(paddr_t x)
 {
 	unsigned dctl = get_dctl();
 	if (dctl & CMMU_DCTL_CEN){
-		set_dsar(page_addr(x)); 
+		set_dsar(page_addr(x));
 		set_dcmd(CMMU_DCMD_FLUSH_PG);
 	}
 }
@@ -247,7 +208,7 @@ static __inline__ void mc88110_flush_data(void)
 	}
 }
 
-static __inline__ void mc88110_inval_data_line(vm_offset_t x)
+static __inline__ void mc88110_inval_data_line(paddr_t x)
 {
 	set_dsar(line_addr(x));
 	set_dcmd(CMMU_DCMD_INV_LINE);
@@ -259,20 +220,20 @@ static __inline__ void mc88110_inval_data(void)
 	set_dcmd(CMMU_DCMD_INV_ALL);
 }
 
-static __inline__ void mc88110_sync_data_line(vm_offset_t x)
+static __inline__ void mc88110_sync_data_line(paddr_t x)
 {
 	unsigned dctl = get_dctl();
 	if (dctl & CMMU_DCTL_CEN){
-		set_dsar(line_addr(x)); 
+		set_dsar(line_addr(x));
 		set_dcmd(CMMU_DCMD_FLUSH_LINE_INV);
 	}
 }
 
-static __inline__ void mc88110_sync_data_page(vm_offset_t x)
+static __inline__ void mc88110_sync_data_page(paddr_t x)
 {
 	unsigned dctl = get_dctl();
 	if (dctl & CMMU_DCTL_CEN){
-		set_dsar(page_addr(x)); 
+		set_dsar(page_addr(x));
 		set_dcmd(CMMU_DCMD_FLUSH_PG_INV);
 	}
 }
@@ -286,7 +247,7 @@ static __inline__ void mc88110_sync_data(void)
 	}
 }
 
-static __inline__ void mc88110_inval_inst_line(vm_offset_t x)
+static __inline__ void mc88110_inval_inst_line(paddr_t x)
 {
 	set_isar(line_addr(x));
 	set_icmd(CMMU_ICMD_INV_LINE);
@@ -299,4 +260,4 @@ static __inline__ void mc88110_inval_inst(void)
 }
 
 #endif	/* _LOCORE */
-#endif /* __MACHINE_M88110_H__ */
+#endif	/* __MACHINE_M88110_H__ */
diff --git a/sys/arch/mvme88k/include/m8820x.h b/sys/arch/mvme88k/include/m8820x.h
index 552f280dfff..f27a2d16101 100644
--- a/sys/arch/mvme88k/include/m8820x.h
+++ b/sys/arch/mvme88k/include/m8820x.h
@@ -1,40 +1,35 @@
-/*	$OpenBSD: m8820x.h,v 1.7 2003/09/26 22:27:25 miod Exp $ */
-/* 
+/*	$OpenBSD: m8820x.h,v 1.8 2003/10/05 20:35:22 miod Exp $ */
+/*
  * Mach Operating System
  * Copyright (c) 1993-1992 Carnegie Mellon University
  * All Rights Reserved.
- * 
+ *
  * Permission to use, copy, modify and distribute this software and its
  * documentation is hereby granted, provided that both the copyright
  * notice and this permission notice appear in all copies of the
  * software, derivative works or modified versions, and any portions
  * thereof, and that both notices appear in supporting documentation.
- * 
+ *
  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- * 
+ *
  * Carnegie Mellon requests users of this software to return to
- * 
+ *
  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  *  School of Computer Science
  *  Carnegie Mellon University
  *  Pittsburgh PA 15213-3890
- * 
- * any improvements or extensions that they make and grant Carnegie Mellon 
+ *
+ * any improvements or extensions that they make and grant Carnegie Mellon
  * the rights to redistribute these changes.
  */
-/*
- * HISTORY
- * 
- */
-
 
 #ifndef	__MACHINE_M8820X_H__
 #define	__MACHINE_M8820X_H__
 
 /*
- *	88200 CMMU definitions
+ *	8820x CMMU definitions
  */
 #define CMMU_IDR	0x000	/* CMMU id register */
 #define CMMU_SCR	0x004	/* system command register */
@@ -63,30 +58,15 @@
 #define CMMU_CTP3	0x84C	/* cache tag port 3 */
 #define CMMU_CSSP	0x880	/* cache set status register */
 
-#define CMMU_BWP(_X_) \
-	(((_X_) < 7) ? \
-	 (((_X_) < 6) ? \
-	  (((_X_) < 5) ? \
-	   (((_X_) < 4) ? \
-	    (((_X_) < 3) ? \
-	     (((_X_) < 2) ? \
-	      (((_X_) < 1) ? \
-	       CMMU_BWP0 : \
-	       CMMU_BWP1) : \
-	      CMMU_BWP2) : \
-	     CMMU_BWP3) : \
-	    CMMU_BWP4) : \
-	   CMMU_BWP5) : \
-	  CMMU_BWP6) : \
-	 CMMU_BWP7)
-
-/* 88204 CMMU definitions  */
+#define CMMU_BWP(n)	(CMMU_BWP0 + ((n) << 2))
+
+/* 88204 CMMU extra definitions  */
 #define CMMU_CSSP0	0x880	/* cache set status register */
 #define CMMU_CSSP1	0x890	/* cache set status register */
 #define CMMU_CSSP2	0x8A0	/* cache set status register */
 #define CMMU_CSSP3	0x8B0	/* cache set status register */
 
-/* CMMU systerm commands */
+/* CMMU system commands */
 #define CMMU_FLUSH_USER_LINE		0x30	/* flush PATC */
 #define CMMU_FLUSH_USER_PAGE		0x31
 #define CMMU_FLUSH_USER_SEGMENT		0x32
@@ -123,47 +103,11 @@
 #define CMMU_PFSR_SUPER		6	/* supervisor violation */
 #define CMMU_PFSR_WRITE		7	/* writer violation */
 
-#ifndef	_LOCORE
-
-/*
- * Prototypes from "mvme88k/mvme88k/m8820x.c"
- */
-void m8820x_show_apr(unsigned);
-void m8820x_setup_board_config(void);
-void m8820x_setup_cmmu_config(void);
-void m8820x_cmmu_dump_config(void);
-void m8820x_cpu_configuration_print(int);
-void m8820x_cmmu_shutdown_now(void);
-void m8820x_cmmu_parity_enable(void);
-unsigned m8820x_cmmu_cpu_number(void);
-unsigned m8820x_cmmu_get_idr(unsigned);
-void m8820x_cmmu_set_sapr(unsigned);
-void m8820x_cmmu_remote_set_sapr(unsigned, unsigned);
-void m8820x_cmmu_set_uapr(unsigned);
-void m8820x_cmmu_set_batc_entry(unsigned, unsigned, unsigned, unsigned);
-void m8820x_cmmu_set_pair_batc_entry(unsigned, unsigned, unsigned);
-void m8820x_cmmu_flush_remote_tlb(unsigned, unsigned, vm_offset_t, int);
-void m8820x_cmmu_flush_tlb(unsigned, vm_offset_t, int);
-void m8820x_cmmu_pmap_activate(unsigned, unsigned, 
-    u_int32_t i_batc[BATC_MAX], u_int32_t d_batc[BATC_MAX]);
-void m8820x_cmmu_flush_remote_cache(int, vm_offset_t, int);
-void m8820x_cmmu_flush_cache(vm_offset_t, int);
-void m8820x_cmmu_flush_remote_inst_cache(int, vm_offset_t, int);
-void m8820x_cmmu_flush_inst_cache(vm_offset_t, int);
-void m8820x_cmmu_flush_remote_data_cache(int, vm_offset_t, int);
-void m8820x_cmmu_flush_data_cache(vm_offset_t, int);
-void m8820x_dma_cachectl(vm_offset_t, int, int);
-
-#if DDB
-unsigned m8820x_cmmu_get_by_mode(int, int);
-void m8820x_cmmu_show_translation(unsigned, unsigned, unsigned, int);
-void m8820x_cmmu_cache_state(unsigned, unsigned);
-void m8820x_show_cmmu_info(unsigned);
-#endif 
-
-void m8820x_cmmu_init(void);
-
-#endif	/* _LOCORE */
+/* Area Description */
+#define AREA_D_WT	0x00000200	/* write through */
+#define AREA_D_G	0x00000080	/* global */
+#define AREA_D_CI	0x00000040	/* cache inhibit */
+#define AREA_D_TE	0x00000001	/* translation enable */
 
 /*
  * Possible MVME188 board configurations
@@ -178,18 +122,13 @@ void m8820x_cmmu_init(void);
 /*
  * Address masks for MMU configs
  */
-#define CMMU_SRAM		      (1<<31)
-#define CMMU_A12_MASK		(1<<12)
-#define CMMU_A14_MASK		(1<<14)
-#define CMMU_SRAM_MASK		((1<<31)|(1<<30))
-
-#define INST_CMMU 0
-#define DATA_CMMU 1
-#define BOTH_CMMU 2
+#define CMMU_SRAM		(1 << 31)
+#define CMMU_A12_MASK		(1 << 12)
+#define CMMU_A14_MASK		(1 << 14)
+#define CMMU_SRAM_MASK		((1 << 31) | (1 << 30))
 
-#define CMMU_MODE_INST		0
-#define CMMU_MODE_DATA		1
-#define CMMU_MODE_BOTH		2
+#define INST_CMMU 		0
+#define DATA_CMMU 		1
 
 #define CMMU_ACS_USER		0
 #define CMMU_ACS_SUPER		1
@@ -204,15 +143,6 @@ void m8820x_cmmu_init(void);
 
 #define CMMU_NSTRATEGIES	4
 
-/*
- * Flags passed to cmmu_set()
- */
-#define NUM_CMMU		0x01
-#define NUM_CPU			0x02 /* notyetused */
-#define MODE_VAL		0x04
-#define ACCESS_VAL		0x08
-#define ADDR_VAL		0x10
-
 #define NBSG    (4*1024*1024) /* segment size */
 
 #endif	/* __MACHINE_M8820X_H__ */
diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c
index 35bb220c4d4..61bc6489eba 100644
--- a/sys/arch/mvme88k/mvme88k/m88110.c
+++ b/sys/arch/mvme88k/mvme88k/m88110.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.c,v 1.9 2003/09/26 22:27:26 miod Exp $	*/
+/*	$OpenBSD: m88110.c,v 1.10 2003/10/05 20:35:26 miod Exp $	*/
 /*
  * Copyright (c) 1998 Steve Murphree, Jr.
  * All rights reserved.
@@ -64,6 +64,8 @@
 #include <machine/board.h>
 #include <machine/cpu_number.h>
 #include <machine/cmmu.h>
+#include <machine/m88110.h>
+#include <machine/m88410.h>
 #include <machine/locore.h>
 #include <machine/trap.h>
 
@@ -73,7 +75,7 @@ unsigned int debuglevel = 0;
 #define dprintf(_L_,_X_) { if (debuglevel & (_L_)) { unsigned int psr = disable_interrupts_return_psr(); printf("%d: ", cpu_number()); printf _X_;  set_psr(psr); } }
 #else
 #define dprintf(_L_,_X_)
-#endif 
+#endif
 
 #ifdef DDB
 #include <ddb/db_output.h>		/* db_printf()		*/
@@ -84,28 +86,40 @@ unsigned int debuglevel = 0;
 #define STATIC	static
 #endif /* DDB */
 
-/* FORWARDS */
-void patc_clear(void);
-void m88110_cmmu_sync_cache(vm_offset_t physaddr, int size);
-void m88110_cmmu_sync_inval_cache(vm_offset_t physaddr, int size);
-void m88110_cmmu_inval_cache(vm_offset_t physaddr, int size);
+void m88110_cmmu_init(void);
+void m88110_setup_board_config(void);
+void m88110_cpu_configuration_print(int);
+void m88110_cmmu_shutdown_now(void);
+void m88110_cmmu_parity_enable(void);
+unsigned m88110_cmmu_cpu_number(void);
+void m88110_cmmu_remote_set_sapr(unsigned, unsigned);
+void m88110_cmmu_set_uapr(unsigned);
+void m88110_cmmu_set_pair_batc_entry(unsigned, unsigned, unsigned);
+void m88110_cmmu_flush_remote_tlb(unsigned, unsigned, vaddr_t, vsize_t);
+void m88110_cmmu_flush_tlb(unsigned, vaddr_t, vsize_t);
+void m88110_cmmu_pmap_activate(unsigned, unsigned,
+    u_int32_t i_batc[BATC_MAX], u_int32_t d_batc[BATC_MAX]);
+void m88110_cmmu_flush_remote_cache(int, paddr_t, psize_t);
+void m88110_cmmu_flush_cache(paddr_t, psize_t);
+void m88110_cmmu_flush_remote_inst_cache(int, paddr_t, psize_t);
+void m88110_cmmu_flush_inst_cache(paddr_t, psize_t);
+void m88110_cmmu_flush_remote_data_cache(int, paddr_t, psize_t);
+void m88110_cmmu_flush_data_cache(paddr_t, psize_t);
+void m88110_dma_cachectl(vaddr_t, vsize_t, int);
+void m88110_cmmu_dump_config(void);
+void m88110_cmmu_show_translation(unsigned, unsigned, unsigned, int);
+void m88110_show_apr(unsigned);
 
 /* This is the function table for the mc88110 built-in CMMUs */
 struct cmmu_p cmmu88110 = {
         m88110_cmmu_init,
-        m88110_show_apr,
 	m88110_setup_board_config,
-	m88110_setup_cmmu_config,
-	m88110_cmmu_dump_config,
 	m88110_cpu_configuration_print,
 	m88110_cmmu_shutdown_now,
 	m88110_cmmu_parity_enable,
 	m88110_cmmu_cpu_number,
-	m88110_cmmu_get_idr,
-	m88110_cmmu_set_sapr,
 	m88110_cmmu_remote_set_sapr,
 	m88110_cmmu_set_uapr,
-	m88110_cmmu_set_batc_entry,
 	m88110_cmmu_set_pair_batc_entry,
 	m88110_cmmu_flush_remote_tlb,
 	m88110_cmmu_flush_tlb,
@@ -118,13 +132,24 @@ struct cmmu_p cmmu88110 = {
 	m88110_cmmu_flush_data_cache,
 	m88110_dma_cachectl,
 #ifdef DDB
-	m88110_cmmu_get_by_mode,
+	m88110_cmmu_dump_config,
 	m88110_cmmu_show_translation,
-	m88110_cmmu_cache_state,
-	m88110_show_cmmu_info,
+#else
+	NULL,
+	NULL,
+#endif
+#ifdef DEBUG
+        m88110_show_apr,
+#else
+	NULL,
 #endif
 };
 
+void patc_clear(void);
+void m88110_cmmu_sync_cache(paddr_t, psize_t);
+void m88110_cmmu_sync_inval_cache(paddr_t, psize_t);
+void m88110_cmmu_inval_cache(paddr_t, psize_t);
+
 void
 patc_clear(void)
 {
@@ -141,6 +166,7 @@ patc_clear(void)
 	}
 }
 
+#ifdef DEBUG
 void
 m88110_show_apr(unsigned value)
 {
@@ -157,44 +183,21 @@ m88110_show_apr(unsigned value)
 		printf(", not valid");
 	printf("\n");
 }
+#endif
 
-void 
+void
 m88110_setup_board_config(void)
 {
-	/* dummy routine */
-	m88110_setup_cmmu_config();
-}
-
-void 
-m88110_setup_cmmu_config(void)
-{
-	/* we can print something here... */
+	/* we could print something here... */
 	cpu_sets[0] = 1;   /* This cpu installed... */
 }
 
-void m88110_cmmu_dump_config(void)
-{
-	/* dummy routine */
-}
-
-#ifdef DDB
-/*
- * Used by DDB for cache probe functions
- */
-unsigned m88110_cmmu_get_by_mode(int cpu, int mode)
-{
-	CMMU_LOCK;
-	CMMU_UNLOCK;
-	return 0;
-}
-#endif
-
 /*
  * Should only be called after the calling cpus knows its cpu
  * number and master/slave status . Should be called first
  * by the master, before the slaves are started.
-*/
-void 
+ */
+void
 m88110_cpu_configuration_print(int master)
 {
 	int pid = read_processor_identification_register();
@@ -241,22 +244,22 @@ m88110_cmmu_init(void)
 
 	/* clear PATCs */
 	patc_clear();
-	
+
 	/* Do NOT enable ICTL_PREN (branch prediction) */
-	set_ictl(BATC_32M 
+	set_ictl(BATC_32M
 		 | CMMU_ICTL_DID	/* Double instruction disable */
 		 | CMMU_ICTL_MEN
-		 | CMMU_ICTL_CEN 
+		 | CMMU_ICTL_CEN
 		 | CMMU_ICTL_BEN
 		 | CMMU_ICTL_HTEN);
 
-	set_dctl(BATC_32M 
+	set_dctl(BATC_32M
                  | CMMU_DCTL_RSVD1	/* Data Matching Disable */
                  | CMMU_DCTL_MEN
-		 | CMMU_DCTL_CEN 
+		 | CMMU_DCTL_CEN
 		 | CMMU_DCTL_SEN
 		 | CMMU_DCTL_ADS
-		 | CMMU_DCTL_HTEN);      
+		 | CMMU_DCTL_HTEN);
 
 	mc88110_inval_inst();		/* clear instruction cache & TIC */
 	mc88110_inval_data();		/* clear data cache */
@@ -279,20 +282,22 @@ m88110_cmmu_init(void)
 void
 m88110_cmmu_shutdown_now(void)
 {
+#if 0
 	CMMU_LOCK;
         CMMU_UNLOCK;
+#endif
 }
 
 /*
- * enable parity
+ * Enable parity
  */
-void 
+void
 m88110_cmmu_parity_enable(void)
 {
-#ifdef	PARITY_ENABLE
+#if 0
 	CMMU_LOCK;
         CMMU_UNLOCK;
-#endif  /* PARITY_ENABLE */
+#endif
 }
 
 /*
@@ -301,23 +306,17 @@ m88110_cmmu_parity_enable(void)
  * disabled.
  */
 
-unsigned 
+unsigned
 m88110_cmmu_cpu_number(void)
 {
 	return 0; /* to make compiler happy */
 }
 
-/* Needs no locking - read only registers */
-unsigned
-m88110_cmmu_get_idr(unsigned data)
-{
-	return 0; /* todo */
-}
-
 void
-m88110_cmmu_set_sapr(unsigned ap)
+m88110_cmmu_remote_set_sapr(unsigned cpu, unsigned ap)
 {
 	unsigned ictl, dctl;
+
 	CMMU_LOCK;
 
 	set_icmd(CMMU_ICMD_INV_SATC);
@@ -332,25 +331,19 @@ m88110_cmmu_set_sapr(unsigned ap)
 
 	set_isap(ap);
 	set_dsap(ap);
-	
+
 	patc_clear();
-	
+
 	set_icmd(CMMU_ICMD_INV_UATC);
 	set_icmd(CMMU_ICMD_INV_SATC);
 	set_dcmd(CMMU_DCMD_INV_UATC);
 	set_dcmd(CMMU_DCMD_INV_SATC);
-	
+
 	/* restore MMU settings */
 	set_ictl(ictl);
 	set_dctl(dctl);
-	
-	CMMU_UNLOCK;
-}
 
-void
-m88110_cmmu_remote_set_sapr(unsigned cpu, unsigned ap)
-{
-	m88110_cmmu_set_sapr(ap);
+	CMMU_UNLOCK;
 }
 
 void
@@ -366,53 +359,40 @@ m88110_cmmu_set_uapr(unsigned ap)
 }
 
 /*
- * Set batc entry number entry_no to value in 
- * the data or instruction cache depending on data.
+ * Set batc entry number entry_no to value in
+ * the data and instruction cache for the named CPU.
  *
- * Except for the cmmu_init, this function, m88110_cmmu_set_pair_batc_entry,
- * and m88110_cmmu_pmap_activate are the only functions which may set the
- * batc values.
+ * Except for the cmmu_init, this function and m88110_cmmu_pmap_activate
+ * are the only functions which may set the batc values.
  */
 void
-m88110_cmmu_set_batc_entry(unsigned cpu, unsigned entry_no, unsigned data,
-    unsigned value)
+m88110_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value)
 {
 	CMMU_LOCK;
-	if (data) {
-		set_dir(entry_no);
-		set_dbp(value);
-	} else {
-		set_iir(entry_no);
-		set_ibp(value);
-	}
+
+	set_dir(entry_no);
+	set_dbp(value);
+
+	set_iir(entry_no);
+	set_ibp(value);
+
 	CMMU_UNLOCK;
 }
 
 /*
- * Set batc entry number entry_no to value in 
- * the data and instruction cache for the named CPU.
+ *	Functions that invalidate TLB entries.
  */
-void
-m88110_cmmu_set_pair_batc_entry(unsigned cpu, unsigned entry_no, unsigned value)
-{
-	m88110_cmmu_set_batc_entry(cpu, entry_no, 1, value);
-	m88110_cmmu_set_batc_entry(cpu, entry_no, 0, value);
-}
-
-/**
- **	Functions that invalidate TLB entries.
- **/
 
 /*
  *	flush any tlb
  *	Some functionality mimiced in m88110_cmmu_pmap_activate.
  */
 void
-m88110_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr,
-    int size)
+m88110_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vaddr_t vaddr,
+    vsize_t size)
 {
 	int s = splhigh();	/* XXX really disable interrupts? */
-	
+
 	CMMU_LOCK;
 	if (kernel) {
 		set_icmd(CMMU_ICMD_INV_SATC);
@@ -422,7 +402,7 @@ m88110_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr,
 		set_dcmd(CMMU_DCMD_INV_UATC);
 	}
 	CMMU_UNLOCK;
-	
+
 	splx(s);
 }
 
@@ -430,7 +410,7 @@ m88110_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vm_offset_t vaddr,
  *	flush my personal tlb
  */
 void
-m88110_cmmu_flush_tlb(unsigned kernel, vm_offset_t vaddr, int size)
+m88110_cmmu_flush_tlb(unsigned kernel, vaddr_t vaddr, vsize_t size)
 {
 	int cpu = cpu_number();
 
@@ -463,34 +443,40 @@ m88110_cmmu_pmap_activate(unsigned cpu, unsigned uapr,
 	set_dcmd(CMMU_DCMD_INV_UATC);
 }
 
-/**
- **	Functions that invalidate caches.
- **
- ** Cache invalidates require physical addresses.  Care must be exercised when
- ** using segment invalidates.  This implies that the starting physical address
- ** plus the segment length should be invalidated.  A typical mistake is to
- ** extract the first physical page of a segment from a virtual address, and
- ** then expecting to invalidate when the pages are not physically contiguous.
- **
- ** We don't push Instruction Caches prior to invalidate because they are not
- ** snooped and never modified (I guess it doesn't matter then which form
- ** of the command we use then).
- **/
-
-/* 
- * Care must be taken to avoid flushing the data cache when 
+/*
+ *	Functions that invalidate caches.
+ *
+ * Cache invalidates require physical addresses.  Care must be exercised when
+ * using segment invalidates.  This implies that the starting physical address
+ * plus the segment length should be invalidated.  A typical mistake is to
+ * extract the first physical page of a segment from a virtual address, and
+ * then expecting to invalidate when the pages are not physically contiguous.
+ *
+ * We don't push Instruction Caches prior to invalidate because they are not
+ * snooped and never modified (I guess it doesn't matter then which form
+ * of the command we use then).
+ */
+
+/*
+ * Care must be taken to avoid flushing the data cache when
  * the data cache is not on!  From the 0F92L Errata Documentation
  * Package, Version 1.1
  */
 
 /*
+ * XXX These routines are really suboptimal because they invalidate
+ * way too much...
+ * Improve them once the 197 support is really working...
+ */
+
+/*
  *	flush both Instruction and Data caches
  */
 void
-m88110_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size)
+m88110_cmmu_flush_remote_cache(int cpu, paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();	/* XXX really disable interrupts? */
-	
+
 	mc88110_inval_inst();
 	mc88110_flush_data();
 	if (mc88410_present())
@@ -502,10 +488,10 @@ m88110_cmmu_flush_remote_cache(int cpu, vm_offset_t physaddr, int size)
  *	flush both Instruction and Data caches
  */
 void
-m88110_cmmu_flush_cache(vm_offset_t physaddr, int size)
+m88110_cmmu_flush_cache(paddr_t physaddr, psize_t size)
 {
 	int cpu = cpu_number();
-	
+
 	m88110_cmmu_flush_remote_cache(cpu, physaddr, size);
 }
 
@@ -513,7 +499,7 @@ m88110_cmmu_flush_cache(vm_offset_t physaddr, int size)
  *	flush Instruction caches
  */
 void
-m88110_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size)
+m88110_cmmu_flush_remote_inst_cache(int cpu, paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();	/* XXX really disable interrupts? */
 
@@ -522,7 +508,7 @@ m88110_cmmu_flush_remote_inst_cache(int cpu, vm_offset_t physaddr, int size)
 }
 
 void
-m88110_cmmu_flush_inst_cache(vm_offset_t physaddr, int size)
+m88110_cmmu_flush_inst_cache(paddr_t physaddr, psize_t size)
 {
 	int cpu = cpu_number();
 
@@ -531,10 +517,10 @@ m88110_cmmu_flush_inst_cache(vm_offset_t physaddr, int size)
 
 /*
  * flush data cache
- */ 
+ */
 void
-m88110_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size)
-{ 
+m88110_cmmu_flush_remote_data_cache(int cpu, paddr_t physaddr, psize_t size)
+{
 	int s = splhigh();	/* XXX really disable interrupts? */
 
 	mc88110_flush_data();
@@ -544,8 +530,8 @@ m88110_cmmu_flush_remote_data_cache(int cpu, vm_offset_t physaddr, int size)
 }
 
 void
-m88110_cmmu_flush_data_cache(vm_offset_t physaddr, int size)
-{ 
+m88110_cmmu_flush_data_cache(paddr_t physaddr, psize_t size)
+{
 	int cpu = cpu_number();
 
 	m88110_cmmu_flush_remote_data_cache(cpu, physaddr, size);
@@ -555,7 +541,7 @@ m88110_cmmu_flush_data_cache(vm_offset_t physaddr, int size)
  * sync dcache (and icache too)
  */
 void
-m88110_cmmu_sync_cache(vm_offset_t physaddr, int size)
+m88110_cmmu_sync_cache(paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();	/* XXX really disable interrupts? */
 
@@ -567,7 +553,7 @@ m88110_cmmu_sync_cache(vm_offset_t physaddr, int size)
 }
 
 void
-m88110_cmmu_sync_inval_cache(vm_offset_t physaddr, int size)
+m88110_cmmu_sync_inval_cache(paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();	/* XXX really disable interrupts? */
 
@@ -578,10 +564,10 @@ m88110_cmmu_sync_inval_cache(vm_offset_t physaddr, int size)
 }
 
 void
-m88110_cmmu_inval_cache(vm_offset_t physaddr, int size)
+m88110_cmmu_inval_cache(paddr_t physaddr, psize_t size)
 {
 	int s = splhigh();	/* XXX really disable interrupts? */
-	
+
 	mc88110_inval_inst();
 	mc88110_inval_data();
 	if (mc88410_present())
@@ -590,7 +576,7 @@ m88110_cmmu_inval_cache(vm_offset_t physaddr, int size)
 }
 
 void
-m88110_dma_cachectl(vm_offset_t va, int size, int op)
+m88110_dma_cachectl(vaddr_t va, vsize_t size, int op)
 {
 	switch (op) {
 	case DMA_CACHE_SYNC:
@@ -606,26 +592,14 @@ m88110_dma_cachectl(vm_offset_t va, int size, int op)
 }
 
 #ifdef DDB
+void
+m88110_cmmu_dump_config(void)
+{
+	/* dummy routine */
+}
 
-   #define VV_EX_UNMOD		0
-   #define VV_EX_MOD		1
-   #define VV_SHARED_UNMOD		2
-   #define VV_INVALID		3
-
-   #define D(UNION, LINE) \
-	((LINE) == 3 ? (UNION).field.d3 : \
-	 ((LINE) == 2 ? (UNION).field.d2 : \
-	  ((LINE) == 1 ? (UNION).field.d1 : \
-	   ((LINE) == 0 ? (UNION).field.d0 : ~0))))
-   #define VV(UNION, LINE) \
-	((LINE) == 3 ? (UNION).field.vv3 : \
-	 ((LINE) == 2 ? (UNION).field.vv2 : \
-	  ((LINE) == 1 ? (UNION).field.vv1 : \
-	   ((LINE) == 0 ? (UNION).field.vv0 : ~0))))
-
-
-   #undef VEQR_ADDR
-   #define  VEQR_ADDR 0
+#undef	VEQR_ADDR
+#define	VEQR_ADDR	0
 
 /*
  * Show (for debugging) how the given CMMU translates the given ADDRESS.
@@ -732,7 +706,7 @@ m88110_cmmu_show_translation(unsigned address,
 		value |= virtual_address.field.segment_table_index *
 			 sizeof(sdt_entry_t);
 
-		if (badwordaddr((vm_offset_t)value)) {
+		if (badwordaddr((vaddr_t)value)) {
 			DEBUG_MSG("ERROR: unable to access page at 0x%08x.\n", value);
 			return;
 		}
@@ -778,7 +752,7 @@ m88110_cmmu_show_translation(unsigned address,
 		value |= virtual_address.field.page_table_index *
 			 sizeof(pt_entry_t);
 
-		if (badwordaddr((vm_offset_t)value)) {
+		if (badwordaddr((vaddr_t)value)) {
 			DEBUG_MSG("error: unable to access page at 0x%08x.\n", value);
 			return;
 		}
@@ -820,7 +794,7 @@ m88110_cmmu_show_translation(unsigned address,
 				  virtual_address.field.page_offset, value);
 		value |= virtual_address.field.page_offset;
 
-		if (badwordaddr((vm_offset_t)value)) {
+		if (badwordaddr((vaddr_t)value)) {
 			DEBUG_MSG("error: unable to access page at 0x%08x.\n", value);
 			return;
 		}
@@ -833,21 +807,4 @@ m88110_cmmu_show_translation(unsigned address,
 
 	DEBUG_MSG("WORD at 0x%x is 0x%08x.\n", value, *(unsigned *)value);
 }
-
-
-void
-m88110_cmmu_cache_state(unsigned addr, unsigned supervisor_flag)
-{
-#ifdef not_yet
-	static char *vv_name[4] =
-	{"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"};
-	int cmmu_num;
-#endif 
-}
-
-void
-m88110_show_cmmu_info(unsigned addr)
-{
-	m88110_cmmu_cache_state(addr, 1);
-}
 #endif /* DDB */
diff --git a/sys/arch/mvme88k/mvme88k/m8820x.c b/sys/arch/mvme88k/mvme88k/m8820x.c
index 995868b88bd..e77974561b0 100644
--- a/sys/arch/mvme88k/mvme88k/m8820x.c
+++ b/sys/arch/mvme88k/mvme88k/m8820x.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m8820x.c,v 1.20 2003/10/05 19:29:15 miod Exp $	*/
+/*	$OpenBSD: m8820x.c,v 1.21 2003/10/05 20:35:26 miod Exp $	*/
 /*
  * Copyright (c) 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -70,25 +70,26 @@
 #include <machine/locore.h>
 
 #include <machine/cmmu.h>
+#include <machine/m8820x.h>
 
 #ifdef DDB
 #include <ddb/db_output.h>		/* db_printf()		*/
-#define DEBUG_MSG db_printf
-#else
-#define DEBUG_MSG printf
 #endif /* DDB */
 
+/*
+ * On some versions of the 88200, page size flushes don't work. I am using
+ * sledge hammer approach till I find for sure which ones are bad XXX nivas
+ */
+#define BROKEN_MMU_MASK
 
-/* On some versions of 88200, page size flushes don't work. I am using
- * sledge hammer approach till I find for sure which ones are bad XXX nivas */
-#define BROKEN_MMU_MASK	
+#undef	SHADOW_BATC		/* don't use BATCs for now XXX nivas */
 
 #ifdef DEBUG
 #define DB_CMMU	0x4000	/* MMU debug */
 unsigned int m8820x_debuglevel = 0;
-#define dprintf(_L_,_X_) \
+#define dprintf(_X_) \
 	do { \
-		if (m8820x_debuglevel & (_L_)) { \
+		if (m8820x_debuglevel & DB_CMMU) { \
 			unsigned int psr = disable_interrupts_return_psr(); \
 			printf("%d: ", cpu_number()); \
 			printf _X_;  \
@@ -96,26 +97,43 @@ unsigned int m8820x_debuglevel = 0;
 		} \
 	} while (0)
 #else
-#define dprintf(_L_,_X_) do { } while (0)
-#endif 
-#undef	SHADOW_BATC		/* don't use BATCs for now XXX nivas */
+#define dprintf(_X_) do { } while (0)
+#endif
+
+void m8820x_cmmu_init(void);
+void m8820x_setup_board_config(void);
+void m8820x_cpu_configuration_print(int);
+void m8820x_cmmu_shutdown_now(void);
+void m8820x_cmmu_parity_enable(void);
+unsigned m8820x_cmmu_cpu_number(void);
+void m8820x_cmmu_remote_set_sapr(unsigned, unsigned);
+void m8820x_cmmu_set_uapr(unsigned);
+void m8820x_cmmu_set_pair_batc_entry(unsigned, unsigned, unsigned);
+void m8820x_cmmu_flush_remote_tlb(unsigned, unsigned, vaddr_t, vsize_t);
+void m8820x_cmmu_flush_tlb(unsigned, vaddr_t, vsize_t);
+void m8820x_cmmu_pmap_activate(unsigned, unsigned,
+    u_int32_t i_batc[BATC_MAX], u_int32_t d_batc[BATC_MAX]);
+void m8820x_cmmu_flush_remote_cache(int, paddr_t, psize_t);
+void m8820x_cmmu_flush_cache(paddr_t, psize_t);
+void m8820x_cmmu_flush_remote_inst_cache(int, paddr_t, psize_t);
+void m8820x_cmmu_flush_inst_cache(paddr_t, psize_t);
+void m8820x_cmmu_flush_remote_data_cache(int, paddr_t, psize_t);
+void m8820x_cmmu_flush_data_cache(paddr_t, psize_t);
+void m8820x_dma_cachectl(vaddr_t, vsize_t, int);
+void m8820x_cmmu_dump_config(void);
+void m8820x_cmmu_show_translation(unsigned, unsigned, unsigned, int);
+void m8820x_show_apr(unsigned);
 
 /* This is the function table for the mc8820x CMMUs */
 struct cmmu_p cmmu8820x = {
 	m8820x_cmmu_init,
-	m8820x_show_apr,
 	m8820x_setup_board_config,
-	m8820x_setup_cmmu_config,
-	m8820x_cmmu_dump_config,
 	m8820x_cpu_configuration_print,
 	m8820x_cmmu_shutdown_now,
 	m8820x_cmmu_parity_enable,
 	m8820x_cmmu_cpu_number,
-	m8820x_cmmu_get_idr,
-	m8820x_cmmu_set_sapr,
 	m8820x_cmmu_remote_set_sapr,
 	m8820x_cmmu_set_uapr,
-	m8820x_cmmu_set_batc_entry,
 	m8820x_cmmu_set_pair_batc_entry,
 	m8820x_cmmu_flush_remote_tlb,
 	m8820x_cmmu_flush_tlb,
@@ -128,61 +146,67 @@ struct cmmu_p cmmu8820x = {
 	m8820x_cmmu_flush_data_cache,
 	m8820x_dma_cachectl,
 #ifdef DDB
-	m8820x_cmmu_get_by_mode,
+	m8820x_cmmu_dump_config,
 	m8820x_cmmu_show_translation,
-	m8820x_cmmu_cache_state,
-	m8820x_show_cmmu_info,
-#endif /* end if DDB */
+#else
+	NULL,
+	NULL,
+#endif
+#ifdef DEBUG
+	m8820x_show_apr,
+#else
+	NULL,
+#endif
 };
 
 struct cmmu_regs {
-   /* base + $000 */volatile unsigned idr; 
-   /* base + $004 */volatile unsigned scr; 
-   /* base + $008 */volatile unsigned ssr; 
-   /* base + $00C */volatile unsigned sar; 
-   /*             */unsigned padding1[0x3D]; 
-   /* base + $104 */volatile unsigned sctr; 
-   /* base + $108 */volatile unsigned pfSTATUSr; 
-   /* base + $10C */volatile unsigned pfADDRr; 
-   /*             */unsigned padding2[0x3C]; 
-   /* base + $200 */volatile unsigned sapr; 
-   /* base + $204 */volatile unsigned uapr; 
-   /*             */unsigned padding3[0x7E]; 
-   /* base + $400 */volatile unsigned bwp[8]; 
-   /*             */unsigned padding4[0xF8]; 
-   /* base + $800 */volatile unsigned cdp[4]; 
-   /*             */unsigned padding5[0x0C]; 
-   /* base + $840 */volatile unsigned ctp[4]; 
-   /*             */unsigned padding6[0x0C]; 
+   /* base + $000 */volatile unsigned idr;
+   /* base + $004 */volatile unsigned scr;
+   /* base + $008 */volatile unsigned ssr;
+   /* base + $00C */volatile unsigned sar;
+   /*             */unsigned padding1[0x3D];
+   /* base + $104 */volatile unsigned sctr;
+   /* base + $108 */volatile unsigned pfSTATUSr;
+   /* base + $10C */volatile unsigned pfADDRr;
+   /*             */unsigned padding2[0x3C];
+   /* base + $200 */volatile unsigned sapr;
+   /* base + $204 */volatile unsigned uapr;
+   /*             */unsigned padding3[0x7E];
+   /* base + $400 */volatile unsigned bwp[8];
+   /*             */unsigned padding4[0xF8];
+   /* base + $800 */volatile unsigned cdp[4];
+   /*             */unsigned padding5[0x0C];
+   /* base + $840 */volatile unsigned ctp[4];
+   /*             */unsigned padding6[0x0C];
    /* base + $880 */volatile unsigned cssp;
 
    /* The rest for the 88204 */
 #define cssp0 cssp
-   /*             */ unsigned padding7[0x03]; 
-   /* base + $890 */volatile unsigned cssp1; 
-   /*             */unsigned padding8[0x03]; 
-   /* base + $8A0 */volatile unsigned cssp2; 
-   /*             */unsigned padding9[0x03]; 
+   /*             */ unsigned padding7[0x03];
+   /* base + $890 */volatile unsigned cssp1;
+   /*             */unsigned padding8[0x03];
+   /* base + $8A0 */volatile unsigned cssp2;
+   /*             */unsigned padding9[0x03];
    /* base + $8B0 */volatile unsigned cssp3;
 };
 
 struct m8820x_cmmu {
 	struct cmmu_regs *cmmu_regs;	/* CMMU "base" area */
-	unsigned char  cmmu_cpu;	/* cpu number it is attached to */
-	unsigned char  which;		/* either INST_CMMU || DATA_CMMU */
-	unsigned char  cmmu_access;	/* either CMMU_ACS_{SUPER,USER,BOTH} */
-	unsigned char  cmmu_alive;
-#define CMMU_DEAD	0		/* This cmmu not there */
+	unsigned char	cmmu_cpu;	/* cpu number it is attached to */
+	unsigned char	which;		/* either INST_CMMU || DATA_CMMU */
+	unsigned char	cmmu_access;	/* either CMMU_ACS_{SUPER,USER,BOTH} */
+	unsigned char	cmmu_alive;
+#define CMMU_DEAD	0		/* This cmmu is not there */
 #define CMMU_AVAILABLE	1		/* It's there, but which cpu's? */
-#define CMMU_ALIVE	1		/* It's there. */
 #define CMMU_MARRIED	2		/* Know which cpu it belongs to. */
-	vm_offset_t    cmmu_addr;	/* address range */
-	vm_offset_t    cmmu_addr_mask;	/* address mask */
-	int            cmmu_addr_match;	/* return value of address comparison */
+	vaddr_t		cmmu_addr;	/* address range */
+	vaddr_t		cmmu_addr_mask;	/* address mask */
+	int		cmmu_addr_match;/* return value of address comparison */
 #ifdef SHADOW_BATC
-	unsigned batc[8];
+	unsigned batc[BATC_MAX];
 #endif
-}; 
+};
+
 /*
  * We rely upon and use INST_CMMU == 0 and DATA_CMMU == 1
  */
@@ -190,32 +214,33 @@ struct m8820x_cmmu {
 error("ack gag barf!");
 #endif
 
-/*
- * CMMU(cpu,data) Is the cmmu struct for the named cpu's indicated cmmu.
- * REGS(cpu,data) is the actual register structure.
- */
-
+#ifdef SHADOW_BATC
+/* CMMU(cpu,data) is the cmmu struct for the named cpu's indicated cmmu.  */
 #define CMMU(cpu, data) cpu_cmmu[(cpu)].pair[(data)?DATA_CMMU:INST_CMMU]
-#define REGS(cpu, data) (*CMMU(cpu, data)->cmmu_regs)
+#endif
 
-/* 
- * This lock protects the cmmu SAR and SCR's; other ports 
- * can be accessed without locking it 
- *
- * May be used from "db_interface.c".
- */
+/* local prototypes */
+void m8820x_cmmu_set(int, unsigned, int, int, int, int, vaddr_t);
+void m8820x_cmmu_sync_cache(paddr_t, psize_t);
+void m8820x_cmmu_sync_inval_cache(paddr_t, psize_t);
+void m8820x_cmmu_inval_cache(paddr_t, psize_t);
 
-int      vme188_config;
+/* Flags passed to m8820x_cmmu_set() */
+#define MODE_VAL		0x01
+#define ACCESS_VAL		0x02
+#define ADDR_VAL		0x04
 
-/* local prototypes */
-unsigned m8820x_cmmu_get(int mmu, int reg);
-void m8820x_cmmu_store(int, int, unsigned);
-void m8820x_cmmu_set(int, unsigned, int, int, int, int, vm_offset_t);
-void m8820x_cmmu_sync_cache(vm_offset_t, int);
-void m8820x_cmmu_sync_inval_cache(vm_offset_t, int);
-void m8820x_cmmu_inval_cache(vm_offset_t, int);
-int m8820x_cmmu_alive(int);
+#define	m8820x_cmmu_store(mmu, reg, val) \
+	*(unsigned *volatile)((reg) + (char *)(m8820x_cmmu[(mmu)].cmmu_regs)) =\
+	    (val)
+
+#define m8820x_cmmu_get(mmu, reg) \
+	*(unsigned *volatile)(reg + (char *)(m8820x_cmmu[mmu].cmmu_regs))
 
+#define m8820x_cmmu_alive(mmu) \
+	(m8820x_cmmu[mmu].cmmu_alive != CMMU_DEAD)
+
+#ifdef DEBUG
 void
 m8820x_show_apr(value)
 	unsigned value;
@@ -231,6 +256,7 @@ m8820x_show_apr(value)
 		printf(", valid");
 	printf("\n");
 }
+#endif
 
 /*----------------------------------------------------------------
  * The cmmu.c module was initially designed for the Omron Luna 88K
@@ -280,16 +306,16 @@ struct cmmu_strategy {
 	{ CMMU_SPLIT_ADDRESS,  CMMU_SPLIT_ADDRESS}  /* CPU 3 */
 };
 
+#ifdef MVME188
 /*
  * The following list of structs describe the different
  * MVME188 configurations which are supported by this module.
  */
-struct board_config {
+const struct board_config {
 	int supported;
 	int ncpus;
 	int ncmmus;
-} bd_config[] =
-{
+} bd_config[] = {
 	/* sup, CPU MMU */
 	{  1,  4,  8}, /* 4P128 - 4P512 */
 	{  1,  2,  8}, /* 2P128 - 2P512 */
@@ -308,6 +334,7 @@ struct board_config {
 	{  0, -1, -1},
 	{  0, -1, -1}
 };
+#endif
 
 /*
  * Structure for accessing MMUS properly.
@@ -315,40 +342,43 @@ struct board_config {
 
 struct m8820x_cmmu m8820x_cmmu[MAX_CMMUS] =
 {
-	/* addr    cpu       mode           access
-      alive   addr mask */
-	{(void *)VME_CMMU_I0, -1, INST_CMMU, CMMU_ACS_BOTH, 
-		CMMU_DEAD, 0, 0},                                 
-	{(void *)VME_CMMU_D0, -1, DATA_CMMU, CMMU_ACS_BOTH,       
-		CMMU_DEAD, 0, 0},                                 
-	{(void *)VME_CMMU_I1, -1, INST_CMMU, CMMU_ACS_BOTH,       
-		CMMU_DEAD, 0, 0},                                 
-	{(void *)VME_CMMU_D1, -1, DATA_CMMU, CMMU_ACS_BOTH,       
-		CMMU_DEAD, 0, 0},                                 
-	{(void *)VME_CMMU_I2, -1, INST_CMMU, CMMU_ACS_BOTH,
-		CMMU_DEAD, 0, 0},
-	{(void *)VME_CMMU_D2, -1, DATA_CMMU, CMMU_ACS_BOTH,
-		CMMU_DEAD, 0, 0},
-	{(void *)VME_CMMU_I3, -1, INST_CMMU, CMMU_ACS_BOTH,
-		CMMU_DEAD, 0, 0},
-	{(void *)VME_CMMU_D3, -1, DATA_CMMU, CMMU_ACS_BOTH,
-		CMMU_DEAD, 0, 0}
+	/* address, cpu, mode, access, alive, addr, mask */
+	{(struct cmmu_regs *)VME_CMMU_I0, -1, INST_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0},
+	{(struct cmmu_regs *)VME_CMMU_D0, -1, DATA_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0},
+	{(struct cmmu_regs *)VME_CMMU_I1, -1, INST_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0},
+	{(struct cmmu_regs *)VME_CMMU_D1, -1, DATA_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0},
+	{(struct cmmu_regs *)VME_CMMU_I2, -1, INST_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0},
+	{(struct cmmu_regs *)VME_CMMU_D2, -1, DATA_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0},
+	{(struct cmmu_regs *)VME_CMMU_I3, -1, INST_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0},
+	{(struct cmmu_regs *)VME_CMMU_D3, -1, DATA_CMMU, CMMU_ACS_BOTH, CMMU_DEAD, 0, 0}
 };
 
 struct cpu_cmmu {
 	struct m8820x_cmmu *pair[2];
 } cpu_cmmu[MAX_CPUS];
 
-void 
+/*
+ * This routine sets up the CPU/CMMU configuration.
+ */
+void
 m8820x_setup_board_config()
 {
-	unsigned long *volatile whoami;
+	int num, cmmu_num;
+	int vme188_config;
+	struct cmmu_regs *cr;
+#ifdef MVME188
+	int val1, val2;
+	u_int32_t *volatile whoami;
+	unsigned long *volatile pcnfa;
+	unsigned long *volatile pcnfb;
+#endif
 
 	master_cpu = 0;	/* temp to get things going */
 	switch (brdtyp) {
 #ifdef MVME187
 	case BRD_187:
-		vme188_config = 10; /* There is no WHOAMI reg on MVME187 - fake it... */
+		/* There is no WHOAMI reg on MVME187 - fake it... */
+		vme188_config = 10;
 		m8820x_cmmu[0].cmmu_regs = (void *)SBC_CMMU_I;
 		m8820x_cmmu[0].cmmu_cpu = 0;
 		m8820x_cmmu[1].cmmu_regs = (void *)SBC_CMMU_D;
@@ -365,16 +395,19 @@ m8820x_setup_board_config()
 #endif /* MVME187 */
 #ifdef MVME188
 	case BRD_188:
-		whoami = (unsigned long *volatile)MVME188_WHOAMI;
+		whoami = (u_int32_t *volatile)MVME188_WHOAMI;
 		vme188_config = (*whoami & 0xf0) >> 4;
-		dprintf(DB_CMMU,("m8820x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x vme188_config = %d\n",
+		dprintf(("m8820x_setup_board_config: WHOAMI @ 0x%08x holds value 0x%08x vme188_config = %d\n",
 				 whoami, *whoami, vme188_config));
 		max_cpus = bd_config[vme188_config].ncpus;
 		max_cmmus = bd_config[vme188_config].ncmmus;
 		break;
 #endif /* MVME188 */
 	}
+
 	cpu_cmmu_ratio = max_cmmus / max_cpus;
+
+#ifdef MVME188
 	if (bd_config[vme188_config].supported) {
 		/* 187 has a fixed configuration, no need to print it */
 		if (brdtyp == BRD_188) {
@@ -382,82 +415,67 @@ m8820x_setup_board_config()
 			    "(%d CPUs %d CMMUs)\n",
 			    vme188_config, max_cpus, max_cmmus);
 		}
-		m8820x_setup_cmmu_config();
 	} else {
 		panic("unsupported MVME%x board configuration "
 		    "#%X (%d CPUs %d CMMUs)",
 		    brdtyp, vme188_config, max_cpus, max_cmmus);
 	}
-}
-
-/*
- * This routine sets up the CPU/CMMU tables used in the
- * motorola/m88k/m88100/cmmu.c module.
- */
-void 
-m8820x_setup_cmmu_config()
-{
-	register int num, cmmu_num;
-#ifdef MVME188
-	register int val1, val2;
-	unsigned long *volatile pcnfa;
-	unsigned long *volatile pcnfb;
-#endif 
-
-	dprintf(DB_CMMU,("m8820x_setup_cmmu_config: initializing with %d CPU(s) and %d CMMU(s)\n",
-			 max_cpus, max_cmmus));
+#endif
 
 	/*
 	 * Probe for available MMUs
 	 */
-	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++)
-		if (!badwordaddr((vm_offset_t)m8820x_cmmu[cmmu_num].cmmu_regs)) {
+	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
+		cr = m8820x_cmmu[cmmu_num].cmmu_regs;
+		if (!badwordaddr((vaddr_t)cr)) {
 			union cpupid id;
 
-			id.cpupid = m8820x_cmmu[cmmu_num].cmmu_regs->idr;
+			id.cpupid = cr->idr;
+#ifdef DIAGNOSTIC
 			if (id.m88200.type != M88200_ID &&
 			    id.m88200.type != M88204_ID) {
-				printf("WARNING: non M8820x circuit found at CMMU address 0x%08x\n",
-				       m8820x_cmmu[cmmu_num].cmmu_regs);
-				continue;
+				printf("WARNING: non M8820x circuit found "
+				    "at CMMU address %p\n", cr);
+				continue;	/* will probably die quickly */
 			}
-			m8820x_cmmu[cmmu_num].cmmu_alive = CMMU_ALIVE;
-			dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CMMU %d found at 0x%08x\n",
-					 cmmu_num, m8820x_cmmu[cmmu_num].cmmu_regs));
+#endif
+			m8820x_cmmu[cmmu_num].cmmu_alive = CMMU_AVAILABLE;
+			dprintf(("m8820x_setup_cmmu_config: CMMU %d found at %p\n",
+			    cmmu_num, cr));
 		}
+	}
 
-		/*
-		 * Now that we know which CMMUs are there, let's report on which
-		 * CPU/CMMU sets seem complete (hopefully all)
-		 */
+	/*
+	 * Now that we know which CMMUs are there, let's report on which
+	 * CPU/CMMU sets seem complete (hopefully all)
+	 */
 	for (num = 0; num < max_cpus; num++) {
-		register int i;
+		int i;
 		union cpupid id;
 
 		for (i = 0; i < cpu_cmmu_ratio; i++) {
-			dprintf(DB_CMMU,("cmmu_init: testing CMMU %d for CPU %d\n",
-					 num*cpu_cmmu_ratio+i, num));
-			if (!m8820x_cmmu_alive(num*cpu_cmmu_ratio + i)) {
+			dprintf(("cmmu_init: testing CMMU %d for CPU %d\n",
+			    num * cpu_cmmu_ratio + i, num));
+#ifdef DIAGNOSTIC
+			if (!m8820x_cmmu_alive(num * cpu_cmmu_ratio + i)) {
 				printf("CMMU %d attached to CPU %d is not working\n",
-					 num*cpu_cmmu_ratio+i, num);
-				panic("m8820x_setup_cmmu_config");
+				    num * cpu_cmmu_ratio + i, num);
+				continue;	/* will probably die quickly */
 			}
+#endif
 		}
 		cpu_sets[num] = 1;   /* This cpu installed... */
-		id.cpupid = m8820x_cmmu[num*cpu_cmmu_ratio].cmmu_regs->idr;
+		id.cpupid = m8820x_cmmu[num * cpu_cmmu_ratio].cmmu_regs->idr;
 
-		if (id.m88200.type == M88204_ID)
-			printf("CPU%d is attached with %d MC88204 CMMUs\n",
-			       num, cpu_cmmu_ratio);
-		else
-			printf("CPU%d is attached with %d MC88200 CMMUs\n",
-			       num, cpu_cmmu_ratio);
+		printf("CPU%d is attached with %d MC%x CMMUs\n",
+		    num, cpu_cmmu_ratio,
+		    id.m88200.type == M88204_ID ? 0x88204 : 0x88200);
 	}
 
 	for (num = 0; num < max_cpus; num++) {
 		cpu_cmmu_strategy[num].inst &= CMMU_SPLIT_MASK;
 		cpu_cmmu_strategy[num].data &= CMMU_SPLIT_MASK;
-		dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n",
+		dprintf(("m8820x_setup_cmmu_config: CPU %d inst strat %d data strat %d\n",
 				 num, cpu_cmmu_strategy[num].inst, cpu_cmmu_strategy[num].data));
 	}
 
@@ -465,13 +483,15 @@ m8820x_setup_cmmu_config()
 	/*
 	 * These configurations have hardwired CPU/CMMU configurations.
 	 */
+#ifdef MVME188
 	case CONFIG_0:
 	case CONFIG_5:
+#endif
 	case CONFIG_A:
-		dprintf(DB_CMMU,("m8820x_setup_cmmu_config: resetting strategies\n"));
+		dprintf(("m8820x_setup_cmmu_config: resetting strategies\n"));
 		for (num = 0; num < max_cpus; num++)
-			cpu_cmmu_strategy[num].inst = cpu_cmmu_strategy[num].data =
-						      CMMU_SPLIT_ADDRESS;
+			cpu_cmmu_strategy[num].inst = CMMU_SPLIT_ADDRESS;
+			cpu_cmmu_strategy[num].data = CMMU_SPLIT_ADDRESS;
 		break;
 #ifdef MVME188
 	/*
@@ -480,35 +500,40 @@ m8820x_setup_cmmu_config()
 	case CONFIG_1:
 		pcnfa = (unsigned long *volatile)MVME188_PCNFA;
 		pcnfb = (unsigned long *volatile)MVME188_PCNFB;
-		val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data;
-		val2 = (cpu_cmmu_strategy[1].inst << 2) | cpu_cmmu_strategy[1].data;
+		val1 = (cpu_cmmu_strategy[0].inst << 2) |
+		    cpu_cmmu_strategy[0].data;
+		val2 = (cpu_cmmu_strategy[1].inst << 2) |
+		    cpu_cmmu_strategy[1].data;
 		*pcnfa = val1;
 		*pcnfb = val2;
-		dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
+		dprintf(("m8820x_setup_cmmu_config: 2P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
 		break;
 	case CONFIG_2:
 		pcnfa = (unsigned long *volatile)MVME188_PCNFA;
 		pcnfb = (unsigned long *volatile)MVME188_PCNFB;
-		val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].inst;
-		val2 = (cpu_cmmu_strategy[0].data << 2) | cpu_cmmu_strategy[0].data;
+		val1 = (cpu_cmmu_strategy[0].inst << 2) |
+		    cpu_cmmu_strategy[0].inst;
+		val2 = (cpu_cmmu_strategy[0].data << 2) |
+		    cpu_cmmu_strategy[0].data;
 		*pcnfa = val1;
 		*pcnfb = val2;
-		dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
+		dprintf(("m8820x_setup_cmmu_config: 1P128: PCNFA = 0x%x, PCNFB = 0x%x\n", val1, val2));
 		break;
 	case CONFIG_6:
 		pcnfa = (unsigned long *volatile)MVME188_PCNFA;
-		val1 = (cpu_cmmu_strategy[0].inst << 2) | cpu_cmmu_strategy[0].data;
+		val1 = (cpu_cmmu_strategy[0].inst << 2) |
+		    cpu_cmmu_strategy[0].data;
 		*pcnfa = val1;
-		dprintf(DB_CMMU,("m8820x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1));
+		dprintf(("m8820x_setup_cmmu_config: 1P64: PCNFA = 0x%x\n", val1));
 		break;
 #endif /* MVME188 */
 	default:
-		panic("m8820x_setup_cmmu_config");
+		panic("m8820x_setup_cmmu_config: unsupported configuration");
 		break;
 	}
 
 #ifdef MVME188
-	dprintf(DB_CMMU,("m8820x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb));
+	dprintf(("m8820x_setup_cmmu_config: PCNFA = 0x%x, PCNFB = 0x%x\n", *pcnfa, *pcnfb));
 #endif /* MVME188 */
 
 	/*
@@ -516,9 +541,9 @@ m8820x_setup_cmmu_config()
 	 */
 	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
 		m8820x_cmmu[cmmu_num].cmmu_cpu =
-		(int) (((float) cmmu_num) * ((float) max_cpus) / ((float) max_cmmus));
-		dprintf(DB_CMMU,("m8820x_setup_cmmu_config: CMMU %d connected with CPU %d\n",
-				 cmmu_num, m8820x_cmmu[cmmu_num].cmmu_cpu));
+		(cmmu_num * max_cpus) / max_cmmus;
+		dprintf(("m8820x_setup_cmmu_config: CMMU %d connected with CPU %d\n",
+		    cmmu_num, m8820x_cmmu[cmmu_num].cmmu_cpu));
 	}
 
 	/*
@@ -529,7 +554,7 @@ m8820x_setup_cmmu_config()
 		 * We don't set up anything for the hardwired configurations.
 		 */
 		if (cpu_cmmu_ratio == 2) {
-			m8820x_cmmu[cmmu_num].cmmu_addr =
+			m8820x_cmmu[cmmu_num].cmmu_addr = 0;
 			m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0;
 			m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
 			m8820x_cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH;
@@ -541,29 +566,32 @@ m8820x_setup_cmmu_config()
 		 * matches.
 		 */
 		switch ((m8820x_cmmu[cmmu_num].which == INST_CMMU) ?
-			cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
-			cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) {
+		    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
+		    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) {
 		case CMMU_SPLIT_ADDRESS:
-			m8820x_cmmu[cmmu_num].cmmu_addr = ((cmmu_num & 0x2) ^ 0x2) << 11;
+			m8820x_cmmu[cmmu_num].cmmu_addr =
+			    ((cmmu_num & 0x2) ^ 0x2) << 11;
 			m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_A12_MASK;
 			m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
 			break;
 		case CMMU_SPLIT_SPV:
-			m8820x_cmmu[cmmu_num].cmmu_addr =
+			m8820x_cmmu[cmmu_num].cmmu_addr = 0;
 			m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0;
 			m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
 			break;
 		case CMMU_SPLIT_SRAM_ALL:
 			m8820x_cmmu[cmmu_num].cmmu_addr = CMMU_SRAM;
 			m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK;
-			m8820x_cmmu[cmmu_num].cmmu_addr_match = (cmmu_num & 0x2) ? 1 : 0;
+			m8820x_cmmu[cmmu_num].cmmu_addr_match =
+			    (cmmu_num & 0x2) ? 1 : 0;
 			break;
 		case CMMU_SPLIT_SRAM_SPV:
 			if (cmmu_num & 0x2) {
 				m8820x_cmmu[cmmu_num].cmmu_addr = CMMU_SRAM;
-				m8820x_cmmu[cmmu_num].cmmu_addr_mask = CMMU_SRAM_MASK;
+				m8820x_cmmu[cmmu_num].cmmu_addr_mask =
+				    CMMU_SRAM_MASK;
 			} else {
-				m8820x_cmmu[cmmu_num].cmmu_addr =
+				m8820x_cmmu[cmmu_num].cmmu_addr = 0;
 				m8820x_cmmu[cmmu_num].cmmu_addr_mask = 0;
 			}
 			m8820x_cmmu[cmmu_num].cmmu_addr_match = 1;
@@ -572,12 +600,13 @@ m8820x_setup_cmmu_config()
 
 		/*
 		 * For MVME188 single processors, we've got to look at A14.
-		 * This bit splits the CMMUs independent of the enabled strategy.
+		 * This bit splits the CMMUs independent of the enabled strategy
 		 *
 		 * NOT TESTED!!! - em
 		 */
-		if (cpu_cmmu_ratio > 4) {
-			m8820x_cmmu[cmmu_num].cmmu_addr |= ((cmmu_num & 0x4) ^ 0x4) << 12;
+		if (cpu_cmmu_ratio > 4) {	/* XXX only handles 1P128!!! */
+			m8820x_cmmu[cmmu_num].cmmu_addr |=
+			    ((cmmu_num & 0x4) ^ 0x4) << 12;
 			m8820x_cmmu[cmmu_num].cmmu_addr_mask |= CMMU_A14_MASK;
 		}
 
@@ -585,15 +614,15 @@ m8820x_setup_cmmu_config()
 		 * Next we cope with the various access modes.
 		 */
 		switch ((m8820x_cmmu[cmmu_num].which == INST_CMMU) ?
-			cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
-			cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) {
+		    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
+		    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data) {
 		case CMMU_SPLIT_SPV:
 			m8820x_cmmu[cmmu_num].cmmu_access =
-			(cmmu_num & 0x2 ) ? CMMU_ACS_USER : CMMU_ACS_SUPER;
+			    (cmmu_num & 0x2 ) ? CMMU_ACS_USER : CMMU_ACS_SUPER;
 			break;
 		case CMMU_SPLIT_SRAM_SPV:
 			m8820x_cmmu[cmmu_num].cmmu_access =
-			(cmmu_num & 0x2 ) ? CMMU_ACS_SUPER : CMMU_ACS_BOTH;
+			    (cmmu_num & 0x2 ) ? CMMU_ACS_SUPER : CMMU_ACS_BOTH;
 			break;
 		default:
 			m8820x_cmmu[cmmu_num].cmmu_access = CMMU_ACS_BOTH;
@@ -602,106 +631,73 @@ m8820x_setup_cmmu_config()
 	}
 }
 
+#ifdef DDB
+
 #ifdef MVME188
-static char *cmmu_strat_string[] = {
+const char *cmmu_strat_string[] = {
 	"address split ",
 	"user/spv split",
 	"spv SRAM split",
 	"all SRAM split"
 };
-#endif 
+#endif
 
-void 
+void
 m8820x_cmmu_dump_config()
 {
 #ifdef MVME188
 	unsigned long *volatile pcnfa;
 	unsigned long *volatile pcnfb;
-	register int cmmu_num;
-#endif /* MVME188 */
-
-	DEBUG_MSG("Current CPU/CMMU configuration:\n\n");
+	int cmmu_num;
 
-	switch (brdtyp) {
 #ifdef MVME187
-	case BRD_187:
-		DEBUG_MSG("VME1x7 split mode\n\n");
-#endif /* MVME187 */
-#ifdef MVME188
-	case BRD_188:
-		pcnfa = (unsigned long *volatile)MVME188_PCNFA;
-		pcnfb = (unsigned long *volatile)MVME188_PCNFB;
-		DEBUG_MSG("VME188 address decoder: PCNFA = 0x%1x, PCNFB = 0x%1x\n\n", *pcnfa & 0xf, *pcnfb & 0xf);
-		for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
-			DEBUG_MSG("CMMU #%d: %s CMMU for CPU %d:\n Strategy: %s\n %s access addr 0x%08x mask 0x%08x match %s\n",
-				  cmmu_num,
-				  (m8820x_cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data",
-				  m8820x_cmmu[cmmu_num].cmmu_cpu,
-				  cmmu_strat_string[(m8820x_cmmu[cmmu_num].which == INST_CMMU) ?
-						    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
-						    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data],
-				  (m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ?   "User and spv" :
-				  ((m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User        " :
-				   "Supervisor  "),
-				  m8820x_cmmu[cmmu_num].cmmu_addr,
-				  m8820x_cmmu[cmmu_num].cmmu_addr_mask,
-				  m8820x_cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE");
-		}
-#endif /* MVME188 */
-	}
-}
-
-/* To be implemented as a macro for speedup - XXX-em */
-void
-m8820x_cmmu_store(mmu, reg, val)
-	int mmu, reg;
-	unsigned val;
-{
-	*(unsigned *volatile)(reg + (char *)(m8820x_cmmu[mmu].cmmu_regs)) = val;
-}
-
-int 
-m8820x_cmmu_alive(mmu)
-	int mmu;
-{
-	return (m8820x_cmmu[mmu].cmmu_alive == CMMU_ALIVE);
-}
+	if (brdtyp != BRD_188)
+		return;
+#endif
 
-unsigned 
-m8820x_cmmu_get(mmu, reg)
-	int mmu, reg;
-{
-	return *(unsigned *volatile)(reg + (char *)(m8820x_cmmu[mmu].cmmu_regs));
+	db_printf("Current CPU/CMMU configuration:\n");
+	pcnfa = (unsigned long *volatile)MVME188_PCNFA;
+	pcnfb = (unsigned long *volatile)MVME188_PCNFB;
+	db_printf("VME188 address decoder: PCNFA = 0x%1x, PCNFB = 0x%1x\n\n",
+	    *pcnfa & 0xf, *pcnfb & 0xf);
+	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
+		db_printf("CMMU #%d: %s CMMU for CPU %d:\n Strategy: %s\n %s access addr 0x%08x mask 0x%08x match %s\n",
+		  cmmu_num,
+		  (m8820x_cmmu[cmmu_num].which == INST_CMMU) ? "inst" : "data",
+		  m8820x_cmmu[cmmu_num].cmmu_cpu,
+		  cmmu_strat_string[(m8820x_cmmu[cmmu_num].which == INST_CMMU) ?
+		    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].inst :
+		    cpu_cmmu_strategy[m8820x_cmmu[cmmu_num].cmmu_cpu].data],
+		  (m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_BOTH) ?   "User and spv" :
+		  ((m8820x_cmmu[cmmu_num].cmmu_access == CMMU_ACS_USER) ? "User        " :
+		   "Supervisor  "),
+		  m8820x_cmmu[cmmu_num].cmmu_addr,
+		  m8820x_cmmu[cmmu_num].cmmu_addr_mask,
+		  m8820x_cmmu[cmmu_num].cmmu_addr_match ? "TRUE" : "FALSE");
+	}
+#endif /* MVME188 */
 }
+#endif	/* DDB */
 
 /*
  * This function is called by the MMU module and pokes values
  * into the CMMU's registers.
  */
-void 
+void
 m8820x_cmmu_set(reg, val, flags, num, mode, access, addr)
 	int reg;
 	unsigned val;
 	int flags, num, mode, access;
-	vm_offset_t addr;
+	vaddr_t addr;
 {
-	register int mmu;
-
-	if (flags & NUM_CMMU) {
-		/*
-		 * Special case: user supplied CMMU number directly as argument.
-		 * Simply store the value away.
-		 */
-		/* assert(num < max_cmmus); */
-		m8820x_cmmu_store(num, reg, val);
-		return;
-	}
+	int mmu;
 
 	/*
 	 * We scan all CMMUs to find the matching ones and store the
 	 * values there.
 	 */
-	for (mmu = num*cpu_cmmu_ratio; mmu < (num+1)*cpu_cmmu_ratio; mmu++) {
+	for (mmu = num * cpu_cmmu_ratio;
+	    mmu < (num + 1) * cpu_cmmu_ratio; mmu++) {
 		if (((flags & MODE_VAL)) &&
 		    (m8820x_cmmu[mmu].which != mode))
 			continue;
@@ -719,28 +715,7 @@ m8820x_cmmu_set(reg, val, flags, num, mode, access, addr)
 	}
 }
 
-#ifdef DDB
-/*
- * Used by DDB for cache probe functions
- */
-unsigned 
-m8820x_cmmu_get_by_mode(cpu, mode)
-	int cpu, mode;
-{
-	register int mmu;
-
-	for (mmu = cpu*cpu_cmmu_ratio; mmu < (cpu+1)*cpu_cmmu_ratio; mmu++)
-		if (m8820x_cmmu[mmu].which == mode)
-			return mmu;
-	printf("can't figure out first %s CMMU for CPU %d\n",
-	       (mode == DATA_CMMU) ? "data" : "instruction", cpu);
-	panic("m8820x_cmmu_get_by_mode");
-	/* NOTREACHED */
-	return(0);
-}
-#endif
-
-static char *mmutypes[8] = {
+const char *mmutypes[8] = {
 	"Unknown (0)",
 	"Unknown (1)",
 	"Unknown (2)",
@@ -756,7 +731,7 @@ static char *mmutypes[8] = {
  * number and master/slave status . Should be called first
  * by the master, before the slaves are started.
 */
-void 
+void
 m8820x_cpu_configuration_print(master)
 	int master;
 {
@@ -781,15 +756,17 @@ m8820x_cpu_configuration_print(master)
 
 	printf("M88100 rev 0x%x", procvers);
 #if 0	/* not useful yet */
+#ifdef MVME188
 	if (brdtyp == BRD_188)
 		printf(", %s", master ? "master" : "slave");
 #endif
+#endif
 	printf(", %d CMMU", cpu_cmmu_ratio);
 
 	for (mmu = cpu * cpu_cmmu_ratio; mmu < (cpu + 1) * cpu_cmmu_ratio;
 	    mmu++) {
 		int idr = m8820x_cmmu_get(mmu, CMMU_IDR);
-		int mmuid = (0xe00000 & idr)>>21;
+		int mmuid = (0xe00000 & idr) >> 21;
 		int access = m8820x_cmmu[mmu].cmmu_access;
 
 		if ((mmu - cpu * cpu_cmmu_ratio) % 2 == 0)
@@ -834,57 +811,54 @@ m8820x_cmmu_init()
 	unsigned tmp, cmmu_num;
 	union cpupid id;
 	int cpu;
+	struct cmmu_regs *cr;
 
 	for (cpu = 0; cpu < max_cpus; cpu++) {
-		cpu_cmmu[cpu].pair[INST_CMMU] = cpu_cmmu[cpu].pair[DATA_CMMU] = 0;
+		cpu_cmmu[cpu].pair[INST_CMMU] = 0;
+		cpu_cmmu[cpu].pair[DATA_CMMU] = 0;
 	}
 
-	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++){
+	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
 		if (m8820x_cmmu_alive(cmmu_num)) {
-			id.cpupid = m8820x_cmmu[cmmu_num].cmmu_regs->idr;
+			cr = m8820x_cmmu[cmmu_num].cmmu_regs;
+			id.cpupid = cr->idr;
 
 			cpu_cmmu[m8820x_cmmu[cmmu_num].cmmu_cpu].pair[m8820x_cmmu[cmmu_num].which] =
-			&m8820x_cmmu[cmmu_num];
+			    &m8820x_cmmu[cmmu_num];
+
 			/*
 			 * Reset cache data....
 			 * as per M88200 Manual (2nd Ed.) section 3.11.
 			 */
 			for (tmp = 0; tmp < 255; tmp++) {
-				m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp << 4;
-				m8820x_cmmu[cmmu_num].cmmu_regs->cssp = 0x3f0ff000;
+				cr->sar = tmp << 4;
+				cr->cssp = 0x3f0ff000;
 			}
 
 			/* 88204 has additional cache to clear */
 			if (id.m88200.type == M88204_ID) {
 				for (tmp = 0; tmp < 255; tmp++) {
-					m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
-					m8820x_cmmu[cmmu_num].cmmu_regs->cssp1 = 0x3f0ff000;
+					cr->sar = tmp << 4;
+					cr->cssp1 = 0x3f0ff000;
 				}
 				for (tmp = 0; tmp < 255; tmp++) {
-					m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
-					m8820x_cmmu[cmmu_num].cmmu_regs->cssp2 = 0x3f0ff000;
+					cr->sar = tmp << 4;
+					cr->cssp2 = 0x3f0ff000;
 				}
 				for (tmp = 0; tmp < 255; tmp++) {
-					m8820x_cmmu[cmmu_num].cmmu_regs->sar = tmp<<4;
-					m8820x_cmmu[cmmu_num].cmmu_regs->cssp3 = 0x3f0ff000;
+					cr->sar = tmp << 4;
+					cr->cssp3 = 0x3f0ff000;
 				}
 			}
 
 			/*
 			 * Set the SCTR, SAPR, and UAPR to some known state
-			 * (I don't trust the reset to do it).
 			 */
-			tmp = 0 & ~(
-			    CMMU_SCTR_PE |   /* not parity enable */
-			    CMMU_SCTR_SE | /* not snoop enable */
-			    CMMU_SCTR_PR);  /* not priority arbitration */
-			m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp;
-
-			tmp = ((0x00000 << PG_BITS) | AREA_D_WT | AREA_D_G |
+			cr->sctr &=
+			    ~(CMMU_SCTR_PE | CMMU_SCTR_SE | CMMU_SCTR_PR);
+			cr->sapr = cr->uapr =
+			    ((0x00000 << PG_BITS) | AREA_D_WT | AREA_D_G |
 			    AREA_D_CI) & ~AREA_D_TE;
-			m8820x_cmmu[cmmu_num].cmmu_regs->sapr =
-			m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp;
-
 
 #ifdef SHADOW_BATC
 			m8820x_cmmu[cmmu_num].batc[0] =
@@ -896,64 +870,53 @@ m8820x_cmmu_init()
 			m8820x_cmmu[cmmu_num].batc[6] =
 			m8820x_cmmu[cmmu_num].batc[7] = 0;
 #endif
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[0] = 
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[1] = 
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[2] = 
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[3] = 
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[4] = 
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[5] = 
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[6] = 
-			m8820x_cmmu[cmmu_num].cmmu_regs->bwp[7] = 0;
-			m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_CACHE_INV_ALL;
-			m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_SUPER_ALL;
-			m8820x_cmmu[cmmu_num].cmmu_regs->scr = CMMU_FLUSH_USER_ALL;
+			cr->bwp[0] = cr->bwp[1] = cr->bwp[2] = cr->bwp[3] =
+			cr->bwp[4] = cr->bwp[5] = cr->bwp[6] = cr->bwp[7] = 0;
+			cr->scr = CMMU_FLUSH_CACHE_INV_ALL;
+			cr->scr = CMMU_FLUSH_SUPER_ALL;
+			cr->scr = CMMU_FLUSH_USER_ALL;
 		}
 	}
+
+#ifdef MVME188
 	/*
-	 * Enable snooping...
+	 * Enable snooping on MVME188 only.
+	 * Snooping is enabled for instruction cmmus as well so that
+	 * we can have breakpoints, modify code, etc.
 	 */
-	for (cpu = 0; cpu < max_cpus; cpu++) {
-		if (!cpu_sets[cpu])
-			continue;
+	if (brdtyp == BRD_188) {
+		for (cpu = 0; cpu < max_cpus; cpu++) {
+			if (!cpu_sets[cpu])
+				continue;
 
-		/*
-		 * Enable snooping.
-		 * We enable it for instruction cmmus as well so that we can have
-		 * breakpoints, etc, and modify code.
-		 */
-		if (brdtyp == BRD_188) {
-			tmp = CMMU_SCTR_SE & ~(CMMU_SCTR_PE | CMMU_SCTR_PR);
-		} else {
-			tmp = 0 & ~(CMMU_SCTR_PE | CMMU_SCTR_PR);
-		}
-		m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, DATA_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SCTR, tmp, 0, cpu, INST_CMMU, 0, 0);
+			m8820x_cmmu_set(CMMU_SCTR, CMMU_SCTR_SE, 0, cpu,
+			    DATA_CMMU, 0, 0);
+			m8820x_cmmu_set(CMMU_SCTR, CMMU_SCTR_SE, 0, cpu,
+			    INST_CMMU, 0, 0);
 
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL,
-			      cpu, DATA_CMMU, CMMU_ACS_SUPER, 0);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL,
-			      cpu, INST_CMMU, CMMU_ACS_SUPER, 0);
+			m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL,
+			    ACCESS_VAL, cpu, DATA_CMMU, CMMU_ACS_SUPER, 0);
+			/* Icache gets flushed just below */
+		}
 	}
+#endif
 
 	/*
-	 * Turn on some cache.
+	 * Enable instruction cache.
+	 * Data cache can not be enabled at this point, because some device
+	 * addresses can never be cached, and the no-caching zones are not
+	 * set up yet.
 	 */
 	for (cpu = 0; cpu < max_cpus; cpu++) {
 		if (!cpu_sets[cpu])
 			continue;
-		/*
-		 * Enable some caching for the instruction stream.
-		 * Can't cache data yet 'cause device addresses can never
-		 * be cached, and we don't have those no-caching zones
-		 * set up yet....
-		 */
+
 		tmp = ((0x00000 << PG_BITS) | AREA_D_WT | AREA_D_G)
 		    & ~(AREA_D_CI | AREA_D_TE);
-		m8820x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
 
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL, ACCESS_VAL|MODE_VAL,
-			      cpu, DATA_CMMU, CMMU_ACS_SUPER, 0);
+		m8820x_cmmu_set(CMMU_SAPR, tmp, MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_SUPER_ALL,
+		    ACCESS_VAL, cpu, 0, CMMU_ACS_SUPER, 0);
 	}
 }
 
@@ -963,56 +926,42 @@ m8820x_cmmu_init()
 void
 m8820x_cmmu_shutdown_now()
 {
-	unsigned tmp;
 	unsigned cmmu_num;
+	struct cmmu_regs *cr;
 
 	CMMU_LOCK;
-	/*
-	 * Now set some state as we like...
-	 */
-	for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) {
-		if (brdtyp == BRD_188) {
-			tmp = 0 & ~(CMMU_SCTR_PE | CMMU_SCTR_SE | CMMU_SCTR_PR);
-		} else {
-			tmp = 0 & ~(CMMU_SCTR_PE | CMMU_SCTR_PR);
-		}
-
-		m8820x_cmmu[cmmu_num].cmmu_regs->sctr = tmp;
-
-		tmp = ((0x00000 << PG_BITS) | AREA_D_CI) &
-		    ~(AREA_D_WT | AREA_D_G | AREA_D_TE);
+	for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++)
+		if (m8820x_cmmu_alive(cmmu_num)) {
+			cr = m8820x_cmmu[cmmu_num].cmmu_regs;
 
-		m8820x_cmmu[cmmu_num].cmmu_regs->sapr = tmp;
-		m8820x_cmmu[cmmu_num].cmmu_regs->uapr = tmp;
-	}
+			cr->sctr &=
+			    ~(CMMU_SCTR_PE | CMMU_SCTR_SE | CMMU_SCTR_PR);
+			cr->sapr = cr->uapr =
+			    ((0x00000 << PG_BITS) | AREA_D_CI) &
+			    ~(AREA_D_WT | AREA_D_G | AREA_D_TE);
+		}
 	CMMU_UNLOCK;
 }
 
-#define PARITY_ENABLE
 /*
  * enable parity
  */
-void 
+void
 m8820x_cmmu_parity_enable()
 {
-#ifdef PARITY_ENABLE
-	register int cmmu_num;
+	unsigned cmmu_num;
+	struct cmmu_regs *cr;
+
 	CMMU_LOCK;
 
-	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++) {
+	for (cmmu_num = 0; cmmu_num < max_cmmus; cmmu_num++)
 		if (m8820x_cmmu_alive(cmmu_num)) {
-			register unsigned val1 = 
-				m8820x_cmmu_get(cmmu_num, CMMU_SCTR);
+			cr = m8820x_cmmu[cmmu_num].cmmu_regs;
 
-			/*
-			m8820x_cmmu[cmmu_num].cmmu_regs->sctr |= CMMU_SCTR_PE;
-			*/
-			m8820x_cmmu_set(CMMU_SCTR, val1 | CMMU_SCTR_PE, 
-				      NUM_CMMU, cmmu_num, 0, 0, 0);
+			cr->sctr |= CMMU_SCTR_PE;
 		}
-	}
+
 	CMMU_UNLOCK;
-#endif  /* PARITY_ENABLE */
 }
 
 /*
@@ -1022,15 +971,15 @@ m8820x_cmmu_parity_enable()
  */
 #define ILLADDRESS	0x0F000000 	/* any faulty address */
 
-unsigned 
+unsigned
 m8820x_cmmu_cpu_number()
 {
-	register unsigned cmmu_no;
-	int i;
+	unsigned cmmu_no;
+	int i, cpu;
 
 	CMMU_LOCK;
 
-	for (i=0; i < 10; i++) {
+	for (i = 0; i < 10; i++) {
 		/* clear CMMU p-bus status registers */
 		for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) {
 			if (m8820x_cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE &&
@@ -1039,49 +988,26 @@ m8820x_cmmu_cpu_number()
 		}
 
 		/* access faulting address */
-		badwordaddr((vm_offset_t)ILLADDRESS);
+		badwordaddr((vaddr_t)ILLADDRESS);
 
 		/* check which CMMU reporting the fault  */
 		for (cmmu_no = 0; cmmu_no < MAX_CMMUS; cmmu_no++) {
 			if (m8820x_cmmu[cmmu_no].cmmu_alive == CMMU_AVAILABLE &&
 			    m8820x_cmmu[cmmu_no].which == DATA_CMMU &&
-			    m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) {
-				if (m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr & 0x70000) {
-					m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0;	/* to be clean */
-					m8820x_cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED;
-					return m8820x_cmmu[cmmu_no].cmmu_cpu;
-				}
+			    ((m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr >> 16) &
+			    0x7) != 0) {
+				/* clean register, just in case... */
+				m8820x_cmmu[cmmu_no].cmmu_regs->pfSTATUSr = 0;
+				m8820x_cmmu[cmmu_no].cmmu_alive = CMMU_MARRIED;
+				cpu = m8820x_cmmu[cmmu_no].cmmu_cpu;
+				CMMU_UNLOCK;
+				return cpu;
 			}
 		}
 	}
-	panic("m8820x_cmmu_cpu_number: could not determine my cpu number");
 	CMMU_UNLOCK;
-	return 0; /* to make compiler happy */
-}
-
-/* Needs no locking - read only registers */
-unsigned
-m8820x_cmmu_get_idr(data)
-	unsigned data;
-{
-	int cpu;
-	cpu = cpu_number();
-	return REGS(cpu,data).idr;
-}
-
-void
-m8820x_cmmu_set_sapr(ap)
-	unsigned ap;
-{
-	int cpu;
-	cpu = cpu_number();
 
-	CMMU_LOCK;
-	if (cache_policy & CACHE_INH)
-		ap |= AREA_D_CI;
-	m8820x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL,
-		      cpu, 0, CMMU_ACS_SUPER, 0);
-	CMMU_UNLOCK;
+	panic("m8820x_cmmu_cpu_number: could not determine my cpu number");
 }
 
 void
@@ -1091,8 +1017,7 @@ m8820x_cmmu_remote_set_sapr(cpu, ap)
 	CMMU_LOCK;
 	if (cache_policy & CACHE_INH)
 		ap |= AREA_D_CI;
-	m8820x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL,
-		      cpu, 0, CMMU_ACS_SUPER, 0);
+	m8820x_cmmu_set(CMMU_SAPR, ap, ACCESS_VAL, cpu, 0, CMMU_ACS_SUPER, 0);
 	CMMU_UNLOCK;
 }
 
@@ -1100,45 +1025,22 @@ void
 m8820x_cmmu_set_uapr(ap)
 	unsigned ap;
 {
-	register int s = splhigh();
-	int cpu;
-	
-	cpu = cpu_number();
+	int s = splhigh();
+	int cpu = cpu_number();
 
 	CMMU_LOCK;
 	/* this functionality also mimiced in m8820x_cmmu_pmap_activate() */
-	m8820x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL,
-		      cpu, 0, CMMU_ACS_USER, 0);
+	m8820x_cmmu_set(CMMU_UAPR, ap, ACCESS_VAL, cpu, 0, CMMU_ACS_USER, 0);
 	CMMU_UNLOCK;
 	splx(s);
 }
 
 /*
- * Set batc entry number entry_no to value in 
- * the data or instruction cache depending on data.
- *
- * Except for the cmmu_init, this function, m8820x_cmmu_set_pair_batc_entry,
- * and m8820x_cmmu_pmap_activate are the only functions which may set the
- * batc values.
- */
-void
-m8820x_cmmu_set_batc_entry(cpu, entry_no, data, value)
-	unsigned cpu, entry_no;
-	unsigned data;	/* 1 = data, 0 = instruction */
-	unsigned value;	/* the value to stuff into the batc */
-{
-	CMMU_LOCK;
-	m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
-		      cpu, data, CMMU_ACS_USER, 0);
-#ifdef SHADOW_BATC
-	CMMU(cpu,data)->batc[entry_no] = value;
-#endif
-	CMMU_UNLOCK;
-}
-
-/*
- * Set batc entry number entry_no to value in 
+ * Set batc entry number entry_no to value in
  * the data and instruction cache for the named CPU.
+ *
+ * Except for the cmmu_init, this function and m8820x_cmmu_pmap_activate
+ * are the only functions which may set the batc values.
  */
 void
 m8820x_cmmu_set_pair_batc_entry(cpu, entry_no, value)
@@ -1146,13 +1048,14 @@ m8820x_cmmu_set_pair_batc_entry(cpu, entry_no, value)
 	unsigned value;	/* the value to stuff into the batc */
 {
 	CMMU_LOCK;
-	m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
-		      cpu, DATA_CMMU, CMMU_ACS_USER, 0);
+
+	m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL | ACCESS_VAL,
+	    cpu, DATA_CMMU, CMMU_ACS_USER, 0);
 #ifdef SHADOW_BATC
 	CMMU(cpu,DATA_CMMU)->batc[entry_no] = value;
 #endif
-	m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL|ACCESS_VAL,
-		      cpu, INST_CMMU, CMMU_ACS_USER, 0);
+	m8820x_cmmu_set(CMMU_BWP(entry_no), value, MODE_VAL | ACCESS_VAL,
+	    cpu, INST_CMMU, CMMU_ACS_USER, 0);
 #ifdef SHADOW_BATC
 	CMMU(cpu,INST_CMMU)->batc[entry_no] = value;
 #endif
@@ -1169,27 +1072,29 @@ m8820x_cmmu_set_pair_batc_entry(cpu, entry_no, value)
  *	Some functionality mimiced in m8820x_cmmu_pmap_activate.
  */
 void
-m8820x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size)
-	unsigned cpu, kernel;
-	vm_offset_t vaddr;
-	int size;
+m8820x_cmmu_flush_remote_tlb(unsigned cpu, unsigned kernel, vaddr_t vaddr,
+    vsize_t size)
 {
-	register int s = splhigh();
+	int s = splhigh();
+
 	CMMU_LOCK;
 
-	if (cpu > max_cpus) {
-		cpu = cpu_number();
+	if (size > PAGE_SIZE) {
+		m8820x_cmmu_set(CMMU_SCR,
+		    kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL,
+		    ACCESS_VAL, cpu, 0,
+		    kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, 0);
+	} else {
+		/* a page or smaller */
+		m8820x_cmmu_set(CMMU_SAR, vaddr,
+		    ADDR_VAL | ACCESS_VAL, cpu, 0,
+		    kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr);
+		m8820x_cmmu_set(CMMU_SCR,
+		    kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE,
+		    ADDR_VAL | ACCESS_VAL, cpu, 0,
+		    kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr);
 	}
 
-	if ((unsigned)size > PAGE_SIZE) {
-		m8820x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_ALL : CMMU_FLUSH_USER_ALL, ACCESS_VAL,
-			      cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, 0);
-	} else { /* a page or smaller */
-		m8820x_cmmu_set(CMMU_SAR, vaddr, ADDR_VAL|ACCESS_VAL,
-			      cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr);
-		m8820x_cmmu_set(CMMU_SCR, kernel ? CMMU_FLUSH_SUPER_PAGE : CMMU_FLUSH_USER_PAGE, ADDR_VAL|ACCESS_VAL,
-			      cpu, 0, kernel ? CMMU_ACS_SUPER : CMMU_ACS_USER, vaddr);
-	}
 	CMMU_UNLOCK;
 	splx(s);
 }
@@ -1198,20 +1103,16 @@ m8820x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size)
  *	flush my personal tlb
  */
 void
-m8820x_cmmu_flush_tlb(kernel, vaddr, size)
-	unsigned kernel;
-	vm_offset_t vaddr;
-	int size;
+m8820x_cmmu_flush_tlb(unsigned kernel, vaddr_t vaddr, vsize_t size)
 {
-	int cpu;
-	cpu = cpu_number();
+	int cpu = cpu_number();
 	m8820x_cmmu_flush_remote_tlb(cpu, kernel, vaddr, size);
 }
 
 /*
  * New fast stuff for pmap_activate.
  * Does what a few calls used to do.
- * Only called from pmap.c's _pmap_activate().
+ * Only called from pmap_activate().
  */
 void
 m8820x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
@@ -1220,6 +1121,7 @@ m8820x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
 	u_int32_t d_batc[BATC_MAX];
 {
 	int entry_no;
+
 	CMMU_LOCK;
 
 	/* the following is from m8820x_cmmu_set_uapr */
@@ -1243,7 +1145,8 @@ m8820x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
 	 * THE SUPERVISOR TLBs SHOULB EE FLUSHED AS WELL.
 	 */
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_USER_ALL, ACCESS_VAL,
-		      cpu, 0, CMMU_ACS_USER, 0);
+	    cpu, 0, CMMU_ACS_USER, 0);
+
 	CMMU_UNLOCK;
 }
 
@@ -1259,46 +1162,44 @@ m8820x_cmmu_pmap_activate(cpu, uapr, i_batc, d_batc)
  * We don't push Instruction Caches prior to invalidate because they are not
  * snooped and never modified (I guess it doesn't matter then which form
  * of the command we use then).
+ *
+ * XXX miod WHAT? Above comment seems 200% bogus wrt snooping!
  */
 
 /*
  *	flush both Instruction and Data caches
  */
 void
-m8820x_cmmu_flush_remote_cache(cpu, physaddr, size)
-	int cpu;
-	vm_offset_t physaddr;
-	int size;
+m8820x_cmmu_flush_remote_cache(int cpu, paddr_t physaddr, psize_t size)
 {
-	register int s = splhigh();
+	int s = splhigh();
 	CMMU_LOCK;
 
 #if !defined(BROKEN_MMU_MASK)
-
-	if (size < 0 || size > NBSG ) {
+	if (size > NBSG) {
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0,
-			      cpu, 0, 0, 0);
+		    cpu, 0, 0, 0);
 	} else if (size <= 16) {
 		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL,
-			      cpu, 0, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE , ADDR_VAL,
-			      cpu, 0, 0, (unsigned)physaddr);
+		    cpu, 0, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, ADDR_VAL,
+		    cpu, 0, 0, (unsigned)physaddr);
 	} else if (size <= NBPG) {
 		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, ADDR_VAL,
-			      cpu, 0, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE , ADDR_VAL,
-			      cpu, 0, 0, (unsigned)physaddr);
+		    cpu, 0, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, ADDR_VAL,
+		    cpu, 0, 0, (unsigned)physaddr);
 	} else {
 		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, 0,
-			      cpu, 0, 0, 0);
+		    cpu, 0, 0, 0);
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, 0,
-			      cpu, 0, 0, 0);
+		    cpu, 0, 0, 0);
 	}
-
 #else
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, 0,
-		      cpu, 0, 0, 0);
+	    cpu, 0, 0, 0);
 #endif /* !BROKEN_MMU_MASK */
+
 	CMMU_UNLOCK;
 	splx(s);
 }
@@ -1307,9 +1208,7 @@ m8820x_cmmu_flush_remote_cache(cpu, physaddr, size)
  *	flush both Instruction and Data caches
  */
 void
-m8820x_cmmu_flush_cache(physaddr, size)
-	vm_offset_t physaddr;
-	int size;
+m8820x_cmmu_flush_cache(paddr_t physaddr, psize_t size)
 {
 	int cpu = cpu_number();
 	m8820x_cmmu_flush_remote_cache(cpu, physaddr, size);
@@ -1319,38 +1218,34 @@ m8820x_cmmu_flush_cache(physaddr, size)
  *	flush Instruction caches
  */
 void
-m8820x_cmmu_flush_remote_inst_cache(cpu, physaddr, size)
-	int cpu;
-	vm_offset_t physaddr;
-	int size;
+m8820x_cmmu_flush_remote_inst_cache(int cpu, paddr_t physaddr, psize_t size)
 {
-	register int s = splhigh();
+	int s = splhigh();
 	CMMU_LOCK;
 
 #if !defined(BROKEN_MMU_MASK)
-	if (size < 0 || size > NBSG ) {
+	if (size > NBSG) {
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
+		    cpu, INST_CMMU, 0, 0);
 	} else if (size <= 16) {
-
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
 	} else if (size <= NBPG) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
 	} else {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
 	}
 #else
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-		      cpu, INST_CMMU, 0, 0);
+	    cpu, INST_CMMU, 0, 0);
 #endif /* !BROKEN_MMU_MASK */
 
 	CMMU_UNLOCK;
@@ -1361,64 +1256,54 @@ m8820x_cmmu_flush_remote_inst_cache(cpu, physaddr, size)
  *	flush Instruction caches
  */
 void
-m8820x_cmmu_flush_inst_cache(physaddr, size)
-	vm_offset_t physaddr;
-	int size;
+m8820x_cmmu_flush_inst_cache(paddr_t physaddr, psize_t size)
 {
-	int cpu;
-	cpu = cpu_number();
+	int cpu = cpu_number();
 	m8820x_cmmu_flush_remote_inst_cache(cpu, physaddr, size);
 }
 
 void
-m8820x_cmmu_flush_remote_data_cache(cpu, physaddr, size)
-	int cpu;
-	vm_offset_t physaddr;
-	int size;
+m8820x_cmmu_flush_remote_data_cache(int cpu, paddr_t physaddr, psize_t size)
 {
-	register int s = splhigh();
+	int s = splhigh();
 	CMMU_LOCK;
 
 #if !defined(BROKEN_MMU_MASK)
-	if (size < 0 || size > NBSG ) {
-
+	if (size > NBSG) {
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		    cpu, DATA_CMMU, 0, 0);
 	} else if (size <= 16) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_LINE,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
 	} else if (size <= NBPG) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_PAGE,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
 	} else {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_SEGMENT,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	}
 #else
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-		      cpu, DATA_CMMU, 0, 0);
+	    cpu, DATA_CMMU, 0, 0);
 #endif /* !BROKEN_MMU_MASK */
+
 	CMMU_UNLOCK;
 	splx(s);
 }
 
 /*
  * flush data cache
- */ 
+ */
 void
-m8820x_cmmu_flush_data_cache(physaddr, size)
-	vm_offset_t physaddr;
-	int size;
-{ 
-	int cpu;
-	cpu = cpu_number();
+m8820x_cmmu_flush_data_cache(paddr_t physaddr, psize_t size)
+{
+	int cpu = cpu_number();
 	m8820x_cmmu_flush_remote_data_cache(cpu, physaddr, size);
 }
 
@@ -1426,201 +1311,203 @@ m8820x_cmmu_flush_data_cache(physaddr, size)
  * sync dcache (and icache too)
  */
 void
-m8820x_cmmu_sync_cache(physaddr, size)
-	vm_offset_t physaddr;
-	int size;
+m8820x_cmmu_sync_cache(paddr_t physaddr, psize_t size)
 {
-	register int s = splhigh();
-	int cpu;
-	
+	int s = splhigh();
+	int cpu = cpu_number();
+
 	CMMU_LOCK;
-	cpu = cpu_number();
 
 #if !defined(BROKEN_MMU_MASK)
-	if (size < 0 || size > NBSG ) {
+	if (size > NBSG) {
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		    cpu, DATA_CMMU, 0, 0);
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
+		    cpu, INST_CMMU, 0, 0);
 	} else if (size <= 16) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_LINE,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	} else if (size <= NBPG) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_PAGE,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	} else {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CB_SEGMENT,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	}
 #else
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
-		      cpu, DATA_CMMU, 0, 0);
+	    cpu, DATA_CMMU, 0, 0);
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CB_ALL, MODE_VAL,
-		      cpu, INST_CMMU, 0, 0);
+	    cpu, INST_CMMU, 0, 0);
 #endif /* !BROKEN_MMU_MASK */
-	splx(s);
+
 	CMMU_UNLOCK;
+	splx(s);
 }
 
-void 
-m8820x_cmmu_sync_inval_cache(physaddr, size)
-	vm_offset_t physaddr;
-	int size;
+void
+m8820x_cmmu_sync_inval_cache(paddr_t physaddr, psize_t size)
 {
-	register int s = splhigh();
-	int cpu;
-	cpu = cpu_number();
+	int s = splhigh();
+	int cpu = cpu_number();
+
 	CMMU_LOCK;
 
 #if !defined(BROKEN_MMU_MASK)
-	if (size < 0 || size > NBSG ) {
+	if (size > NBSG) {
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		    cpu, DATA_CMMU, 0, 0);
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
+		    cpu, INST_CMMU, 0, 0);
 	} else if (size <= 16) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_LINE,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	} else if (size <= NBPG) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_PAGE,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	} else {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_CBI_SEGMENT,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	}
-
 #else
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-		      cpu, DATA_CMMU, 0, 0);
+	    cpu, DATA_CMMU, 0, 0);
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_CBI_ALL, MODE_VAL,
-		      cpu, INST_CMMU, 0, 0);
+	    cpu, INST_CMMU, 0, 0);
 #endif /* !BROKEN_MMU_MASK */
+
 	CMMU_UNLOCK;
 	splx(s);
 }
 
 void
-m8820x_cmmu_inval_cache(physaddr, size)
-	vm_offset_t physaddr;
-	int size;
+m8820x_cmmu_inval_cache(paddr_t physaddr, psize_t size)
 {
-	register int s = splhigh();
-	int cpu;
-	cpu = cpu_number();
+	int s = splhigh();
+	int cpu = cpu_number();
+
 	CMMU_LOCK;
 
 #if !defined(BROKEN_MMU_MASK)
-	if (size < 0 || size > NBSG ) {
+	if (size > NBSG) {
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		    cpu, DATA_CMMU, 0, 0);
 		m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
+		    cpu, INST_CMMU, 0, 0);
 	} else if (size <= 16) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_LINE,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	} else if (size <= NBPG) {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_PAGE,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	} else {
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, INST_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL,
-			      cpu, INST_CMMU, 0, 0);
-		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr, MODE_VAL|ADDR_VAL,
-			      cpu, DATA_CMMU, 0, (unsigned)physaddr);
-		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT, MODE_VAL,
-			      cpu, DATA_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, INST_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT,
+		    MODE_VAL, cpu, INST_CMMU, 0, 0);
+		m8820x_cmmu_set(CMMU_SAR, (unsigned)physaddr,
+		    MODE_VAL | ADDR_VAL, cpu, DATA_CMMU, 0, (unsigned)physaddr);
+		m8820x_cmmu_set(CMMU_SAR, CMMU_FLUSH_CACHE_INV_SEGMENT,
+		    MODE_VAL, cpu, DATA_CMMU, 0, 0);
 	}
 #else
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
-		      cpu, DATA_CMMU, 0, 0);
+	    cpu, DATA_CMMU, 0, 0);
 	m8820x_cmmu_set(CMMU_SCR, CMMU_FLUSH_CACHE_INV_ALL, MODE_VAL,
-		      cpu, INST_CMMU, 0, 0);
+	    cpu, INST_CMMU, 0, 0);
 #endif /* !BROKEN_MMU_MASK */
+
 	CMMU_UNLOCK;
 	splx(s);
 }
 
 void
-m8820x_dma_cachectl(va, size, op)
-	vm_offset_t va;
-	int size, op;
+m8820x_dma_cachectl(vaddr_t va, vsize_t size, int op)
 {
 #if !defined(BROKEN_MMU_MASK)
-	int count;
+	psize_t count;
 
-	while (size) {
-		count = NBPG - ((int)va & PGOFSET);
+	while (size != 0) {
+		count = NBPG - (va & PGOFSET);
 
 		if (size < count)
 			count = size;
 
-		if (op == DMA_CACHE_SYNC)
+		switch (op) {
+		case DMA_CACHE_SYNC:
 			m8820x_cmmu_sync_cache(kvtop(va), count);
-		else if (op == DMA_CACHE_SYNC_INVAL)
+			break;
+		case DMA_CACHE_SYNC_INVAL:
 			m8820x_cmmu_sync_inval_cache(kvtop(va), count);
-		else
+			break;
+		default:
 			m8820x_cmmu_inval_cache(kvtop(va), count);
+			break;
+		}
 
-		va = (vm_offset_t)((int)va + count);
+		va += count;
 		size -= count;
 	}
 #else
-
-	if (op == DMA_CACHE_SYNC)
+	switch (op) {
+	case DMA_CACHE_SYNC:
 		m8820x_cmmu_sync_cache(kvtop(va), size);
-	else if (op == DMA_CACHE_SYNC_INVAL)
+		break;
+	case DMA_CACHE_SYNC_INVAL:
 		m8820x_cmmu_sync_inval_cache(kvtop(va), size);
-	else
+		break;
+	default:
 		m8820x_cmmu_inval_cache(kvtop(va), size);
+		break;
+	}
 #endif /* !BROKEN_MMU_MASK */
 }
 
@@ -1720,118 +1607,78 @@ m8820x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
 	u_int32_t value;
 
 	if (verbose_flag)
-		DEBUG_MSG("-------------------------------------------\n");
+		db_printf("-------------------------------------------\n");
 
 
 
 	/****** ACCESS PROPER CMMU or THREAD ***********/
-#if 0 /* no thread */
-	if (thread != 0) {
-		/* the following tidbit from pmap_activate() */
-		supervisor_flag = 0; /* thread implies user */
-
-		if (thread->task == 0) {
-			DEBUG_MSG("[thread %x has empty task pointer]\n", thread);
-			return;
-		} else if (thread->task->map == 0) {
-			DEBUG_MSG("[thread/task %x/%x has empty map pointer]\n",
-				  thread, thread->task);
+	if (cmmu_num == -1) {
+		int cpu = cpu_number();
+		if (cpu_cmmu[cpu].pair[DATA_CMMU] == 0) {
+			db_printf("ack! can't figure my own data cmmu number.\n");
 			return;
-		} else if (thread->task->map->pmap == 0) {
-			DEBUG_MSG("[thread/task/map %x/%x/%x has empty pmap pointer]\n",
-				  thread, thread->task, thread->task->map);
-			return;
-		}
-		if (thread->task->map->pmap->lock.lock_data) {
-			DEBUG_MSG("[Warning: thread %x's task %x's map %x's "
-				  "pmap %x is locked]\n", thread, thread->task,
-				  thread->task->map, thread->task->map->pmap);
 		}
-		value = CACHE_GLOBAL | APR_V |
-		    (atop(thread->task->map->pmap->sdt_paddr) << PG_SHIFT);
-		if (verbose_flag) {
-			DEBUG_MSG("[thread %x task %x map %x pmap %x UAPR is %x]\n",
-				  thread, thread->task, thread->task->map,
-				  thread->task->map->pmap, value);
-		}
-	} else
-#endif /* 0 */
-	{
-		if (cmmu_num == -1) {
-			int cpu = cpu_number();
-			if (cpu_cmmu[cpu].pair[DATA_CMMU] == 0) {
-				DEBUG_MSG("ack! can't figure my own data cmmu number.\n");
-				return;
-			}
-			cmmu_num = cpu_cmmu[cpu].pair[DATA_CMMU] - m8820x_cmmu;
-			if (verbose_flag)
-				DEBUG_MSG("The data cmmu for cpu#%d is cmmu#%d.\n",
-					  0, cmmu_num);
-		} else if (cmmu_num < 0 || cmmu_num >= MAX_CMMUS) {
-			DEBUG_MSG("invalid cpu number [%d]... must be in range [0..%d]\n",
-				  cmmu_num, MAX_CMMUS - 1);
+		cmmu_num = cpu_cmmu[cpu].pair[DATA_CMMU] - m8820x_cmmu;
+		if (verbose_flag)
+			db_printf("The data cmmu for cpu#%d is cmmu#%d.\n",
+				  0, cmmu_num);
+	} else if (cmmu_num < 0 || cmmu_num >= MAX_CMMUS) {
+		db_printf("invalid cpu number [%d]... must be in range [0..%d]\n",
+			  cmmu_num, MAX_CMMUS - 1);
 
-			return;
-		}
+		return;
+	}
 
-		if (m8820x_cmmu[cmmu_num].cmmu_alive == 0) {
-			DEBUG_MSG("warning: cmmu %d is not alive.\n", cmmu_num);
+	if (m8820x_cmmu[cmmu_num].cmmu_alive == 0) {
+		db_printf("warning: cmmu %d is not alive.\n", cmmu_num);
 #if 0
-			return;
+		return;
 #endif
-		}
-
-		if (!verbose_flag) {
-			if (!(m8820x_cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE))
-				DEBUG_MSG("WARNING: snooping not enabled for CMMU#%d.\n",
-					  cmmu_num);
-		} else {
-			int i;
-			for (i=0; i<MAX_CMMUS; i++)
-				if ((i == cmmu_num || m8820x_cmmu[i].cmmu_alive) &&
-				    (verbose_flag>1 || !(m8820x_cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) {
-					DEBUG_MSG("CMMU#%d (cpu %d %s) snooping %s\n", i,
-						  m8820x_cmmu[i].cmmu_cpu, m8820x_cmmu[i].which ? "data" : "inst",
-						  (m8820x_cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF");
-				}
-		}
-
-		if (supervisor_flag)
-			value = m8820x_cmmu[cmmu_num].cmmu_regs->sapr;
-		else
-			value = m8820x_cmmu[cmmu_num].cmmu_regs->uapr;
+	}
 
+	if (!verbose_flag) {
+		if (!(m8820x_cmmu[cmmu_num].cmmu_regs->sctr & CMMU_SCTR_SE))
+			db_printf("WARNING: snooping not enabled for CMMU#%d.\n",
+				  cmmu_num);
+	} else {
+		int i;
+		for (i=0; i<MAX_CMMUS; i++)
+			if ((i == cmmu_num || m8820x_cmmu[i].cmmu_alive) &&
+			    (verbose_flag>1 || !(m8820x_cmmu[i].cmmu_regs->sctr&CMMU_SCTR_SE))) {
+				db_printf("CMMU#%d (cpu %d %s) snooping %s\n", i,
+					  m8820x_cmmu[i].cmmu_cpu, m8820x_cmmu[i].which ? "data" : "inst",
+					  (m8820x_cmmu[i].cmmu_regs->sctr & CMMU_SCTR_SE) ? "on":"OFF");
+			}
 	}
 
-	/******* LOOK AT THE BATC ** (if not a thread) **************/
-#if 0
+	if (supervisor_flag)
+		value = m8820x_cmmu[cmmu_num].cmmu_regs->sapr;
+	else
+		value = m8820x_cmmu[cmmu_num].cmmu_regs->uapr;
+
 #ifdef SHADOW_BATC
-	if (thread == 0) {
+	{
 		int i;
 		union batcu batc;
 		for (i = 0; i < 8; i++) {
 			batc.bits = m8820x_cmmu[cmmu_num].batc[i];
 			if (batc.field.v == 0) {
 				if (verbose_flag>1)
-					DEBUG_MSG("cmmu #%d batc[%d] invalid.\n", cmmu_num, i);
+					db_printf("cmmu #%d batc[%d] invalid.\n", cmmu_num, i);
 			} else {
-				DEBUG_MSG("cmmu#%d batc[%d] v%08x p%08x", cmmu_num, i,
+				db_printf("cmmu#%d batc[%d] v%08x p%08x", cmmu_num, i,
 					  batc.field.lba << 18, batc.field.pba);
-				if (batc.field.s)  DEBUG_MSG(", supervisor");
-				if (batc.field.wt) DEBUG_MSG(", wt.th");
-				if (batc.field.g)  DEBUG_MSG(", global");
-				if (batc.field.ci) DEBUG_MSG(", cache inhibit");
-				if (batc.field.wp) DEBUG_MSG(", write protect");
+				if (batc.field.s)  db_printf(", supervisor");
+				if (batc.field.wt) db_printf(", wt.th");
+				if (batc.field.g)  db_printf(", global");
+				if (batc.field.ci) db_printf(", cache inhibit");
+				if (batc.field.wp) db_printf(", write protect");
 			}
 		}
 	}
 #endif	/* SHADOW_BATC */
-#endif	/* 0 */
 
 	/******* SEE WHAT A PROBE SAYS (if not a thread) ***********/
-#if 0
-	if (thread == 0)
-#endif /* 0 */
 	{
 		union ssr ssr;
 		struct cmmu_regs *cmmu_regs = m8820x_cmmu[cmmu_num].cmmu_regs;
@@ -1839,61 +1686,49 @@ m8820x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
 		cmmu_regs->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER;
 		ssr.bits = cmmu_regs->ssr;
 		if (verbose_flag > 1)
-			DEBUG_MSG("probe of 0x%08x returns ssr=0x%08x\n",
+			db_printf("probe of 0x%08x returns ssr=0x%08x\n",
 				  address, ssr.bits);
 		if (ssr.field.v)
-			DEBUG_MSG("PROBE of 0x%08x returns phys=0x%x",
+			db_printf("PROBE of 0x%08x returns phys=0x%x",
 				  address, cmmu_regs->sar);
 		else
-			DEBUG_MSG("PROBE fault at 0x%x", cmmu_regs->pfADDRr);
-		if (ssr.field.ce) DEBUG_MSG(", copyback err");
-		if (ssr.field.be) DEBUG_MSG(", bus err");
-		if (ssr.field.wt) DEBUG_MSG(", writethrough");
-		if (ssr.field.sp) DEBUG_MSG(", sup prot");
-		if (ssr.field.g)  DEBUG_MSG(", global");
-		if (ssr.field.ci) DEBUG_MSG(", cache inhibit");
-		if (ssr.field.m)  DEBUG_MSG(", modified");
-		if (ssr.field.u)  DEBUG_MSG(", used");
-		if (ssr.field.wp) DEBUG_MSG(", write prot");
-		if (ssr.field.bh) DEBUG_MSG(", BATC");
-		DEBUG_MSG(".\n");
+			db_printf("PROBE fault at 0x%x", cmmu_regs->pfADDRr);
+		if (ssr.field.ce) db_printf(", copyback err");
+		if (ssr.field.be) db_printf(", bus err");
+		if (ssr.field.wt) db_printf(", writethrough");
+		if (ssr.field.sp) db_printf(", sup prot");
+		if (ssr.field.g)  db_printf(", global");
+		if (ssr.field.ci) db_printf(", cache inhibit");
+		if (ssr.field.m)  db_printf(", modified");
+		if (ssr.field.u)  db_printf(", used");
+		if (ssr.field.wp) db_printf(", write prot");
+		if (ssr.field.bh) db_printf(", BATC");
+		db_printf(".\n");
 	}
 
 	/******* INTERPRET AREA DESCRIPTOR *********/
 	{
 		if (verbose_flag > 1) {
-			DEBUG_MSG("CMMU#%d", cmmu_num);
-#if 0
-			if (thread == 0)
-				DEBUG_MSG("CMMU#%d", cmmu_num);
-			else
-				DEBUG_MSG("THREAD %x", thread);
-#endif /* 0 */
-			DEBUG_MSG(" %cAPR is 0x%08x\n",
+			db_printf("CMMU#%d", cmmu_num);
+			db_printf(" %cAPR is 0x%08x\n",
 				  supervisor_flag ? 'S' : 'U', value);
 		}
-		DEBUG_MSG("CMMU#%d", cmmu_num);
-#if 0
-		if (thread == 0)
-			DEBUG_MSG("CMMU#%d", cmmu_num);
-		else
-			DEBUG_MSG("THREAD %x", thread);
-#endif /* 0 */
-		DEBUG_MSG(" %cAPR: SegTbl: 0x%x000p",
+		db_printf("CMMU#%d", cmmu_num);
+		db_printf(" %cAPR: SegTbl: 0x%x000p",
 			  supervisor_flag ? 'S' : 'U', PG_PFNUM(value));
 		if (value & CACHE_WT)
-			DEBUG_MSG(", WTHRU");
+			db_printf(", WTHRU");
 		if (value & CACHE_GLOBAL)
-			DEBUG_MSG(", GLOBAL");
+			db_printf(", GLOBAL");
 		if (value & CACHE_INH)
-			DEBUG_MSG(", INHIBIT");
+			db_printf(", INHIBIT");
 		if (value & APR_V)
-			DEBUG_MSG(", VALID");
-		DEBUG_MSG("\n");
+			db_printf(", VALID");
+		db_printf("\n");
 
 		/* if not valid, done now */
 		if ((value & APR_V) == 0) {
-			DEBUG_MSG("<would report an error, valid bit not set>\n");
+			db_printf("<would report an error, valid bit not set>\n");
 
 			return;
 		}
@@ -1903,7 +1738,7 @@ m8820x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
 
 	/* translate value from physical to virtual */
 	if (verbose_flag)
-		DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
+		db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
 	value += VEQR_ADDR;
 
 	virtual_address.bits = address;
@@ -1912,38 +1747,38 @@ m8820x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
 	{
 		sdt_entry_t sdt;
 		if (verbose_flag)
-			DEBUG_MSG("will follow to entry %d of page at 0x%x...\n",
+			db_printf("will follow to entry %d of page at 0x%x...\n",
 				  virtual_address.field.segment_table_index, value);
 		value |= virtual_address.field.segment_table_index *
 			 sizeof(sdt_entry_t);
 
-		if (badwordaddr((vm_offset_t)value)) {
-			DEBUG_MSG("ERROR: unable to access page at 0x%08x.\n", value);
+		if (badwordaddr((vaddr_t)value)) {
+			db_printf("ERROR: unable to access page at 0x%08x.\n", value);
 			return;
 		}
 
 		sdt = *(sdt_entry_t *)value;
 		if (verbose_flag > 1)
-			DEBUG_MSG("SEG DESC @0x%x is 0x%08x\n", value, sdt);
-		DEBUG_MSG("SEG DESC @0x%x: PgTbl: 0x%x000",
+			db_printf("SEG DESC @0x%x is 0x%08x\n", value, sdt);
+		db_printf("SEG DESC @0x%x: PgTbl: 0x%x000",
 			  value, PG_PFNUM(sdt));
-		if (sdt & CACHE_WT)		    DEBUG_MSG(", WTHRU");
-		else				    DEBUG_MSG(", !wthru");
-		if (sdt & SG_SO)		    DEBUG_MSG(", S-PROT");
-		else				    DEBUG_MSG(", UserOk");
-		if (sdt & CACHE_GLOBAL)		    DEBUG_MSG(", GLOBAL");
-		else				    DEBUG_MSG(", !global");
-		if (sdt & CACHE_INH)		    DEBUG_MSG(", $INHIBIT");
-		else				    DEBUG_MSG(", $ok");
-		if (sdt & SG_PROT)		    DEBUG_MSG(", W-PROT");
-		else				    DEBUG_MSG(", WriteOk");
-		if (sdt & SG_V)			    DEBUG_MSG(", VALID");
-		else				    DEBUG_MSG(", !valid");
-		DEBUG_MSG(".\n");
+		if (sdt & CACHE_WT)		    db_printf(", WTHRU");
+		else				    db_printf(", !wthru");
+		if (sdt & SG_SO)		    db_printf(", S-PROT");
+		else				    db_printf(", UserOk");
+		if (sdt & CACHE_GLOBAL)		    db_printf(", GLOBAL");
+		else				    db_printf(", !global");
+		if (sdt & CACHE_INH)		    db_printf(", $INHIBIT");
+		else				    db_printf(", $ok");
+		if (sdt & SG_PROT)		    db_printf(", W-PROT");
+		else				    db_printf(", WriteOk");
+		if (sdt & SG_V)			    db_printf(", VALID");
+		else				    db_printf(", !valid");
+		db_printf(".\n");
 
 		/* if not valid, done now */
 		if (!(sdt & SG_V)) {
-			DEBUG_MSG("<would report an error, STD entry not valid>\n");
+			db_printf("<would report an error, STD entry not valid>\n");
 			return;
 		}
 
@@ -1952,145 +1787,73 @@ m8820x_cmmu_show_translation(address, supervisor_flag, verbose_flag, cmmu_num)
 
 	/* translate value from physical to virtual */
 	if (verbose_flag)
-		DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
+		db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
 	value += VEQR_ADDR;
 
 	/******* PAGE TABLE *********/
 	{
 		pt_entry_t pte;
 		if (verbose_flag)
-			DEBUG_MSG("will follow to entry %d of page at 0x%x...\n",
+			db_printf("will follow to entry %d of page at 0x%x...\n",
 				  virtual_address.field.page_table_index, value);
 		value |= virtual_address.field.page_table_index *
 			 sizeof(pt_entry_t);
 
-		if (badwordaddr((vm_offset_t)value)) {
-			DEBUG_MSG("error: unable to access page at 0x%08x.\n", value);
+		if (badwordaddr((vaddr_t)value)) {
+			db_printf("error: unable to access page at 0x%08x.\n", value);
 
 			return;
 		}
 
 		pte = *(pt_entry_t *)value;
 		if (verbose_flag > 1)
-			DEBUG_MSG("PAGE DESC @0x%x is 0x%08x.\n", value, pte);
-		DEBUG_MSG("PAGE DESC @0x%x: page @%x000",
+			db_printf("PAGE DESC @0x%x is 0x%08x.\n", value, pte);
+		db_printf("PAGE DESC @0x%x: page @%x000",
 			  value, PG_PFNUM(pte));
-		if (pte & PG_W)			DEBUG_MSG(", WIRE");
-		else				DEBUG_MSG(", !wire");
-		if (pte & CACHE_WT)		DEBUG_MSG(", WTHRU");
-		else				DEBUG_MSG(", !wthru");
-		if (pte & PG_SO)		DEBUG_MSG(", S-PROT");
-		else				DEBUG_MSG(", UserOk");
-		if (pte & CACHE_GLOBAL)		DEBUG_MSG(", GLOBAL");
-		else				DEBUG_MSG(", !global");
-		if (pte & CACHE_INH)		DEBUG_MSG(", $INHIBIT");
-		else				DEBUG_MSG(", $ok");
-		if (pte & PG_M)			DEBUG_MSG(", MOD");
-		else				DEBUG_MSG(", !mod");
-		if (pte & PG_U)			DEBUG_MSG(", USED");
-		else				DEBUG_MSG(", !used");
-		if (pte & PG_PROT)		DEBUG_MSG(", W-PROT");
-		else				DEBUG_MSG(", WriteOk");
-		if (pte & PG_V)			DEBUG_MSG(", VALID");
-		else				DEBUG_MSG(", !valid");
-		DEBUG_MSG(".\n");
+		if (pte & PG_W)			db_printf(", WIRE");
+		else				db_printf(", !wire");
+		if (pte & CACHE_WT)		db_printf(", WTHRU");
+		else				db_printf(", !wthru");
+		if (pte & PG_SO)		db_printf(", S-PROT");
+		else				db_printf(", UserOk");
+		if (pte & CACHE_GLOBAL)		db_printf(", GLOBAL");
+		else				db_printf(", !global");
+		if (pte & CACHE_INH)		db_printf(", $INHIBIT");
+		else				db_printf(", $ok");
+		if (pte & PG_M)			db_printf(", MOD");
+		else				db_printf(", !mod");
+		if (pte & PG_U)			db_printf(", USED");
+		else				db_printf(", !used");
+		if (pte & PG_PROT)		db_printf(", W-PROT");
+		else				db_printf(", WriteOk");
+		if (pte & PG_V)			db_printf(", VALID");
+		else				db_printf(", !valid");
+		db_printf(".\n");
 
 		/* if not valid, done now */
 		if (!(pte & PG_V)) {
-			DEBUG_MSG("<would report an error, PTE entry not valid>\n");
+			db_printf("<would report an error, PTE entry not valid>\n");
 			return;
 		}
 
 		value = ptoa(PG_PFNUM(pte));
 		if (verbose_flag)
-			DEBUG_MSG("will follow to byte %d of page at 0x%x...\n",
+			db_printf("will follow to byte %d of page at 0x%x...\n",
 				  virtual_address.field.page_offset, value);
 		value |= virtual_address.field.page_offset;
 
-		if (badwordaddr((vm_offset_t)value)) {
-			DEBUG_MSG("error: unable to access page at 0x%08x.\n", value);
+		if (badwordaddr((vaddr_t)value)) {
+			db_printf("error: unable to access page at 0x%08x.\n", value);
 			return;
 		}
 	}
 
 	/* translate value from physical to virtual */
 	if (verbose_flag)
-		DEBUG_MSG("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
+		db_printf("[%x physical is %x virtual]\n", value, value + VEQR_ADDR);
 	value += VEQR_ADDR;
 
-	DEBUG_MSG("WORD at 0x%x is 0x%08x.\n", value, *(unsigned *)value);
-
-}
-
-void
-m8820x_cmmu_cache_state(addr, supervisor_flag)
-	unsigned addr, supervisor_flag;
-{
-	static char *vv_name[4] =
-	{"exclu-unmod", "exclu-mod", "shared-unmod", "invalid"};
-	int cmmu_num;
-
-	for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++) {
-		union ssr ssr;
-		union cssp cssp;
-		struct cmmu_regs *R;
-		unsigned tag, line;
-		if (!m8820x_cmmu[cmmu_num].cmmu_alive)
-			continue;
-		R = m8820x_cmmu[cmmu_num].cmmu_regs;
-		DEBUG_MSG("cmmu #%d %s cmmu for cpu %d.\n", cmmu_num,
-			  m8820x_cmmu[cmmu_num].which ? "data" : "inst", 
-			  m8820x_cmmu[cmmu_num].cmmu_cpu);
-		R->sar = addr;
-		R->scr = supervisor_flag ? CMMU_PROBE_SUPER : CMMU_PROBE_USER;
-
-		ssr.bits = R->ssr;
-		if (!ssr.field.v) {
-			DEBUG_MSG("PROBE of 0x%08x faults.\n",addr);
-			continue;
-		}
-		DEBUG_MSG("PROBE of 0x%08x returns phys=0x%x", addr, R->sar);
-
-		tag = R->sar & ~0xfff;
-		cssp.bits = R->cssp;
-
-		/* check to see if any of the tags for the set match the address */
-		for (line = 0; line < 4; line++) {
-			if (VV(cssp, line) == VV_INVALID) {
-				DEBUG_MSG("line %d invalid.\n", line);
-				continue; /* line is invalid */
-			}
-			if (D(cssp, line)) {
-				DEBUG_MSG("line %d disabled.\n", line);
-				continue; /* line is disabled */
-			}
-
-			if ((R->ctp[line] & ~0xfff) != tag) {
-				DEBUG_MSG("line %d address tag is %x.\n", line,
-					  (R->ctp[line] & ~0xfff));
-				continue;
-			}
-			DEBUG_MSG("found in line %d as %08x (%s).\n",
-				  line, R->cdp[line], vv_name[VV(cssp, line)]);
-		}
-	}
+	db_printf("WORD at 0x%x is 0x%08x.\n", value, *(unsigned *)value);
 
 }
-
-void
-m8820x_show_cmmu_info(addr)
-	unsigned addr;
-{
-	int cmmu_num;
-	m8820x_cmmu_cache_state(addr, 1);
-
-	for (cmmu_num = 0; cmmu_num < MAX_CMMUS; cmmu_num++)
-		if (m8820x_cmmu[cmmu_num].cmmu_alive) {
-			DEBUG_MSG("cmmu #%d %s cmmu for cpu %d: ", cmmu_num,
-				  m8820x_cmmu[cmmu_num].which ? "data" : "inst", 
-				  m8820x_cmmu[cmmu_num].cmmu_cpu);
-			m8820x_cmmu_show_translation(addr, 1, 0, cmmu_num);
-		}
-}
-
 #endif /* DDB */