Standardize cache handling functions and defines to use wb/wbinv/inv instead

of flush/sync/inval. No functional change.

5 files changed, 152 insertions, 152 deletions

diff --git a/sys/arch/mvme88k/include/m88110.h b/sys/arch/mvme88k/include/m88110.h
index f3dfad7e3a9..306bd6cd4ac 100644
--- a/sys/arch/mvme88k/include/m88110.h
+++ b/sys/arch/mvme88k/include/m88110.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.h,v 1.22 2007/12/02 21:32:44 miod Exp $ */
+/*	$OpenBSD: m88110.h,v 1.23 2010/12/31 20:54:21 miod Exp $ */
 
 #ifndef	__MACHINE_M88110_H__
 #define	__MACHINE_M88110_H__
@@ -7,88 +7,88 @@
  *	88110 CMMU definitions
  */
 
-#define CMMU_ICMD_INV_ITIC       0x001    /* Invalidate Inst Cache & TIC */
-#define CMMU_ICMD_INV_TIC        0x002    /* Invalidate TIC */
-#define CMMU_ICMD_INV_LINE       0x005    /* Invalidate Inst Cache Line */
-#define CMMU_ICMD_PRB_SUPR       0x008    /* MMU Probe Supervisor */
-#define CMMU_ICMD_PRB_USER       0x009    /* MMU Probe User */
-#define CMMU_ICMD_INV_SATC       0x00a    /* Invalidate All Supervisor ATCs */
-#define CMMU_ICMD_INV_UATC       0x00b    /* Invalidate All User ATCs */
-
-#define CMMU_ICTL_DID            0x8000   /* Double instruction disable */
-#define CMMU_ICTL_PREN           0x4000   /* Branch Prediction Enable */
-#define CMMU_ICTL_FRZ0           0x0100   /* Inst Cache Freeze Bank 0 */
-#define CMMU_ICTL_FRZ1           0x0080   /* Inst Cache Freeze Bank 1 */
-#define CMMU_ICTL_HTEN           0x0040   /* Hardware Table Search Enable */
-#define CMMU_ICTL_MEN            0x0020   /* Inst MMU Enable */
-#define CMMU_ICTL_BEN            0x0004   /* TIC Cache Enable */
-#define CMMU_ICTL_CEN            0x0001   /* Inst Cache Enable */
-
-#define CMMU_ISR_TBE             0x200000 /* Table Search Bus Error */
-#define CMMU_ISR_SI              0x100000 /* Segment Fault*/
-#define CMMU_ISR_PI              0x080000 /* Page Fault */
-#define CMMU_ISR_SP              0x040000 /* Supervisor Protection Violation */
-#define CMMU_ISR_PH              0x000800 /* PATC Hit */
-#define CMMU_ISR_BH              0x000400 /* BATC Hit */
-#define CMMU_ISR_SU              0x000200 /* Supervisor Bit */
-#define CMMU_ISR_BE              0x000001 /* Bus Error */
-
-#define CMMU_DCMD_FLUSH_PG       0x000    /* Flush Data Cache Page (sync) */
-#define CMMU_DCMD_INV_ALL        0x001    /* Invalidate Data Cache All */
-#define CMMU_DCMD_FLUSH_ALL      0x002    /* Flush Data Cache All (sync) */
-#define CMMU_DCMD_FLUSH_ALL_INV  0x003    /* Flush Data Cache All (sync & inval) */
-#define CMMU_DCMD_FLUSH_PG_INV   0x004    /* Flush Data Cache Page (sync & inval) */
-#define CMMU_DCMD_INV_LINE       0x005    /* Invalidate Data Cache Line */
-#define CMMU_DCMD_FLUSH_LINE     0x006    /* Flush Data Cache Line (sync)*/
-#define CMMU_DCMD_FLUSH_LINE_INV 0x007    /* Flush Data Cache Line (sync & inval)*/
-#define CMMU_DCMD_PRB_SUPR       0x008    /* MMU Probe Supervisor */
-#define CMMU_DCMD_PRB_USER       0x009    /* MMU Probe User */
-#define CMMU_DCMD_INV_SATC       0x00A    /* Invalidate All Supervisor ATCs */
-#define CMMU_DCMD_INV_UATC       0x00B    /* Invalidate All User ATCs */
-
-#define CMMU_DCTL_RSVD7          0x40000   /* Reserved */
-#define CMMU_DCTL_RSVD6          0x20000   /* Reserved */
-#define CMMU_DCTL_RSVD5          0x10000   /* Reserved */
-#define CMMU_DCTL_RSVD4          0x8000   /* Reserved */
-#define CMMU_DCTL_RSVD3          0x4000   /* Reserved */
-#define CMMU_DCTL_XMEM           0x2000   /* store -> load sequence */
-#define CMMU_DCTL_DEN            0x1000   /* Decoupled Cache Access Enable */
-#define CMMU_DCTL_FWT            0x0800   /* Force Write Through */
-#define CMMU_DCTL_BPEN1          0x0400   /* Break Point Enable 1 */
-#define CMMU_DCTL_BPEN0          0x0200   /* Break Point Enable 0 */
-#define CMMU_DCTL_FRZ0           0x0100   /* Data Cache Freeze Bank 0 */
-#define CMMU_DCTL_FRZ1           0x0080   /* Data Cache Freeze Bank 1 */
-#define CMMU_DCTL_HTEN           0x0040   /* Hardware Table Search Enable */
-#define CMMU_DCTL_MEN            0x0020   /* Data MMU Enable */
-#define CMMU_DCTL_RSVD2          0x0010   /* Reserved */
-#define CMMU_DCTL_ADS            0x0008   /* Allocat Disable */
-#define CMMU_DCTL_RSVD1          0x0004   /* Reserved */
-#define CMMU_DCTL_SEN            0x0002   /* Data Cache Snoop Enable */
-#define CMMU_DCTL_CEN            0x0001   /* Data Cache Enable */
-
-#define CMMU_DSR_TBE             0x200000 /* Table Search Bus Error */
-#define CMMU_DSR_SI              0x100000 /* Segment Fault*/
-#define CMMU_DSR_PI              0x080000 /* Page Fault */
-#define CMMU_DSR_SP              0x040000 /* Supervisor Protection Violation */
-#define CMMU_DSR_WE              0x020000 /* Write Protection Violation */
-#define CMMU_DSR_BPE             0x010000 /* Break Point Exception */
-#define CMMU_DSR_PH              0x000800 /* PATC Hit */
-#define CMMU_DSR_BH              0x000400 /* BATC Hit */
-#define CMMU_DSR_SU              0x000200 /* Supervisor Bit */
-#define CMMU_DSR_RW              0x000100 /* Read Bit */
-#define CMMU_DSR_CP              0x000004 /* Copyback Error */
-#define CMMU_DSR_WA              0x000002 /* Write-Allocate Bus Error */
-#define CMMU_DSR_BE              0x000001 /* Bus Error */
+#define	CMMU_ICMD_INV_ITIC	0x001	/* Invalidate Inst Cache & TIC */
+#define	CMMU_ICMD_INV_TIC	0x002	/* Invalidate TIC */
+#define	CMMU_ICMD_INV_LINE	0x005	/* Invalidate Inst Cache Line */
+#define	CMMU_ICMD_PRB_SUPR	0x008	/* MMU Probe Supervisor */
+#define	CMMU_ICMD_PRB_USER	0x009	/* MMU Probe User */
+#define	CMMU_ICMD_INV_SATC	0x00a	/* Invalidate All Supervisor ATCs */
+#define	CMMU_ICMD_INV_UATC	0x00b	/* Invalidate All User ATCs */
+
+#define	CMMU_ICTL_DID		0x8000	/* Double instruction disable */
+#define	CMMU_ICTL_PREN		0x4000	/* Branch Prediction Enable */
+#define	CMMU_ICTL_FRZ0		0x0100	/* Inst Cache Freeze Bank 0 */
+#define	CMMU_ICTL_FRZ1		0x0080	/* Inst Cache Freeze Bank 1 */
+#define	CMMU_ICTL_HTEN		0x0040	/* Hardware Table Search Enable */
+#define	CMMU_ICTL_MEN		0x0020	/* Inst MMU Enable */
+#define	CMMU_ICTL_BEN		0x0004	/* TIC Cache Enable */
+#define	CMMU_ICTL_CEN		0x0001	/* Inst Cache Enable */
+
+#define	CMMU_ISR_TBE		0x200000 /* Table Search Bus Error */
+#define	CMMU_ISR_SI		0x100000 /* Segment Fault*/
+#define	CMMU_ISR_PI		0x080000 /* Page Fault */
+#define	CMMU_ISR_SP		0x040000 /* Supervisor Protection Violation */
+#define	CMMU_ISR_PH		0x000800 /* PATC Hit */
+#define	CMMU_ISR_BH		0x000400 /* BATC Hit */
+#define	CMMU_ISR_SU		0x000200 /* Supervisor Bit */
+#define	CMMU_ISR_BE		0x000001 /* Bus Error */
+
+#define	CMMU_DCMD_WB_PG		0x000	/* Flush Data Cache Page (sync) */
+#define	CMMU_DCMD_INV_ALL	0x001	/* Invalidate Data Cache All */
+#define	CMMU_DCMD_WB_ALL	0x002	/* Flush Data Cache All (sync) */
+#define	CMMU_DCMD_WBINV_ALL	0x003	/* Flush Data Cache All (sync + inv) */
+#define	CMMU_DCMD_WBINV_PG	0x004	/* Flush Data Cache Page (sync + inv) */
+#define	CMMU_DCMD_INV_LINE	0x005	/* Invalidate Data Cache Line */
+#define	CMMU_DCMD_WB_LINE	0x006	/* Flush Data Cache Line (sync) */
+#define	CMMU_DCMD_WBINV_LINE	0x007	/* Flush Data Cache Line (sync + inv) */
+#define	CMMU_DCMD_PRB_SUPR	0x008	/* MMU Probe Supervisor */
+#define	CMMU_DCMD_PRB_USER	0x009	/* MMU Probe User */
+#define	CMMU_DCMD_INV_SATC	0x00a	/* Invalidate All Supervisor ATCs */
+#define	CMMU_DCMD_INV_UATC	0x00b	/* Invalidate All User ATCs */
+
+#define	CMMU_DCTL_RSVD7		0x40000	/* Reserved */
+#define	CMMU_DCTL_RSVD6		0x20000	/* Reserved */
+#define	CMMU_DCTL_RSVD5		0x10000	/* Reserved */
+#define	CMMU_DCTL_RSVD4		0x8000	/* Reserved */
+#define	CMMU_DCTL_RSVD3		0x4000	/* Reserved */
+#define	CMMU_DCTL_XMEM		0x2000	/* store -> load sequence */
+#define	CMMU_DCTL_DEN		0x1000	/* Decoupled Cache Access Enable */
+#define	CMMU_DCTL_FWT		0x0800	/* Force Write Through */
+#define	CMMU_DCTL_BPEN1		0x0400	/* Break Point Enable 1 */
+#define	CMMU_DCTL_BPEN0		0x0200	/* Break Point Enable 0 */
+#define	CMMU_DCTL_FRZ0		0x0100	/* Data Cache Freeze Bank 0 */
+#define	CMMU_DCTL_FRZ1		0x0080	/* Data Cache Freeze Bank 1 */
+#define	CMMU_DCTL_HTEN		0x0040	/* Hardware Table Search Enable */
+#define	CMMU_DCTL_MEN		0x0020	/* Data MMU Enable */
+#define	CMMU_DCTL_RSVD2		0x0010	/* Reserved */
+#define	CMMU_DCTL_ADS		0x0008	/* Allocate Disable */
+#define	CMMU_DCTL_RSVD1		0x0004	/* Reserved */
+#define	CMMU_DCTL_SEN		0x0002	/* Data Cache Snoop Enable */
+#define	CMMU_DCTL_CEN		0x0001	/* Data Cache Enable */
+
+#define	CMMU_DSR_TBE		0x200000 /* Table Search Bus Error */
+#define	CMMU_DSR_SI		0x100000 /* Segment Fault */
+#define	CMMU_DSR_PI		0x080000 /* Page Fault */
+#define	CMMU_DSR_SP		0x040000 /* Supervisor Protection Violation */
+#define	CMMU_DSR_WE		0x020000 /* Write Protection Violation */
+#define	CMMU_DSR_BPE		0x010000 /* Break Point Exception */
+#define	CMMU_DSR_PH		0x000800 /* PATC Hit */
+#define	CMMU_DSR_BH		0x000400 /* BATC Hit */
+#define	CMMU_DSR_SU		0x000200 /* Supervisor Bit */
+#define	CMMU_DSR_RW		0x000100 /* Read Bit */
+#define	CMMU_DSR_CP		0x000004 /* Copyback Error */
+#define	CMMU_DSR_WA		0x000002 /* Write-Allocate Bus Error */
+#define	CMMU_DSR_BE		0x000001 /* Bus Error */
 
 /* definitions for use of the BATC */
-#define BATC_512K	(0x00 << BATC_BLKSHIFT)
-#define BATC_1M		(0x01 << BATC_BLKSHIFT)
-#define BATC_2M		(0x03 << BATC_BLKSHIFT)
-#define BATC_4M		(0x07 << BATC_BLKSHIFT)
-#define BATC_8M		(0x0f << BATC_BLKSHIFT)
-#define BATC_16M	(0x1f << BATC_BLKSHIFT)
-#define BATC_32M	(0x3f << BATC_BLKSHIFT)
-#define BATC_64M	(0x7f << BATC_BLKSHIFT)
+#define	BATC_512K		(0x00 << BATC_BLKSHIFT)
+#define	BATC_1M			(0x01 << BATC_BLKSHIFT)
+#define	BATC_2M			(0x03 << BATC_BLKSHIFT)
+#define	BATC_4M			(0x07 << BATC_BLKSHIFT)
+#define	BATC_8M			(0x0f << BATC_BLKSHIFT)
+#define	BATC_16M		(0x1f << BATC_BLKSHIFT)
+#define	BATC_32M		(0x3f << BATC_BLKSHIFT)
+#define	BATC_64M		(0x7f << BATC_BLKSHIFT)
 
 /*
  * Cache line information
@@ -128,23 +128,23 @@ u_int	get_dctl(void);
  */
 
 static __inline__ void
-mc88110_flush_data_line(paddr_t x)
+mc88110_wb_data_line(paddr_t x)
 {
 	set_dsar(x);
-	set_dcmd(CMMU_DCMD_FLUSH_LINE);
+	set_dcmd(CMMU_DCMD_WB_LINE);
 }
 
 static __inline__ void
-mc88110_flush_data_page(paddr_t x)
+mc88110_wb_data_page(paddr_t x)
 {
 	set_dsar(x);
-	set_dcmd(CMMU_DCMD_FLUSH_PG);
+	set_dcmd(CMMU_DCMD_WB_PG);
 }
 
 static __inline__ void
-mc88110_flush_data(void)
+mc88110_wb_data(void)
 {
-	set_dcmd(CMMU_DCMD_FLUSH_ALL);
+	set_dcmd(CMMU_DCMD_WB_ALL);
 }
 
 static __inline__ void
@@ -161,23 +161,23 @@ mc88110_inval_data(void)
 }
 
 static __inline__ void
-mc88110_sync_data_line(paddr_t x)
+mc88110_wbinv_data_line(paddr_t x)
 {
 	set_dsar(x);
-	set_dcmd(CMMU_DCMD_FLUSH_LINE_INV);
+	set_dcmd(CMMU_DCMD_WBINV_LINE);
 }
 
 static __inline__ void
-mc88110_sync_data_page(paddr_t x)
+mc88110_wbinv_data_page(paddr_t x)
 {
 	set_dsar(x);
-	set_dcmd(CMMU_DCMD_FLUSH_PG_INV);
+	set_dcmd(CMMU_DCMD_WBINV_PG);
 }
 
 static __inline__ void
-mc88110_sync_data(void)
+mc88110_wbinv_data(void)
 {
-	set_dcmd(CMMU_DCMD_FLUSH_ALL_INV);
+	set_dcmd(CMMU_DCMD_WBINV_ALL);
 }
 
 static __inline__ void
diff --git a/sys/arch/mvme88k/include/m88410.h b/sys/arch/mvme88k/include/m88410.h
index d0b5d464823..02a969450ff 100644
--- a/sys/arch/mvme88k/include/m88410.h
+++ b/sys/arch/mvme88k/include/m88410.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88410.h,v 1.12 2005/12/12 20:36:32 miod Exp $ */
+/*	$OpenBSD: m88410.h,v 1.13 2010/12/31 20:54:21 miod Exp $ */
 /*
  * Copyright (c) 2001 Steve Murphree, Jr.
  * All rights reserved.
@@ -42,15 +42,15 @@
 
 #include <mvme88k/dev/busswreg.h>
 
-void	mc88410_flush_page(paddr_t);
-void	mc88410_flush(void);
-void	mc88410_inval(void);
+void	mc88410_wb_page(paddr_t);
+void	mc88410_wb(void);
+void	mc88410_inv(void);
 
 static __inline__ void
-mc88410_sync(void)
+mc88410_wbinv(void)
 {
-	mc88410_flush();
-	mc88410_inval();
+	mc88410_wb();
+	mc88410_inv();
 }
 
 static __inline__ int
diff --git a/sys/arch/mvme88k/mvme88k/m197_machdep.c b/sys/arch/mvme88k/mvme88k/m197_machdep.c
index 518075852d2..863997d2ad0 100644
--- a/sys/arch/mvme88k/mvme88k/m197_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/m197_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m197_machdep.c,v 1.42 2010/06/22 17:42:37 miod Exp $	*/
+/*	$OpenBSD: m197_machdep.c,v 1.43 2010/12/31 20:54:21 miod Exp $	*/
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -603,16 +603,16 @@ m197_ipi_handler(struct trapframe *eframe)
 		arg2 = ci->ci_ipi_arg2;
 
 		if (ipi & CI_IPI_TLB_FLUSH_KERNEL) {
-			cmmu_flush_tlb(ci->ci_cpuid, 1, 0, 0);
+			cmmu_tlb_inv(ci->ci_cpuid, 1, 0, 0);
 		}
 		else if (ipi & CI_IPI_TLB_FLUSH_USER) {
-			cmmu_flush_tlb(ci->ci_cpuid, 0, 0, 0);
+			cmmu_tlb_inv(ci->ci_cpuid, 0, 0, 0);
 		}
 		else if (ipi & CI_IPI_CACHE_FLUSH) {
-			cmmu_flush_cache(ci->ci_cpuid, arg1, arg2);
+			cmmu_cache_wbinv(ci->ci_cpuid, arg1, arg2);
 		}
 		else if (ipi & CI_IPI_ICACHE_FLUSH) {
-			cmmu_flush_inst_cache(ci->ci_cpuid, arg1, arg2);
+			cmmu_icache_inv(ci->ci_cpuid, arg1, arg2);
 		}
 		else if (ipi & CI_IPI_DMA_CACHECTL) {
 			dma_cachectl_local(arg1, arg2, DMA_CACHE_INV);
diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c
index c6a9d3b6c0a..278818c7935 100644
--- a/sys/arch/mvme88k/mvme88k/m88110.c
+++ b/sys/arch/mvme88k/mvme88k/m88110.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.c,v 1.65 2010/06/22 17:42:37 miod Exp $	*/
+/*	$OpenBSD: m88110.c,v 1.66 2010/12/31 20:54:21 miod Exp $	*/
 /*
  * Copyright (c) 1998 Steve Murphree, Jr.
  * All rights reserved.
@@ -85,12 +85,12 @@ void	m88110_shutdown(void);
 cpuid_t	m88110_cpu_number(void);
 void	m88110_set_sapr(apr_t);
 void	m88110_set_uapr(apr_t);
-void	m88110_flush_tlb(cpuid_t, u_int, vaddr_t, u_int);
-void	m88410_flush_tlb(cpuid_t, u_int, vaddr_t, u_int);
-void	m88110_flush_cache(cpuid_t, paddr_t, psize_t);
-void	m88410_flush_cache(cpuid_t, paddr_t, psize_t);
-void	m88110_flush_inst_cache(cpuid_t, paddr_t, psize_t);
-void	m88410_flush_inst_cache(cpuid_t, paddr_t, psize_t);
+void	m88110_tlb_inv(cpuid_t, u_int, vaddr_t, u_int);
+void	m88410_tlb_inv(cpuid_t, u_int, vaddr_t, u_int);
+void	m88110_cache_wbinv(cpuid_t, paddr_t, psize_t);
+void	m88410_cache_wbinv(cpuid_t, paddr_t, psize_t);
+void	m88110_icache_inv(cpuid_t, paddr_t, psize_t);
+void	m88410_icache_inv(cpuid_t, paddr_t, psize_t);
 void	m88110_dma_cachectl(paddr_t, psize_t, int);
 void	m88110_dma_cachectl_local(paddr_t, psize_t, int);
 void	m88410_dma_cachectl(paddr_t, psize_t, int);
@@ -110,9 +110,9 @@ struct cmmu_p cmmu88110 = {
 	m88110_cpu_number,
 	m88110_set_sapr,
 	m88110_set_uapr,
-	m88110_flush_tlb,
-	m88110_flush_cache,
-	m88110_flush_inst_cache,
+	m88110_tlb_inv,
+	m88110_cache_wbinv,
+	m88110_icache_inv,
 	m88110_dma_cachectl,
 #ifdef MULTIPROCESSOR
 	m88110_dma_cachectl_local,
@@ -132,9 +132,9 @@ struct cmmu_p cmmu88410 = {
 	m88110_cpu_number,
 	m88110_set_sapr,
 	m88110_set_uapr,
-	m88110_flush_tlb,
-	m88410_flush_cache,
-	m88410_flush_inst_cache,
+	m88110_tlb_inv,
+	m88410_cache_wbinv,
+	m88410_icache_inv,
 	m88410_dma_cachectl,
 #ifdef MULTIPROCESSOR
 	m88410_dma_cachectl_local,
@@ -378,9 +378,9 @@ m88410_initialize_cpu(cpuid_t cpu)
 			junk += *(uint32_t *)va;
 
 		/* to make sure the above loop isn't optimized away */
-		mc88110_sync_data_page(junk & PAGE_SIZE);
+		mc88110_wbinv_data_page(junk & PAGE_SIZE);
 	}
-	mc88410_flush();
+	mc88410_wb();
 	mc88410_inval();
 #endif
 	CMMU_UNLOCK;
@@ -443,7 +443,7 @@ m88110_set_uapr(apr_t ap)
  *	flush any tlb
  */
 void
-m88110_flush_tlb(cpuid_t cpu, u_int kernel, vaddr_t vaddr, u_int count)
+m88110_tlb_inv(cpuid_t cpu, u_int kernel, vaddr_t vaddr, u_int count)
 {
 	u_int32_t psr;
 #ifdef MULTIPROCESSOR
@@ -520,7 +520,7 @@ m88110_flush_tlb(cpuid_t cpu, u_int kernel, vaddr_t vaddr, u_int count)
  */
 
 void
-m88110_flush_cache(cpuid_t cpu, paddr_t pa, psize_t size)
+m88110_cache_wbinv(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 
@@ -528,13 +528,13 @@ m88110_flush_cache(cpuid_t cpu, paddr_t pa, psize_t size)
 	set_psr(psr | PSR_IND);
 
 	mc88110_inval_inst();
-	mc88110_flush_data();
+	mc88110_wb_data();
 
 	set_psr(psr);
 }
 
 void
-m88410_flush_cache(cpuid_t cpu, paddr_t pa, psize_t size)
+m88410_cache_wbinv(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 #ifdef MULTIPROCESSOR
@@ -551,9 +551,9 @@ m88410_flush_cache(cpuid_t cpu, paddr_t pa, psize_t size)
 
 	mc88110_inval_inst();
 	/* flush all data to avoid errata invalidate */
-	mc88110_flush_data();
+	mc88110_wb_data();
 	CMMU_LOCK;
-	mc88410_flush();
+	mc88410_wb();
 	CMMU_UNLOCK;
 
 	set_psr(psr);
@@ -564,14 +564,14 @@ m88410_flush_cache(cpuid_t cpu, paddr_t pa, psize_t size)
  */
 
 void
-m88110_flush_inst_cache(cpuid_t cpu, paddr_t pa, psize_t size)
+m88110_icache_inv(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	/* atomic so no psr games */
 	mc88110_inval_inst();
 }
 
 void
-m88410_flush_inst_cache(cpuid_t cpu, paddr_t pa, psize_t size)
+m88410_icache_inv(cpuid_t cpu, paddr_t pa, psize_t size)
 {
 	u_int32_t psr;
 #ifdef MULTIPROCESSOR
@@ -588,7 +588,7 @@ m88410_flush_inst_cache(cpuid_t cpu, paddr_t pa, psize_t size)
 
 	mc88110_inval_inst();
 	CMMU_LOCK;
-	mc88410_flush();
+	mc88410_wb();
 	CMMU_UNLOCK;
 
 	set_psr(psr);
@@ -602,12 +602,12 @@ void
 m88110_cmmu_sync_cache(paddr_t pa, psize_t size)
 {
 #ifdef ENABLE_88110_ERRATA_17
-	mc88110_flush_data_page(pa);
+	mc88110_wb_data_page(pa);
 #else
 	if (size <= MC88110_CACHE_LINE)
-		mc88110_flush_data_line(pa);
+		mc88110_wb_data_line(pa);
 	else
-		mc88110_flush_data_page(pa);
+		mc88110_wb_data_page(pa);
 #endif
 }
 
@@ -615,13 +615,13 @@ void
 m88110_cmmu_sync_inval_cache(paddr_t pa, psize_t size)
 {
 #ifdef ENABLE_88110_ERRATA_17
-	mc88110_flush_data_page(pa);
-	mc88110_sync_data_page(pa);
+	mc88110_wb_data_page(pa);
+	mc88110_wbinv_data_page(pa);
 #else
 	if (size <= MC88110_CACHE_LINE)
-		mc88110_sync_data_line(pa);
+		mc88110_wbinv_data_line(pa);
 	else
-		mc88110_sync_data_page(pa);
+		mc88110_wbinv_data_page(pa);
 #endif
 }
 
@@ -711,12 +711,12 @@ m88410_dma_cachectl_local(paddr_t pa, psize_t size, int op)
 	case DMA_CACHE_SYNC:
 #if 0
 		flusher = m88110_cmmu_sync_cache;
-		ext_flusher = mc88410_flush;
+		ext_flusher = mc88410_wb;
 #endif
 		break;
 	case DMA_CACHE_SYNC_INVAL:
 		flusher = m88110_cmmu_sync_inval_cache;
-		ext_flusher = mc88410_sync;
+		ext_flusher = mc88410_wbinv;
 		break;
 	default:
 #ifdef ENABLE_88110_ERRATA_17
@@ -727,7 +727,7 @@ m88410_dma_cachectl_local(paddr_t pa, psize_t size, int op)
 #ifdef notyet
 		ext_flusher = mc88410_inval;
 #else
-		ext_flusher = mc88410_sync;
+		ext_flusher = mc88410_wbinv;
 #endif
 		break;
 	}
@@ -739,7 +739,7 @@ m88410_dma_cachectl_local(paddr_t pa, psize_t size, int op)
 		CMMU_LOCK;
 		while (size != 0) {
 			m88110_cmmu_sync_cache(pa, PAGE_SIZE);
-			mc88410_flush_page(pa);
+			mc88410_wb_page(pa);
 			pa += PAGE_SIZE;
 			size -= PAGE_SIZE;
 		}
diff --git a/sys/arch/mvme88k/mvme88k/m88410.c b/sys/arch/mvme88k/mvme88k/m88410.c
index 1b5217a0b8f..a2f9938d9ea 100644
--- a/sys/arch/mvme88k/mvme88k/m88410.c
+++ b/sys/arch/mvme88k/mvme88k/m88410.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88410.c,v 1.4 2009/02/27 05:17:53 miod Exp $	*/
+/*	$OpenBSD: m88410.c,v 1.5 2010/12/31 20:54:21 miod Exp $	*/
 /*
  * Copyright (c) 2001 Steve Murphree, Jr.
  * All rights reserved.
@@ -48,18 +48,18 @@
  */
 
 /*
- * Flush physical page number (specified in the low 20 bits of the
+ * Writeback physical page number (specified in the low 20 bits of the
  * address).
  */
-#define XCC_FLUSH_PAGE	0x01
+#define XCC_WB_PAGE	0x01
 /*
- * Flush the whole cache.
+ * Writeback the whole cache.
  */
-#define XCC_FLUSH_ALL	0x02
+#define XCC_WB_ALL	0x02
 /*
  * Invalidate the whole cache.
  */
-#define XCC_INVAL_ALL	0x03
+#define XCC_INV_ALL	0x03
 
 /*
  * Base address of the 88410 when mapped.
@@ -67,7 +67,7 @@
 #define XCC_ADDR	0xff800000
 
 void
-mc88410_flush_page(paddr_t physaddr)
+mc88410_wb_page(paddr_t physaddr)
 {
 	paddr_t xccaddr = XCC_ADDR | (physaddr >> PGSHIFT);
 	u_int psr;
@@ -93,7 +93,7 @@ mc88410_flush_page(paddr_t physaddr)
 	__asm__ __volatile__ (
 	    "or   r2, r0, %0\n\t"
 	    "or   r3, r0, r0\n\t"
-	    "st.d r2, %1, 0" : : "i" (XCC_FLUSH_PAGE), "r" (xccaddr) : "r2", "r3");
+	    "st.d r2, %1, 0" : : "i" (XCC_WB_PAGE), "r" (xccaddr) : "r2", "r3");
 
 	/* spin until the operation is complete */
 	while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) != 0)
@@ -107,7 +107,7 @@ mc88410_flush_page(paddr_t physaddr)
 }
 
 void
-mc88410_flush(void)
+mc88410_wb(void)
 {
 	u_int16_t bs_gcsr, bs_romcr;
 
@@ -125,7 +125,7 @@ mc88410_flush(void)
 	__asm__ __volatile__ (
 	    "or   r2, r0, %0\n\t"
 	    "or   r3, r0, r0\n\t"
-	    "st.d r2, %1, 0" : : "i" (XCC_FLUSH_ALL), "r" (XCC_ADDR) : "r2", "r3");
+	    "st.d r2, %1, 0" : : "i" (XCC_WB_ALL), "r" (XCC_ADDR) : "r2", "r3");
 
 	/* spin until the operation is complete */
 	while ((*(volatile u_int32_t *)(BS_BASE + BS_XCCR) & BS_XCC_FBSY) != 0)
@@ -136,7 +136,7 @@ mc88410_flush(void)
 }
 
 void
-mc88410_inval(void)
+mc88410_inv(void)
 {
 	u_int16_t bs_gcsr, bs_romcr;
 	u_int32_t dummy;
@@ -155,7 +155,7 @@ mc88410_inval(void)
 	__asm__ __volatile__ (
 	    "or   r2, r0, %0\n\t"
 	    "or   r3, r0, r0\n\t"
-	    "st.d r2, %1, 0" : : "i" (XCC_INVAL_ALL), "r" (XCC_ADDR) : "r2", "r3");
+	    "st.d r2, %1, 0" : : "i" (XCC_INV_ALL), "r" (XCC_ADDR) : "r2", "r3");
 
 	/*
 	 * The 88410 will not let the 88110 access it until the