Remove the last debug bit from the PSR on 88110: do not force memory accesses

instructions to be serialized (this defeats the purpose of having a superscalar
processor, and accesses to volatile variables are done with explicit memory
barriers anyway).

This brings a HUGE speedup: openssl speed -elapsed shows AES is 90% faster,
blowfish is 75% faster, and sha1 is 50% faster. Not so bad!

However, doing this increases the pressure on the processor bus, so it is
necessary to increase the processor bus timeout on 40MHz boards again (to 256
usec). ``black cat'' 50MHz boards seem to be unaffected, so they remain at
64 usec.

2 files changed, 37 insertions, 30 deletions

diff --git a/sys/arch/mvme88k/mvme88k/m197_machdep.c b/sys/arch/mvme88k/mvme88k/m197_machdep.c
index eda80736450..9f2e2ead8ee 100644
--- a/sys/arch/mvme88k/mvme88k/m197_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/m197_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m197_machdep.c,v 1.24 2007/12/25 21:13:11 miod Exp $	*/
+/*	$OpenBSD: m197_machdep.c,v 1.25 2007/12/26 22:21:41 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -336,6 +336,9 @@ m197_bootstrap()
 	extern struct cmmu_p cmmu88410;
 	extern int cpuspeed;
 	u_int16_t cpu;
+#ifndef MULTIPROCESSOR
+	u_int8_t btimer, pbt;
+#endif
 
 	if (mc88410_present()) {
 		cmmu = &cmmu88410;	/* 197SP/197DP */
@@ -359,6 +362,33 @@ m197_bootstrap()
 	 */
 	cpuspeed = 256 - *(volatile u_int8_t *)(BS_BASE + BS_PADJUST);
 
+#ifndef MULTIPROCESSOR
+	/*
+	 * Kernels running without snooping enabled (i.e. without
+	 * CACHE_GLOBAL set in the apr in pmap.c) need increased processor
+	 * bus timeout limits, or the instruction cache might not be able
+	 * to fill or answer fast enough.
+	 *
+	 * Do this as soon as possible (i.e. now...), since this is
+	 * especially critical on 40MHz boards, while some 50MHz boards can
+	 * run without this timeout change... but better be safe than sorry.
+	 */
+	btimer = *(volatile u_int8_t *)(BS_BASE + BS_BTIMER);
+	pbt = btimer & BS_BTIMER_PBT_MASK;
+	btimer = (btimer & ~BS_BTIMER_PBT_MASK);
+	
+	/* PBT256 only be necessary for busswitch rev1? */
+	if (cpuspeed < 50) {
+		if (pbt < BS_BTIMER_PBT256)
+			pbt = BS_BTIMER_PBT256;
+	} else {
+		if (pbt < BS_BTIMER_PBT64)
+			pbt = BS_BTIMER_PBT64;
+	}
+
+	*(volatile u_int8_t *)(BS_BASE + BS_BTIMER) = btimer | pbt;
+#endif
+
 	md_interrupt_func_ptr = m197_ext_int;
 	md_getipl = m197_getipl;
 	md_setipl = m197_setipl;
@@ -384,20 +414,14 @@ m197_send_ipi(int ipi, cpuid_t cpu)
 
 	atomic_setbits_int(&ci->ci_ipi, ipi);
 
-	/*
-	 * If the other processor doesn't have an IPI pending, send one,
-	 * keeping IPIs enabled for us.
-	 */
-	if ((*(volatile u_int8_t *)(BS_BASE + BS_CPINT) & BS_CPI_STAT) == 0)
-		*(volatile u_int8_t *)(BS_BASE + BS_CPINT) =
-		    BS_CPI_SCPI | BS_CPI_IEN;
+	*(volatile u_int8_t *)(BS_BASE + BS_CPINT) = BS_CPI_SCPI | BS_CPI_IEN;
 }
 
 void
 m197_send_complex_ipi(int ipi, cpuid_t cpu, u_int32_t arg1, u_int32_t arg2)
 {
 	struct cpu_info *ci = &m88k_cpus[cpu];
-	int wait = 0;
+	int wait;
 
 	if ((ci->ci_flags & CIF_ALIVE) == 0)
 		return;				/* XXX not ready yet */
@@ -408,7 +432,7 @@ m197_send_complex_ipi(int ipi, cpuid_t cpu, u_int32_t arg1, u_int32_t arg2)
 	/*
 	 * Wait for the other processor to be ready to accept an IPI.
 	 */
-	for (wait = 10000000; wait != 0; wait--) {
+	for (wait = 1000000; wait != 0; wait--) {
 		if (!ISSET(*(volatile u_int8_t *)(BS_BASE + BS_CPINT),
 		    BS_CPI_STAT))
 			break;
diff --git a/sys/arch/mvme88k/mvme88k/m88110.c b/sys/arch/mvme88k/mvme88k/m88110.c
index b816f14dfca..019d2f3d2b2 100644
--- a/sys/arch/mvme88k/mvme88k/m88110.c
+++ b/sys/arch/mvme88k/mvme88k/m88110.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m88110.c,v 1.55 2007/12/25 21:10:56 miod Exp $	*/
+/*	$OpenBSD: m88110.c,v 1.56 2007/12/26 22:21:41 miod Exp $	*/
 /*
  * Copyright (c) 1998 Steve Murphree, Jr.
  * All rights reserved.
@@ -177,13 +177,13 @@ m88410_setup_board_config(void)
 	struct mvmeprom_brdid brdid;
 
 	/*
-	 * MVME197SP are 01-W3815B03, while MVME197DP are 01-W3815B04.
+	 * MVME197SP are 01-W3815B04, while MVME197DP are 01-W3815B03.
 	 * If the CNFG memory has been lost and the board is a 197SP,
 	 * we'll just fail to spin up the non-existing second processor.
 	 */
 	bzero(&brdid, sizeof(brdid));
 	bugbrdid(&brdid);
-	if (bcmp(brdid.pwa, "01-W3815B03", 11) == 0)
+	if (bcmp(brdid.pwa, "01-W3815B04", 11) == 0)
 		max_cpus = 1;
 	else
 		max_cpus = 2;
@@ -264,9 +264,6 @@ void
 m88110_initialize_cpu(cpuid_t cpu)
 {
 	u_int ictl, dctl;
-#ifndef MULTIPROCESSOR
-	u_int8_t btimer;
-#endif
 	int i;
 	int procvers = (get_cpu_pid() & PID_VN) >> VN_SHIFT;
 
@@ -281,20 +278,6 @@ m88110_initialize_cpu(cpuid_t cpu)
 	/* clear PATCs */
 	patc_clear();
 
-#ifndef MULTIPROCESSOR
-	/*
-	 * Kernels running without snooping enabled (i.e. without
-	 * CACHE_GLOBAL set in the apr in pmap.c) need increased processor
-	 * bus timeout limits, or the instruction cache might not be able
-	 * to fill or answer fast enough.  This is especially critical on
-	 * 40MHz boards, while some 50MHz boards can run without this
-	 * timeout change... but better be safe than sorry.
-	 */
-	btimer = *(volatile u_int8_t *)(BS_BASE + BS_BTIMER);
-	btimer = (btimer & ~BS_BTIMER_PBT_MASK) | BS_BTIMER_PBT64;
-	*(volatile u_int8_t *)(BS_BASE + BS_BTIMER) = btimer;
-#endif
-
 	ictl = BATC_512K | CMMU_ICTL_DID | CMMU_ICTL_CEN | CMMU_ICTL_BEN;
 
 	/*