Move more z8536 defines from MVME188 specific code to the MI header and use it.

2 files changed, 21 insertions, 72 deletions

diff --git a/sys/arch/mvme88k/include/mvme188.h b/sys/arch/mvme88k/include/mvme188.h
index 6ef8921c8ae..817af7bb040 100644
--- a/sys/arch/mvme88k/include/mvme188.h
+++ b/sys/arch/mvme88k/include/mvme188.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mvme188.h,v 1.32 2007/12/27 23:17:55 miod Exp $ */
+/*	$OpenBSD: mvme188.h,v 1.33 2009/03/08 16:03:05 miod Exp $ */
 /*
  * Copyright (c) 1999 Steve Murphree, Jr.
  * All rights reserved.
@@ -200,58 +200,6 @@
 #define CIO_PORTA		0xfff83008
 #define CIO_CTRL		0xfff8300c
 
-#define CIO_MICR		0x00	/* Master interrupt control register */
-#define CIO_MICR_MIE		0x80
-#define CIO_MICR_DLC		0x40
-#define CIO_MICR_NV		0x20
-#define CIO_MICR_PAVIS		0x10
-#define CIO_MICR_PBVIS		0x08
-#define CIO_MICR_CTVIS		0x04
-#define CIO_MICR_RJA		0x02
-#define CIO_MICR_RESET		0x01
-
-#define CIO_MCCR		0x01	/* Master config control register */
-#define CIO_MCCR_PBE		0x80
-#define CIO_MCCR_CT1E		0x40
-#define CIO_MCCR_CT2E		0x20
-#define CIO_MCCR_CT3E		0x10
-#define CIO_MCCR_PLC		0x08
-#define CIO_MCCR_PAE		0x04
-
-#define CIO_CTMS1		0x1c	/* Counter/timer mode specification #1 */
-#define CIO_CTMS2		0x1d	/* Counter/timer mode specification #2 */
-#define CIO_CTMS3		0x1e	/* Counter/timer mode specification #3 */
-#define CIO_CTMS_CSC		0x80	/* Continuous Single Cycle */
-#define CIO_CTMS_EOE		0x40	/* External Output Enable  */
-#define CIO_CTMS_ECE		0x20	/* External Count Enable   */
-#define CIO_CTMS_ETE		0x10	/* External Trigger Enable */
-#define CIO_CTMS_EGE		0x08	/* External Gate Enable    */
-#define CIO_CTMS_REB		0x04	/* Retrigger Enable Bit    */
-#define CIO_CTMS_PO		0x00	/* Pulse Output            */
-#define CIO_CTMS_OSO		0x01	/* One Shot Output         */
-#define CIO_CTMS_SWO		0x02	/* Square Wave Output      */
-
-#define CIO_IVR			0x04	/* Interrupt vector register */
-
-#define CIO_CSR1		0x0a	/* Command and status register CTC #1 */
-#define CIO_CSR2		0x0b	/* Command and status register CTC #2 */
-#define CIO_CSR3		0x0c	/* Command and status register CTC #3 */
-
-#define CIO_CT1MSB		0x16	/* CTC #1 Timer constant - MSB */
-#define CIO_CT1LSB		0x17	/* CTC #1 Timer constant - LSB */
-#define CIO_CT2MSB		0x18	/* CTC #2 Timer constant - MSB */
-#define CIO_CT2LSB		0x19	/* CTC #2 Timer constant - LSB */
-#define CIO_CT3MSB		0x1a	/* CTC #3 Timer constant - MSB */
-#define CIO_CT3LSB		0x1b	/* CTC #3 Timer constant - LSB */
-#define CIO_PDCA		0x23	/* Port A data direction control */
-#define CIO_PDCB		0x2b	/* Port B data direction control */
-
-#define CIO_GCB			0x04	/* CTC Gate command bit */
-#define CIO_TCB			0x02	/* CTC Trigger command bit */
-#define CIO_IE			0xc0	/* CTC Interrupt enable (set) */
-#define CIO_CIP			0x20	/* CTC Clear interrupt pending */
-#define CIO_IP			0x20	/* CTC Interrupt pending */
-
 #define DART_BASE		0xfff82000
 
 /*
diff --git a/sys/arch/mvme88k/mvme88k/m188_machdep.c b/sys/arch/mvme88k/mvme88k/m188_machdep.c
index 9ed61c605d1..d2c9b3fbabc 100644
--- a/sys/arch/mvme88k/mvme88k/m188_machdep.c
+++ b/sys/arch/mvme88k/mvme88k/m188_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: m188_machdep.c,v 1.50 2009/02/21 18:37:48 miod Exp $	*/
+/*	$OpenBSD: m188_machdep.c,v 1.51 2009/03/08 16:03:06 miod Exp $	*/
 /*
  * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
  * Copyright (c) 1996 Nivas Madhur
@@ -127,6 +127,7 @@
 #include <machine/mvme188.h>
 
 #include <mvme88k/dev/sysconvar.h>
+#include <dev/ic/z8536reg.h>
 #include <mvme88k/mvme88k/clockvar.h>
 
 #ifdef MULTIPROCESSOR
@@ -854,10 +855,10 @@ int
 m188_calibrateintr(void *eframe)
 {
 	CIO_LOCK();
-	write_cio(CIO_CSR1, CIO_GCB | CIO_CIP);  /* Ack the interrupt */
-
+	/* ack the interrupt */
+	write_cio(ZCIO_CT1CS, ZCIO_CTCS_GCB | ZCIO_CTCS_C_IP); 
 	/* restart counter */
-	write_cio(CIO_CSR1, CIO_GCB | CIO_TCB | CIO_IE);
+	write_cio(ZCIO_CT1CS, ZCIO_CTCS_GCB | ZCIO_CTCS_TCB | ZCIO_CTCS_S_IE);
 	CIO_UNLOCK();
 
 	m188_calibrate_phase++;
@@ -869,10 +870,10 @@ int
 m188_clockintr(void *eframe)
 {
 	CIO_LOCK();
-	write_cio(CIO_CSR1, CIO_GCB | CIO_CIP);  /* Ack the interrupt */
-
+	/* ack the interrupt */
+	write_cio(ZCIO_CT1CS, ZCIO_CTCS_GCB | ZCIO_CTCS_C_IP); 
 	/* restart counter */
-	write_cio(CIO_CSR1, CIO_GCB | CIO_TCB | CIO_IE);
+	write_cio(ZCIO_CT1CS, ZCIO_CTCS_GCB | ZCIO_CTCS_TCB | ZCIO_CTCS_S_IE);
 	CIO_UNLOCK();
 
 	hardclock(eframe);
@@ -971,28 +972,28 @@ m188_cio_init(u_int period)
 	volatile int i;
 
 	/* Start by forcing chip into known state */
-	read_cio(CIO_MICR);
-	write_cio(CIO_MICR, CIO_MICR_RESET);	/* Reset the CTC */
+	read_cio(ZCIO_MIC);
+	write_cio(ZCIO_MIC, ZCIO_MIC_RESET);	/* Reset the CTC */
 	for (i = 0; i < 1000; i++)	 	/* Loop to delay */
 		;
 
 	/* Clear reset and start init seq. */
-	write_cio(CIO_MICR, 0x00);
+	write_cio(ZCIO_MIC, 0x00);
 
 	/* Wait for chip to come ready */
-	while ((read_cio(CIO_MICR) & CIO_MICR_RJA) == 0)
+	while ((read_cio(ZCIO_MIC) & ZCIO_MIC_RJA) == 0)
 		;
 
 	/* Initialize the 8536 for real */
-	write_cio(CIO_MICR,
-	    CIO_MICR_MIE /* | CIO_MICR_NV */ | CIO_MICR_RJA | CIO_MICR_DLC);
-	write_cio(CIO_CTMS1, CIO_CTMS_CSC);	/* Continuous count */
-	write_cio(CIO_PDCB, 0xff);		/* set port B to input */
+	write_cio(ZCIO_MIC,
+	    ZCIO_MIC_MIE /* | ZCIO_MIC_NV */ | ZCIO_MIC_RJA | ZCIO_MIC_DLC);
+	write_cio(ZCIO_CT1MD, ZCIO_CTMD_CSC);	/* Continuous count */
+	write_cio(ZCIO_PBDIR, 0xff);		/* set port B to input */
 
 	period <<= 1;	/* CT#1 runs at PCLK/2, hence 2MHz */
-	write_cio(CIO_CT1MSB, period >> 8);
-	write_cio(CIO_CT1LSB, period);
+	write_cio(ZCIO_CT1TCM, period >> 8);
+	write_cio(ZCIO_CT1TCL, period);
 	/* enable counter #1 */
-	write_cio(CIO_MCCR, CIO_MCCR_CT1E | CIO_MCCR_PBE);
-	write_cio(CIO_CSR1, CIO_GCB | CIO_TCB | CIO_IE);
+	write_cio(ZCIO_MCC, ZCIO_MCC_CT1E | ZCIO_MCC_PBE);
+	write_cio(ZCIO_CT1CS, ZCIO_CTCS_GCB | ZCIO_CTCS_TCB | ZCIO_CTCS_S_IE);
 }