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| author | Miod Vallat <miod@cvs.openbsd.org> | 2010-03-16 17:12:51 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2010-03-16 17:12:51 +0000 |
| commit | e5607f886b5f9d19e6348d4ed71a19dabe5eb63c (patch) | |
| tree | 8b80e8df713f02adda73c9d4bb85493617198ba8 /sys/arch/mvmeppc/conf/RAMDISK | |
| parent | d424582d72e123f5994724c53e6fb3610cf70ee4 (diff) | |
PCXS processors (really, all PA-RISC processors with separate I and D tlb
entries) may use the DTLB to resolve an address in ficache(), so make sure
pdtlb() always happens after ficache(), not before.
This problem was exposed with revision 1.145 of pmap.c.
ok kettenis@
Diffstat (limited to 'sys/arch/mvmeppc/conf/RAMDISK')
0 files changed, 0 insertions, 0 deletions