update the pmax stuff to NetBSD 961107 - this version i got somehow

compiled on my decstation 2100 (PLUTO) - but it will not fully work
out of the box - but i want to bring it into the tree because i get
my own pmax on 961228 - so that i have a good startpoint then :-)

all the OpenBSD changes to the pmax tree will follow in the next commit

20 files changed, 465 insertions, 722 deletions

diff --git a/sys/arch/pmax/include/aout_machdep.h b/sys/arch/pmax/include/aout_machdep.h
new file mode 100644
index 00000000000..7b6986d0c47
--- /dev/null
+++ b/sys/arch/pmax/include/aout_machdep.h
@@ -0,0 +1,40 @@
+/*	$NetBSD: aout_machdep.h,v 1.5 1994/10/26 21:09:39 cgd Exp $	*/
+
+/*-
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)exec.h	8.1 (Berkeley) 6/10/93
+ */
+
+#define	__LDPGSZ	4096
+
+#include <machine/reloc.h>
diff --git a/sys/arch/pmax/include/autoconf.h b/sys/arch/pmax/include/autoconf.h
index 59c3eaa6791..06416ffb952 100644
--- a/sys/arch/pmax/include/autoconf.h
+++ b/sys/arch/pmax/include/autoconf.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: autoconf.h,v 1.6.4.1 1996/05/30 04:07:36 mhitch Exp $	*/
+/*	$NetBSD: autoconf.h,v 1.7 1996/05/29 06:19:49 mhitch Exp $	*/
 
 /*
  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
diff --git a/sys/arch/pmax/include/cpu.h b/sys/arch/pmax/include/cpu.h
index 4b169358773..5b56410257e 100644
--- a/sys/arch/pmax/include/cpu.h
+++ b/sys/arch/pmax/include/cpu.h
@@ -190,12 +190,10 @@ union cpuprid {
  */
 #define	enablertclock()
 
-#include <pmax/cpuregs.h> /* XXX */
-
+/* Stuff from the NetBSD mips tree TTTTT */
 #define CLKF_USERMODE(framep)   CLKF_USERMODE_R3K(framep)
 #define CLKF_BASEPRI(framep)    CLKF_BASEPRI_R3K(framep)
 
-
 #ifdef _KERNEL
 union   cpuprid cpu_id;
 union   cpuprid fpu_id;
@@ -203,5 +201,6 @@ u_int   machDataCacheSize;
 u_int   machInstCacheSize;
 extern  struct intr_tab intr_tab[];
 #endif
+/* End of stuff from the NetBSD mips tree TTTTT */
 
 #endif /* _CPU_H_ */
diff --git a/sys/arch/pmax/include/ecoff.h b/sys/arch/pmax/include/ecoff.h
index ceee6c6a420..8838d6462a9 100644
--- a/sys/arch/pmax/include/ecoff.h
+++ b/sys/arch/pmax/include/ecoff.h
@@ -1,4 +1,5 @@
-/*	$NetBSD: ecoff.h,v 1.5 1996/05/09 23:46:18 cgd Exp $	*/
+/*	$OpenBSD: ecoff.h,v 1.4 1996/12/22 15:18:10 graichen Exp $	*/
+/*	$NetBSD: ecoff.h,v 1.4 1995/06/16 02:07:33 mellon Exp $	*/
 
 /*
  * Copyright (c) 1994 Adam Glass
@@ -36,11 +37,58 @@
 #define ECOFF_PAD
 
 #define ECOFF_MACHDEP \
-        u_long gprmask; \
-        u_long cprmask[4]; \
-        u_long gp_value
+        u_long ea_gprmask; \
+        u_long ea_cprmask[4]; \
+        u_long ea_gp_value
 
 #define ECOFF_MAGIC_MIPSEL 0x0162
-#define ECOFF_BADMAG(ep) ((ep)->f.f_magic != ECOFF_MAGIC_MIPSEL)
+#define ECOFF_BADMAG(ex) ((ex)->f.f_magic != ECOFF_MAGIC_MIPSEL)
 
 #define ECOFF_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
+
+struct ecoff_symhdr {
+        int16_t         sh_magic;
+        int16_t         sh_vstamp;
+        int32_t         sh_linemax;
+        int32_t         sh_densenummax;
+        int32_t         sh_procmax;
+        int32_t         sh_lsymmax;
+        int32_t         sh_optsymmax;
+        int32_t         sh_auxxymmax;
+        int32_t         sh_lstrmax;
+        int32_t         sh_estrmax;
+        int32_t         sh_fdmax;
+        int32_t         sh_rfdmax;
+        int32_t         sh_esymmax;
+        long            sh_linesize;
+        long            sh_lineoff;
+        long            sh_densenumoff;
+        long            sh_procoff; 
+        long            sh_lsymoff;
+        long            sh_optsymoff;
+        long            sh_auxsymoff;
+        long            sh_lstroff;
+        long            sh_estroff;
+        long            sh_fdoff;
+        long            sh_rfdoff;
+        long            sh_esymoff;
+};
+/* Some day they will make up their minds.... */
+#define	esymMax		sh_esymmax
+#define cbExtOffset	sh_esymoff
+#define	cbSsExtOffset	sh_estroff
+
+struct ecoff_extsym {  
+        long            es_value;
+        int             es_strindex;
+        unsigned        es_type:6;
+        unsigned        es_class:5;
+        unsigned        :1;
+        unsigned        es_symauxindex:20;  
+        unsigned        es_jmptbl:1;
+        unsigned        es_cmain:1;
+        unsigned        es_weakext:1;
+        unsigned        :29;
+        int             es_indexfld; 
+};
+
diff --git a/sys/arch/pmax/include/ecoff_machdep.h b/sys/arch/pmax/include/ecoff_machdep.h
new file mode 100644
index 00000000000..72dba194502
--- /dev/null
+++ b/sys/arch/pmax/include/ecoff_machdep.h
@@ -0,0 +1,46 @@
+/*	$NetBSD: ecoff_machdep.h,v 1.5 1996/05/09 23:46:18 cgd Exp $	*/
+
+/*
+ * Copyright (c) 1994 Adam Glass
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Adam Glass.
+ * 4. The name of the Author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL Adam Glass BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#define ECOFF_LDPGSZ 4096
+
+#define ECOFF_PAD
+
+#define ECOFF_MACHDEP \
+        u_long gprmask; \
+        u_long cprmask[4]; \
+        u_long gp_value
+
+#define ECOFF_MAGIC_MIPSEL 0x0162
+#define ECOFF_BADMAG(ep) ((ep)->f.f_magic != ECOFF_MAGIC_MIPSEL)
+
+#define ECOFF_SEGMENT_ALIGNMENT(ep) ((ep)->a.vstamp < 23 ? 8 : 16)
diff --git a/sys/arch/pmax/include/elf.h b/sys/arch/pmax/include/elf.h
index b14ddc36640..9ea386dc85e 100644
--- a/sys/arch/pmax/include/elf.h
+++ b/sys/arch/pmax/include/elf.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: elf.h,v 1.3.4.1 1996/06/26 06:39:09 jtc Exp $	*/
+/*	$NetBSD: elf.h,v 1.4 1996/06/26 04:41:41 jonathan Exp $	*/
 
 /*
  * Copyright (c) 1994 Ted Lemon
diff --git a/sys/arch/pmax/include/elf_machdep.h b/sys/arch/pmax/include/elf_machdep.h
new file mode 100644
index 00000000000..d93b48b6c93
--- /dev/null
+++ b/sys/arch/pmax/include/elf_machdep.h
@@ -0,0 +1,8 @@
+/*	$NetBSD: elf_machdep.h,v 1.1 1996/09/26 21:50:59 cgd Exp $	*/
+
+#define	ELF32_MACHDEP_ID_CASES						\
+		case Elf_em_mips:					\
+			break;
+
+#define	ELF64_MACHDEP_ID_CASES						\
+		/* no 64-bit ELF machine types supported */
diff --git a/sys/arch/pmax/include/endian.h b/sys/arch/pmax/include/endian.h
index 81ca584b676..968b1d5c446 100644
--- a/sys/arch/pmax/include/endian.h
+++ b/sys/arch/pmax/include/endian.h
@@ -1,5 +1,4 @@
-/*	$OpenBSD: endian.h,v 1.4 1996/11/25 13:11:34 niklas Exp $	*/
-/*	$NetBSD: endian.h,v 1.5.4.1 1996/06/05 23:53:20 jonathan Exp $	*/
+/*	$NetBSD: endian.h,v 1.8 1996/10/13 20:59:02 mhitch Exp $	*/
 
 /*
  * Copyright (c) 1987, 1991, 1993
@@ -57,18 +56,21 @@
  */
 #define	LITTLE_ENDIAN	1234	/* LSB first: i386, vax */
 #define	BIG_ENDIAN	4321	/* MSB first: 68000, ibm, net */
-#define	PDP_ENDIAN	3412	/* LSB first in word, MSW first in int32_t */
+#define	PDP_ENDIAN	3412	/* LSB first in word, MSW first in long */
 
 #define	BYTE_ORDER	LITTLE_ENDIAN
 
 #include <sys/cdefs.h>
 #include <pmax/types.h>
 
+typedef u_int32_t	in_addr_t;
+typedef u_int16_t	in_port_t;
+
 __BEGIN_DECLS
-u_int32_t	htonl __P((u_int32_t));
-u_int16_t	htons __P((u_int16_t));
-u_int32_t	ntohl __P((u_int32_t));
-u_int16_t	ntohs __P((u_int16_t));
+in_addr_t	htonl __P((in_addr_t));
+in_port_t	htons __P((in_port_t));
+in_addr_t	ntohl __P((in_addr_t));
+in_port_t	ntohs __P((in_port_t));
 __END_DECLS
 
 /*
@@ -87,10 +89,10 @@ __END_DECLS
 
 #else
 
-#define	NTOHL(x)	(x) = ntohl((u_int32_t)x)
-#define	NTOHS(x)	(x) = ntohs((u_int16_t)x)
-#define	HTONL(x)	(x) = htonl((u_int32_t)x)
-#define	HTONS(x)	(x) = htons((u_int16_t)x)
+#define	NTOHL(x)	(x) = ntohl((in_addr_t)x)
+#define	NTOHS(x)	(x) = ntohs((in_port_t)x)
+#define	HTONL(x)	(x) = htonl((in_addr_t)x)
+#define	HTONS(x)	(x) = htons((in_port_t)x)
 #endif
 #endif /* ! _POSIX_SOURCE */
 #endif /* !_ENDIAN_H_ */
diff --git a/sys/arch/pmax/include/exec.h b/sys/arch/pmax/include/exec.h
index 5325a407c92..8a460086e6f 100644
--- a/sys/arch/pmax/include/exec.h
+++ b/sys/arch/pmax/include/exec.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: exec.h,v 1.4 1996/09/29 11:36:27 deraadt Exp $	*/
+/*	$OpenBSD: exec.h,v 1.5 1996/12/22 15:18:13 graichen Exp $	*/
 /*	$NetBSD: exec.h,v 1.5 1994/10/26 21:09:39 cgd Exp $	*/
 
 /*-
diff --git a/sys/arch/pmax/include/limits.h b/sys/arch/pmax/include/limits.h
index f1d28a3701c..01047a06e1b 100644
--- a/sys/arch/pmax/include/limits.h
+++ b/sys/arch/pmax/include/limits.h
@@ -94,6 +94,9 @@
 #define FLT_MAX		3.40282347E+38F
 #define FLT_MIN		1.17549435E-38F
 #endif
+
+/* Stuff from the NetBSD mips tree TTTTT */
 #ifdef _KERNEL
-#define CLK_TCK		60		/* ticks per second */
+#define CLK_TCK         60              /* ticks per second */
 #endif
+/* End of stuff from the NetBSD mips tree TTTTT */
diff --git a/sys/arch/pmax/include/locore.h b/sys/arch/pmax/include/locore.h
index dda4f72c628..e3235bfff7d 100644
--- a/sys/arch/pmax/include/locore.h
+++ b/sys/arch/pmax/include/locore.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.h,v 1.2 1996/05/20 23:38:26 jonathan Exp $	*/
+/*	$NetBSD: locore.h,v 1.3 1996/10/13 21:37:35 jonathan Exp $	*/
 
 /*
  * Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -58,32 +58,33 @@ extern int switch_exit __P((void)); /* XXX never really returns? */
  * only to print them by name in stack tracebacks
  */
 
-extern void mips_r2000_KernIntr __P(());
+extern void mips1_KernIntr __P((void));
 
-extern void mips_r2000_ConfigCache  __P((void));
-extern void mips_r2000_FlushCache  __P((void));
-extern void mips_r2000_FlushDCache  __P((vm_offset_t addr, vm_offset_t len));
-extern void mips_r2000_FlushICache  __P((vm_offset_t addr, vm_offset_t len));
-extern void mips_r2000_ForceCacheUpdate __P((void));
-extern void mips_r2000_SetPID   __P((int pid));
-extern void mips_r2000_TLBFlush __P((void));
-extern void mips_r2000_TLBFlushAddr   __P( /* XXX Really pte highpart ? */
+extern void mips1_ConfigCache  __P((void));
+extern void mips1_FlushCache  __P((void));
+extern void mips1_FlushDCache  __P((vm_offset_t addr, vm_offset_t len));
+extern void mips1_FlushICache  __P((vm_offset_t addr, vm_offset_t len));
+extern void mips1_ForceCacheUpdate __P((void));
+extern void mips1_SetPID   __P((int pid));
+extern void mips1_TLBFlush __P((void));
+extern void mips1_TLBFlushAddr   __P( /* XXX Really pte highpart ? */
 					  (vm_offset_t addr));
-extern void mips_r2000_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
-extern void mips_r2000_TLBWriteIndexed  __P((u_int index, u_int high,
+extern void mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
+extern void mips1_TLBWriteIndexed  __P((u_int index, u_int high,
 					    u_int low));
 
-extern void mips_r4000_ConfigCache __P((void));
-extern void mips_r4000_FlushCache  __P((void));
-extern void mips_r4000_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
-extern void mips_r4000_FlushICache __P((vm_offset_t addr, vm_offset_t len));
-extern void mips_r4000_ForceCacheUpdate __P((void));
-extern void mips_r4000_SetPID  __P((int pid));
-extern void mips_r4000_TLBFlush __P((void));
-extern void mips_r4000_TLBFlushAddr __P( /* XXX Really pte highpart ? */
+extern void mips3_KernIntr __P((void));
+extern void mips3_ConfigCache __P((void));
+extern void mips3_FlushCache  __P((void));
+extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
+extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len));
+extern void mips3_ForceCacheUpdate __P((void));
+extern void mips3_SetPID  __P((int pid));
+extern void mips3_TLBFlush __P((void));
+extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */
 					  (vm_offset_t addr));
-extern void mips_r4000_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
-extern void mips_r4000_TLBWriteIndexed __P((u_int index, u_int high,
+extern void mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
+extern void mips3_TLBWriteIndexed __P((u_int index, u_int high,
 					    u_int low));
 
 /*
diff --git a/sys/arch/pmax/include/machConst.h b/sys/arch/pmax/include/machConst.h
index eda5e7897af..19234930fdd 100644
--- a/sys/arch/pmax/include/machConst.h
+++ b/sys/arch/pmax/include/machConst.h
@@ -1,584 +1,4 @@
-/*	$NetBSD: machConst.h,v 1.5 1996/03/28 11:34:05 jonathan Exp $	*/
+/*	$NetBSD: machConst.h,v 1.6 1996/09/30 07:58:20 jonathan Exp $	*/
 
-/*
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This code is derived from software contributed to Berkeley by
- * Ralph Campbell and Rick Macklem.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	@(#)machConst.h	8.1 (Berkeley) 6/10/93
- *
- * machConst.h --
- *
- *	Machine dependent constants.
- *
- *	Copyright (C) 1989 Digital Equipment Corporation.
- *	Permission to use, copy, modify, and distribute this software and
- *	its documentation for any purpose and without fee is hereby granted,
- *	provided that the above copyright notice appears in all copies.
- *	Digital Equipment Corporation makes no representations about the
- *	suitability of this software for any purpose.  It is provided "as is"
- *	without express or implied warranty.
- *
- * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
- *	v 9.2 89/10/21 15:55:22 jhh Exp  SPRITE (DECWRL)
- * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
- *	v 1.2 89/08/15 18:28:21 rab Exp  SPRITE (DECWRL)
- * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
- *	v 9.1 89/09/18 17:33:00 shirriff Exp  SPRITE (DECWRL)
- */
 
-#ifndef _MACHCONST
-#define _MACHCONST
-
-#define MACH_KUSEG_ADDR			0x0
-#define MACH_CACHED_MEMORY_ADDR		0x80000000
-#define MACH_UNCACHED_MEMORY_ADDR	0xa0000000
-#define MACH_KSEG2_ADDR			0xc0000000
-#define MACH_MAX_MEM_ADDR		0xbe000000
-#define	MACH_RESERVED_ADDR		0xbfc80000
-
-#define	MACH_CACHED_TO_PHYS(x)	((unsigned)(x) & 0x1fffffff)
-#define	MACH_PHYS_TO_CACHED(x)	((unsigned)(x) | MACH_CACHED_MEMORY_ADDR)
-#define	MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
-#define	MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR)
-
-/* Map virtual address to index in r4k virtually-indexed cache */
-#define MIPS_R4K_VA_TO_CINDEX(x) \
-		((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR)
-
-/* XXX compatibility with Pica port */
-#define MACH_VA_TO_CINDEX(x) MIPS_R4K_VA_TO_CINDEX(x)
-
-
-/*
- * XXX
- * Port-specific constants:
- * Kernel virtual address at which kernel is loaded, and
- * Kernel virtual address for user page table entries
- * (i.e., the address for the context register).
- */
-#ifdef pmax
-#define MACH_CODE_START			0x80030000
-#define VMMACH_PTE_BASE			0xFFC00000
-#endif	/* pmax */
-
-#ifdef pica
-#define MACH_CODE_START			0x80080000
-#define VMMACH_PTE_BASE			0xFF800000
-#endif	/* pica */
-
-
-
-/*
- * The bits in the cause register.
- *
- * Bits common to r3000 and r4000:
- *
- *	MACH_CR_BR_DELAY	Exception happened in branch delay slot.
- *	MACH_CR_COP_ERR		Coprocessor error.
- *	MACH_CR_IP		Interrupt pending bits defined below.
- *				(same meaning as in CAUSE register).
- *	MACH_CR_EXC_CODE	The exception type (see exception codes below).
- *
- * Differences:
- *  r3k has 4 bits of execption type, r4k has 5 bits.
- */
-#define MACH_CR_BR_DELAY	0x80000000
-#define MACH_CR_COP_ERR		0x30000000
-#define MIPS_3K_CR_EXC_CODE	0x0000003C
-#define MIPS_4K_CR_EXC_CODE	0x0000007C
-#define MACH_CR_IP		0x0000FF00
-#define MACH_CR_EXC_CODE_SHIFT	2
-
-#ifdef pmax /* XXX not used any more, only to satisfy regression tests */
-#define MACH_CR_EXC_CODE	MIPS_3K_CR_EXC_CODE
-#endif	/* pmax */
-#ifdef pica
-#define MACH_CR_EXC_CODE	MIPS_4K_CR_EXC_CODE
-#endif	/* pica */
-
-
-/*
- * The bits in the status register.  All bits are active when set to 1.
- *
- *	R3000 status register fields:
- *	MACH_SR_CO_USABILITY	Control the usability of the four coprocessors.
- *	MACH_SR_BOOT_EXC_VEC	Use alternate exception vectors.
- *	MACH_SR_TLB_SHUTDOWN	TLB disabled.
- *
- *	MIPS_SR_INT_IE		Master (current) interrupt enable bit.
- *
- * Differences:
- *	r3k has cache control is via frobbing SR register bits, whereas the
- *	r4k cache control is via explicit instructions.
- *	r3k has a 3-entry stack of kernel/user bits, whereas the
- *	r4k has kernel/supervisor/user.
- */
-#define MACH_SR_COP_USABILITY	0xf0000000
-#define MACH_SR_COP_0_BIT	0x10000000
-#define MACH_SR_COP_1_BIT	0x20000000
-
-	/* r4k and r3k differences, see below */
-
-#define MACH_SR_BOOT_EXC_VEC	0x00400000
-#define MACH_SR_TLB_SHUTDOWN	0x00200000
-
-	/* r4k and r3k differences, see below */
-
-#define MIPS_SR_INT_IE		0x00000001
-/*#define MACH_SR_MBZ		0x0f8000c0*/	/* Never used, true for r3k */
-/*#define MACH_SR_INT_MASK	0x0000ff00*/
-
-#define MACH_SR_INT_ENAB	MIPS_SR_INT_IE	/* backwards compatibility */
-#define MACH_SR_INT_ENA_CUR	MIPS_SR_INT_IE	/* backwards compatibility */
-
-
-
-/*
- * The R2000/R3000-specific status register bit definitions.
- * all bits are active when set to 1.
- *
- *	MACH_SR_PARITY_ERR	Parity error.
- *	MACH_SR_CACHE_MISS	Most recent D-cache load resulted in a miss.
- *	MACH_SR_PARITY_ZERO	Zero replaces outgoing parity bits.
- *	MACH_SR_SWAP_CACHES	Swap I-cache and D-cache.
- *	MACH_SR_ISOL_CACHES	Isolate D-cache from main memory.
- *				Interrupt enable bits defined below.
- *	MACH_SR_KU_OLD		Old kernel/user mode bit. 1 => user mode.
- *	MACH_SR_INT_ENA_OLD	Old interrupt enable bit.
- *	MACH_SR_KU_PREV		Previous kernel/user mode bit. 1 => user mode.
- *	MACH_SR_INT_ENA_PREV	Previous interrupt enable bit.
- *	MACH_SR_KU_CUR		Current kernel/user mode bit. 1 => user mode.
- */
-
-#define MIPS_3K_PARITY_ERR      0x00100000
-#define MIPS_3K_CACHE_MISS      0x00080000
-#define MIPS_3K_PARITY_ZERO     0x00040000
-#define MIPS_3K_SWAP_CACHES     0x00020000
-#define MIPS_3K_ISOL_CACHES     0x00010000
-
-#define MIPS_3K_SR_KU_OLD	0x00000020	/* 2nd stacked KU/IE*/
-#define MIPS_3K_SR_INT_ENA_OLD	0x00000010	/* 2nd stacked KU/IE*/
-#define MIPS_3K_SR_KU_PREV	0x00000008	/* 1st stacked KU/IE*/
-#define MIPS_3K_SR_INT_ENA_PREV	0x00000004	/* 1st stacked KU/IE*/
-#define MIPS_3K_SR_KU_CUR	0x00000002	/* current KU */
-
-/* backwards compatibility */
-#define MACH_SR_PARITY_ERR	MIPS_3K_PARITY_ERR
-#define MACH_SR_CACHE_MISS	MIPS_3K_CACHE_MISS
-#define MACH_SR_PARITY_ZERO	MIPS_3K_PARITY_ZERO
-#define MACH_SR_SWAP_CACHES	MIPS_3K_SWAP_CACHES
-#define MACH_SR_ISOL_CACHES	MIPS_3K_ISOL_CACHES
-
-#define MACH_SR_KU_OLD		MIPS_3K_SR_KU_OLD
-#define MACH_SR_INT_ENA_OLD	MIPS_3K_SR_INT_ENA_OLD
-#define MACH_SR_KU_PREV		MIPS_3K_SR_KU_PREV
-#define MACH_SR_KU_CUR		MIPS_3K_SR_KU_CUR
-#define MACH_SR_INT_ENA_PREV	MIPS_3K_SR_INT_ENA_PREV
-
-
-/*
- * R4000 status register bit definitons,
- * where different from r2000/r3000.
- */
-#define MIPS_4K_SR_RP   	0x08000000
-#define MIPS_4K_SR_FR_32	0x04000000
-#define MIPS_4K_SR_RE   	0x02000000
-
-#define MIPS_4K_SR_SOFT_RESET	0x00100000
-#define MIPS_4K_SR_DIAG_CH	0x00040000
-#define MIPS_4K_SR_DIAG_CE	0x00020000
-#define MIPS_4K_SR_DIAG_PE	0x00010000
-#define MIPS_4K_SR_KX		0x00000080
-#define MIPS_4K_SR_SX		0x00000040
-#define MIPS_4K_SR_UX		0x00000020
-#define MIPS_4K_SR_KSU_MASK	0x00000018
-#define MIPS_4K_SR_KSU_USER	0x00000010
-#define MIPS_4K_SR_KSU_SUPER	0x00000008
-#define MIPS_4K_SR_KSU_KERNEL	0x00000000
-#define MIPS_4K_SR_ERL		0x00000004
-#define MIPS_4K_SR_EXL		0x00000002
-
-/* backwards compatibility with names used in Pica port */
-#define MACH_SR_RP		MIPS_4K_SR_RP   
-#define MACH_SR_FR_32		MIPS_4K_SR_FR_32
-#define MACH_SR_RE		MIPS_4K_SR_RE   
-
-#define MACH_SR_SOFT_RESET	MIPS_4K_SR_SOFT_RESET
-#define MACH_SR_DIAG_CH		MIPS_4K_SR_DIAG_CH
-#define MACH_SR_DIAG_CE		MIPS_4K_SR_DIAG_CE
-#define MACH_SR_DIAG_PE		MIPS_4K_SR_DIAG_PE
-#define MACH_SR_KX		MIPS_4K_SR_KX
-#define MACH_SR_SX		MIPS_4K_SR_SX
-#define MACH_SR_UX		MIPS_4K_SR_UX
-
-#define MACH_SR_KSU_MASK	MIPS_4K_SR_KSU_MASK
-#define MACH_SR_KSU_USER	MIPS_4K_SR_KSU_USER
-#define MACH_SR_KSU_SUPER	MIPS_4K_SR_KSU_SUPER
-#define MACH_SR_KSU_KERNEL	MIPS_4K_SR_KSU_KERNEL
-#define MACH_SR_ERL		MIPS_4K_SR_ERL
-#define MACH_SR_EXL		MIPS_4K_SR_EXL
-
-
-/*
- * The interrupt masks.
- * If a bit in the mask is 1 then the interrupt is enabled (or pending).
- */
-#define MIPS_INT_MASK		0xff00
-#define MACH_INT_MASK_5		0x8000
-#define MACH_INT_MASK_4		0x4000
-#define MACH_INT_MASK_3		0x2000
-#define MACH_INT_MASK_2		0x1000
-#define MACH_INT_MASK_1		0x0800
-#define MACH_INT_MASK_0		0x0400
-#define MIPS_HARD_INT_MASK	0xfc00
-#define MACH_SOFT_INT_MASK_1	0x0200
-#define MACH_SOFT_INT_MASK_0	0x0100
-
-#ifdef pmax
-#define MACH_INT_MASK		MIPS_INT_MASK
-#define MACH_HARD_INT_MASK	MIPS_HARD_INT_MASK
-#endif
-
-/* r4000 has on-chip timer at INT_MASK_5 */
-#ifdef pica
-#define MACH_INT_MASK		(MIPS_INT_MASK &  ~MACH_INT_MASK_5)
-#define MACH_HARD_INT_MASK	(MIPS_HARD_INT_MASK & ~MACH_INT_MASK_5)
-#endif
-
-
-
-/*
- * The bits in the context register.
- */
-#define MIPS_3K_CNTXT_PTE_BASE  0xFFE00000
-#define MIPS_3K_CNTXT_BAD_VPN   0x001FFFFC
-
-#define MIPS_4K_CNTXT_PTE_BASE	0xFF800000
-#define MIPS_4K_CNTXT_BAD_VPN2	0x007FFFF0
-
-/*
- * Backwards compatbility -- XXX more thought
- */
-#ifdef pmax
-#define MACH_CNTXT_PTE_BASE	MIPS_3K_CNTXT_PTE_BASE
-#define MACH_CNTXT_BAD_VPN	MIPS_3K_CNTXT_BAD_VPN
-#endif	/* pmax */
-
-#ifdef pica
-#define MACH_CNTXT_PTE_BASE	MIPS_4K_CNTXT_PTE_BASE
-#define MACH_CNTXT_BAD_VPN2	MIPS_4K_CNTXT_BAD_VPN2
-#endif	/* pica */
-
-
-
-/*
- * Location of exception vectors.
- *
- * Common vectors:  reset and UTLB miss.
- */
-#define MACH_RESET_EXC_VEC	0xBFC00000
-#define MACH_UTLB_MISS_EXC_VEC	0x80000000
-
-/*
- * R3000 general exception vector (everything else)
- */
-#define MIPS_3K_GEN_EXC_VEC	0x80000080
-
-/*
- * R4000 MIPS-III exception vectors
- */
-#define MIPS_4K_XTLB_MISS_EXC_VEC	0x80000080
-#define MIPS_4K_CACHE_ERR_EXC_VEC	0x80000100
-#define MIPS_4K_GEN_EXC_VEC		0x80000180
-
-/*
- * Backwards compatbility -- XXX more thought
- */
-#ifdef pmax
-#define MACH_GEN_EXC_VEC	MIPS_3K_GEN_EXC_VEC
-#endif	/* pmax */
-
-#ifdef pica
-#define MACH_GEN_EXC_VEC	MIPS_4K_GEN_EXC_VEC
-#define MACH_TLB_MISS_EXC_VEC	MACH_UTLB_MISS_EXC_VEC	/* locore compat */
-#define MACH_XTLB_MISS_EXC_VEC	MIPS_4K_XTLB_MISS_EXC_VEC
-#define MACH_CACHE_ERR_EXC_VEC	MIPS_4K_CACHE_ERR_EXC_VEC
-#endif	/* pica */
-
-
-
-/*
- * Coprocessor 0 registers:
- *
- *	MACH_COP_0_TLB_INDEX	TLB index.
- *	MACH_COP_0_TLB_RANDOM	TLB random.
- *	MACH_COP_0_TLB_LOW	r3k TLB entry low.
- *	MACH_COP_0_TLB_LO0	r4k TLB entry low.
- *	MACH_COP_0_TLB_LO1	r4k TLB entry low, extended.
- *	MACH_COP_0_TLB_CONTEXT	TLB context.
- *	MACH_COP_0_BAD_VADDR	Bad virtual address.
- *	MACH_COP_0_TLB_HI	TLB entry high.
- *	MACH_COP_0_STATUS_REG	Status register.
- *	MACH_COP_0_CAUSE_REG	Exception cause register.
- *	MACH_COP_0_EXC_PC	Exception PC.
- *	MACH_COP_0_PRID		Processor revision identifier.
- */
-#define MACH_COP_0_TLB_INDEX	$0
-#define MACH_COP_0_TLB_RANDOM	$1
-	/* Name and meaning of  TLB bits for $2 differ on r3k and r4k. */
-
-#define MACH_COP_0_TLB_CONTEXT	$4
-					/* $5 and $6 new with MIPS-III */
-#define MACH_COP_0_BAD_VADDR	$8
-#define MACH_COP_0_TLB_HI	$10
-#define MACH_COP_0_STATUS_REG	$12
-#define MACH_COP_0_CAUSE_REG	$13
-#define MACH_COP_0_EXC_PC	$14
-#define MACH_COP_0_PRID		$15
-
-
-/* r3k-specific */
-#define MACH_COP_0_TLB_LOW	$2
-
-/* MIPS-III additions */
-#define MACH_COP_0_TLB_LO0	$2
-#define MACH_COP_0_TLB_LO1	$3
-
-#define MACH_COP_0_TLB_PG_MASK	$5
-#define MACH_COP_0_TLB_WIRED	$6
-
-#define MACH_COP_0_CONFIG	$16
-#define MACH_COP_0_LLADDR	$17
-#define MACH_COP_0_WATCH_LO	$18
-#define MACH_COP_0_WATCH_HI	$19
-#define MACH_COP_0_TLB_XCONTEXT	$20
-#define MACH_COP_0_ECC		$26
-#define MACH_COP_0_CACHE_ERR	$27
-#define MACH_COP_0_TAG_LO	$28
-#define MACH_COP_0_TAG_HI	$29
-#define MACH_COP_0_ERROR_PC	$30
-
-
-
-/*
- * Values for the code field in a break instruction.
- */
-#define MACH_BREAK_INSTR	0x0000000d
-#define MACH_BREAK_VAL_MASK	0x03ff0000
-#define MACH_BREAK_VAL_SHIFT	16
-#define MACH_BREAK_KDB_VAL	512
-#define MACH_BREAK_SSTEP_VAL	513
-#define MACH_BREAK_BRKPT_VAL	514
-#define MACH_BREAK_SOVER_VAL	515
-#define MACH_BREAK_KDB		(MACH_BREAK_INSTR | \
-				(MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT))
-#define MACH_BREAK_SSTEP	(MACH_BREAK_INSTR | \
-				(MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT))
-#define MACH_BREAK_BRKPT	(MACH_BREAK_INSTR | \
-				(MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT))
-#define MACH_BREAK_SOVER	(MACH_BREAK_INSTR | \
-				(MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT))
-
-/*
- * Mininum and maximum cache sizes.
- */
-#define MACH_MIN_CACHE_SIZE	(16 * 1024)
-#define MACH_MAX_CACHE_SIZE	(256 * 1024)
-
-/*
- * The floating point version and status registers.
- */
-#define	MACH_FPC_ID	$0
-#define	MACH_FPC_CSR	$31
-
-/*
- * The floating point coprocessor status register bits.
- */
-#define MACH_FPC_ROUNDING_BITS		0x00000003
-#define MACH_FPC_ROUND_RN		0x00000000
-#define MACH_FPC_ROUND_RZ		0x00000001
-#define MACH_FPC_ROUND_RP		0x00000002
-#define MACH_FPC_ROUND_RM		0x00000003
-#define MACH_FPC_STICKY_BITS		0x0000007c
-#define MACH_FPC_STICKY_INEXACT		0x00000004
-#define MACH_FPC_STICKY_UNDERFLOW	0x00000008
-#define MACH_FPC_STICKY_OVERFLOW	0x00000010
-#define MACH_FPC_STICKY_DIV0		0x00000020
-#define MACH_FPC_STICKY_INVALID		0x00000040
-#define MACH_FPC_ENABLE_BITS		0x00000f80
-#define MACH_FPC_ENABLE_INEXACT		0x00000080
-#define MACH_FPC_ENABLE_UNDERFLOW	0x00000100
-#define MACH_FPC_ENABLE_OVERFLOW	0x00000200
-#define MACH_FPC_ENABLE_DIV0		0x00000400
-#define MACH_FPC_ENABLE_INVALID		0x00000800
-#define MACH_FPC_EXCEPTION_BITS		0x0003f000
-#define MACH_FPC_EXCEPTION_INEXACT	0x00001000
-#define MACH_FPC_EXCEPTION_UNDERFLOW	0x00002000
-#define MACH_FPC_EXCEPTION_OVERFLOW	0x00004000
-#define MACH_FPC_EXCEPTION_DIV0		0x00008000
-#define MACH_FPC_EXCEPTION_INVALID	0x00010000
-#define MACH_FPC_EXCEPTION_UNIMPL	0x00020000
-#define MACH_FPC_COND_BIT		0x00800000
-#define MACH_FPC_FLUSH_BIT		0x01000000	/* r4k,  MBZ on r3k */
-#define MIPS_3K_FPC_MBZ_BITS		0xff7c0000
-#define MIPS_4K_FPC_MBZ_BITS		0xfe7c0000
-
-
-/*
- * Constants to determine if have a floating point instruction.
- */
-#define MACH_OPCODE_SHIFT	26
-#define MACH_OPCODE_C1		0x11
-
-
-
-/*
- * The low part of the TLB entry.
- */
-#define VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT	12
-#define VMMACH_MIPS_3K_TLB_PF_NUM		0xfffff000
-#define VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT	0x00000800
-#define VMMACH_MIPS_3K_TLB_MOD_BIT		0x00000400
-#define VMMACH_MIPS_3K_TLB_VALID_BIT		0x00000200
-#define VMMACH_MIPS_3K_TLB_GLOBAL_BIT		0x00000100
-
-#define VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT	6
-#define VMMACH_MIPS_4K_TLB_PF_NUM		0x3fffffc0
-#define VMMACH_MIPS_4K_TLB_ATTR_MASK		0x00000038
-#define VMMACH_MIPS_4K_TLB_MOD_BIT		0x00000004
-#define VMMACH_MIPS_4K_TLB_VALID_BIT		0x00000002
-#define VMMACH_MIPS_4K_TLB_GLOBAL_BIT		0x00000001
-
-
-#ifdef pmax /* XXX */
-#define VMMACH_TLB_PHYS_PAGE_SHIFT	VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT
-#define VMMACH_TLB_PF_NUM		VMMACH_MIPS_3K_TLB_PF_NUM
-#define VMMACH_TLB_NON_CACHEABLE_BIT	VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT
-#define VMMACH_TLB_MOD_BIT		VMMACH_MIPS_3K_TLB_MOD_BIT
-#define VMMACH_TLB_VALID_BIT		VMMACH_MIPS_3K_TLB_VALID_BIT
-#define VMMACH_TLB_GLOBAL_BIT		VMMACH_MIPS_3K_TLB_GLOBAL_BIT
-#endif /* pmax */
-
-#ifdef pica /*  XXX */
-#define VMMACH_TLB_PHYS_PAGE_SHIFT	VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT
-#define VMMACH_TLB_PF_NUM		VMMACH_MIPS_4K_TLB_PF_NUM
-#define VMMACH_TLB_ATTR_MASK		VMMACH_MIPS_4K_TLB_ATTR_MASK
-#define VMMACH_TLB_MOD_BIT		VMMACH_MIPS_4K_TLB_MOD_BIT
-#define VMMACH_TLB_VALID_BIT		VMMACH_MIPS_4K_TLB_VALID_BIT
-#define VMMACH_TLB_GLOBAL_BIT		VMMACH_MIPS_4K_TLB_GLOBAL_BIT
-#endif	/* pica */
-
-
-
-/*
- * The high part of the TLB entry.
- */
-#define VMMACH_TLB_VIRT_PAGE_SHIFT		12
-
-#define VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM	0xfffff000
-#define VMMACH_TLB_MIPS_3K_PID			0x00000fc0
-#define VMMACH_TLB_MIPS_3K_PID_SHIFT		6
-
-#define VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM	0xffffe000
-#define VMMACH_TLB_MIPS_4K_PID			0x000000ff
-#define VMMACH_TLB_MIPS_4K_PID_SHIFT		0
-
-/* XXX needs more thought */
-/*
- * backwards XXX needs more thought, should support runtime decisions.
- */
-
-#ifdef pmax
-#define VMMACH_TLB_VIRT_PAGE_NUM	VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM
-#define VMMACH_TLB_PID			VMMACH_TLB_MIPS_3K_PID      
-#define VMMACH_TLB_PID_SHIFT		VMMACH_TLB_MIPS_3K_PID_SHIFT
-#endif
-
-#ifdef pica
-#define VMMACH_TLB_VIRT_PAGE_NUM	VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM
-#define VMMACH_TLB_PID			VMMACH_TLB_MIPS_4K_PID      
-#define VMMACH_TLB_PID_SHIFT		VMMACH_TLB_MIPS_4K_PID_SHIFT
-#endif
-
-/*
- * r3000: shift count to put the index in the right spot.
- * (zero on r4000?) 
- */
-#define VMMACH_TLB_INDEX_SHIFT		8
-
-
-/*
- * The number of TLB entries and the first one that write random hits.
- */
-#define VMMACH_MIPS_3K_NUM_TLB_ENTRIES	64
-#define VMMACH_MIPS_3K_FIRST_RAND_ENTRY	8
-
-#define VMMACH_MIPS_4K_NUM_TLB_ENTRIES	48
-#define VMMACH_MIPS_4K_WIRED_ENTRIES	8
-
-/* compatibility with existing locore -- XXX more thought */
-#ifdef pmax
-#define VMMACH_NUM_TLB_ENTRIES		VMMACH_MIPS_3K_NUM_TLB_ENTRIES
-#define VMMACH_FIRST_RAND_ENTRY 	VMMACH_MIPS_3K_FIRST_RAND_ENTRY
-#endif	/* pmax */
-
-#ifdef pica
-#define VMMACH_NUM_TLB_ENTRIES		VMMACH_MIPS_4K_NUM_TLB_ENTRIES
-#define VMMACH_WIRED_ENTRIES	 	VMMACH_MIPS_4K_WIRED_ENTRIES
-#endif	/* pica */
-
-
-/*
- * The number of process id entries.
- */
-#define	VMMACH_MIPS_3K_NUM_PIDS			64
-#define	VMMACH_MIPS_4K_NUM_PIDS			256
-
-#ifdef pmax
-#define	VMMACH_NUM_PIDS		VMMACH_MIPS_3K_NUM_PIDS
-#endif	/* pmax */
-#ifdef pica
-#define	VMMACH_NUM_PIDS		VMMACH_MIPS_4K_NUM_PIDS
-#endif	/* pica */
-
-
-/*
- * TLB probe return codes.
- */
-#define VMMACH_TLB_NOT_FOUND		0
-#define VMMACH_TLB_FOUND		1
-#define VMMACH_TLB_FOUND_WITH_PATCH	2
-#define VMMACH_TLB_PROBE_ERROR		3
-
-#endif /* _MACHCONST */
+#include <pmax/cpuregs.h>
diff --git a/sys/arch/pmax/include/mips1_pte.h b/sys/arch/pmax/include/mips1_pte.h
new file mode 100644
index 00000000000..220d93fa9f9
--- /dev/null
+++ b/sys/arch/pmax/include/mips1_pte.h
@@ -0,0 +1,97 @@
+/*	$NetBSD: mips1_pte.h,v 1.8 1996/10/13 09:54:43 jonathan Exp $	*/
+
+/*
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: pte.h 1.11 89/09/03
+ *
+ *	@(#)pte.h	8.1 (Berkeley) 6/10/93
+ */
+
+/*
+ * R2000 hardware page table entry
+ */
+
+#ifndef _LOCORE
+struct pte {
+#if BYTE_ORDER == BIG_ENDIAN
+unsigned int	pg_pfnum:20,		/* HW: core page frame number or 0 */
+		pg_n:1,			/* HW: non-cacheable bit */
+		pg_m:1,			/* HW: modified (dirty) bit */
+		pg_v:1,			/* HW: valid bit */
+		pg_g:1,			/* HW: ignore pid bit */
+		:4,
+		pg_swapm:1,		/* SW: page must be forced to swap */
+		pg_fod:1,		/* SW: is fill on demand (=0) */
+		pg_prot:2;		/* SW: access control */
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+unsigned int	pg_prot:2,		/* SW: access control */
+		pg_fod:1,		/* SW: is fill on demand (=0) */
+		pg_swapm:1,		/* SW: page must be forced to swap */
+		:4,
+		pg_g:1,			/* HW: ignore pid bit */
+		pg_v:1,			/* HW: valid bit */
+		pg_m:1,			/* HW: modified (dirty) bit */
+		pg_n:1,			/* HW: non-cacheable bit */
+		pg_pfnum:20;		/* HW: core page frame number or 0 */
+#endif
+};
+
+typedef union pt_entry {
+	unsigned int	pt_entry;	/* for copying, etc. */
+	struct pte	pt_pte;		/* for getting to bits by name */
+} pt_entry_t;	/* Mach page table entry */
+#endif /* _LOCORE */
+
+#define	PT_ENTRY_NULL	((pt_entry_t *) 0)
+
+#define	PG_PROT		0x00000003
+#define PG_RW		0x00000000
+#define PG_RO		0x00000001
+#define PG_WIRED	0x00000002
+#define	PG_G		0x00000100
+#define	PG_V		0x00000200
+#define	PG_NV		0x00000000
+#define	PG_M		0x00000400
+#define	PG_N		0x00000800
+#define	PG_FRAME	0xfffff000
+#define PG_SHIFT	12
+#define	PG_PFNUM(x)	(((x) & PG_FRAME) >> PG_SHIFT)
+
+#define PTE_TO_PADDR(pte) ((unsigned)(pte) & PG_FRAME)
+#define PAGE_IS_RDONLY(pte,va) ((pte) & PG_RO)
diff --git a/sys/arch/pmax/include/mips3_pte.h b/sys/arch/pmax/include/mips3_pte.h
new file mode 100644
index 00000000000..fc798eb93b4
--- /dev/null
+++ b/sys/arch/pmax/include/mips3_pte.h
@@ -0,0 +1,132 @@
+/*	$NetBSD: mips3_pte.h,v 1.5 1996/10/13 09:54:44 jonathan Exp $	*/
+
+/*
+ * Copyright (c) 1988 University of Utah.
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * the Systems Programming Group of the University of Utah Computer
+ * Science Department and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * from: Utah Hdr: pte.h 1.11 89/09/03
+ *
+ *	from: @(#)pte.h	8.1 (Berkeley) 6/10/93
+ */
+
+/*
+ * R4000 hardware page table entry
+ */
+
+#ifndef _LOCORE
+struct pte {
+#if BYTE_ORDER == BIG_ENDIAN
+unsigned int	pg_prot:2,		/* SW: access control */
+		pg_pfnum:24,		/* HW: core page frame number or 0 */
+		pg_attr:3,		/* HW: cache attribute */
+		pg_m:1,			/* HW: modified (dirty) bit */
+		pg_v:1,			/* HW: valid bit */
+		pg_g:1;			/* HW: ignore pid bit */
+#endif
+#if BYTE_ORDER == LITTLE_ENDIAN
+unsigned int 	pg_g:1,			/* HW: ignore pid bit */
+		pg_v:1,			/* HW: valid bit */
+		pg_m:1,			/* HW: modified (dirty) bit */
+		pg_attr:3,			/* HW: cache attribute */
+		pg_pfnum:24,		/* HW: core page frame number or 0 */
+		pg_prot:2;		/* SW: access control */
+#endif
+};
+
+/*
+ * Structure defining an tlb entry data set.
+ */
+
+struct tlb {
+	int	tlb_mask;
+	int	tlb_hi;
+	int	tlb_lo0;
+	int	tlb_lo1;
+};
+
+typedef union pt_entry {
+	unsigned int	pt_entry;	/* for copying, etc. */
+	struct pte	pt_pte;		/* for getting to bits by name */
+} pt_entry_t;	/* Mach page table entry */
+#endif /* _LOCORE */
+
+#define	PT_ENTRY_NULL	((pt_entry_t *) 0)
+
+#define PG_WIRED	0x80000000	/* SW */
+#define PG_RO		0x40000000	/* SW */
+
+#define	PG_SVPN		0xfffff000	/* Software page no mask */
+#define	PG_HVPN		0xffffe000	/* Hardware page no mask */
+#define	PG_ODDPG	0x00001000	/* Odd even pte entry */
+#define	PG_ASID		0x000000ff	/* Address space ID */
+#define	PG_G		0x00000001	/* HW */
+#define	PG_V		0x00000002
+#define	PG_NV		0x00000000
+#define	PG_M		0x00000004
+#define	PG_ATTR		0x0000003f
+#define	PG_UNCACHED	0x00000010
+#define	PG_CACHED	0x00000018
+#define	PG_CACHEMODE	0x00000038
+#define	PG_ROPAGE	(PG_V | PG_RO | PG_CACHED) /* Write protected */
+#define	PG_RWPAGE	(PG_V | PG_M | PG_CACHED)  /* Not wr-prot not clean */
+#define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not wr-prot but clean */
+#define	PG_IOPAGE	(PG_G | PG_V | PG_M | PG_UNCACHED)
+#define	PG_FRAME	0x3fffffc0
+#define PG_SHIFT	6
+
+/* pte accessor macros */
+
+#define vad_to_pfn(x) (((unsigned)(x) >> PG_SHIFT) & PG_FRAME)
+#define pfn_to_vad(x) (((x) & PG_FRAME) << PG_SHIFT)
+#define vad_to_vpn(x) ((unsigned)(x) & PG_SVPN)
+#define vpn_to_vad(x) ((x) & PG_SVPN)
+
+#define PTE_TO_PADDR(pte) (pfn_to_vad(pte))
+#define PAGE_IS_RDONLY(pte,va) \
+    (pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte)))
+
+
+/* User virtual to pte page entry */
+#define uvtopte(adr) (((adr) >> PGSHIFT) & (NPTEPG -1))
+
+#define	PG_SIZE_4K	0x00000000
+#define	PG_SIZE_16K	0x00006000
+#define	PG_SIZE_64K	0x0001e000
+#define	PG_SIZE_256K	0x0007e000
+#define	PG_SIZE_1M	0x001fe000
+#define	PG_SIZE_4M	0x007fe000
+#define	PG_SIZE_16M	0x01ffe000
+
diff --git a/sys/arch/pmax/include/param.h b/sys/arch/pmax/include/param.h
index e677902b4b2..33eb0c3dc82 100644
--- a/sys/arch/pmax/include/param.h
+++ b/sys/arch/pmax/include/param.h
@@ -88,8 +88,8 @@
  * of the hardware page size.
  */
 #define	MSIZE		128		/* size of an mbuf */
-#define	MCLSHIFT	11
-#define	MCLBYTES	(1 << MCLSHIFT)	/* enough for whole Ethernet packet */
+#define	MCLBYTES	2048		/* enough for whole Ethernet packet */
+#define	MCLSHIFT	10
 #define	MCLOFSET	(MCLBYTES - 1)
 #ifndef NMBCLUSTERS
 #ifdef GATEWAY
diff --git a/sys/arch/pmax/include/pmap.h b/sys/arch/pmax/include/pmap.h
index 4c5b9ca5b7e..fb948a7ed87 100644
--- a/sys/arch/pmax/include/pmap.h
+++ b/sys/arch/pmax/include/pmap.h
@@ -102,6 +102,9 @@ struct pmap kernel_pmap_store;
 #define pmap_kernel()		(&kernel_pmap_store)
 #endif	/* _KERNEL */
 
-#endif	/* _PMAP_MACHINE_ */
+/* Stuff from the NetBSD mips tree TTTTT */
 #define pmax_trunc_seg(a) mips_trunc_seg(a)
 #define pmax_round_seg(a) mips_round_seg(a)
+/* End of stuff from the NetBSD mips tree TTTTT */
+
+#endif	/* _PMAP_MACHINE_ */
diff --git a/sys/arch/pmax/include/pte.h b/sys/arch/pmax/include/pte.h
index 599f0265a8c..70dd4be56bf 100644
--- a/sys/arch/pmax/include/pte.h
+++ b/sys/arch/pmax/include/pte.h
@@ -1,97 +1,34 @@
-/*	$NetBSD: pte.h,v 1.6 1996/02/01 22:32:15 mycroft Exp $	*/
+/*	$NetBSD: pte.h,v 1.1 1996/10/13 09:28:56 jonathan Exp $	*/
 
 /*
- * Copyright (c) 1988 University of Utah.
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
+ * Copyright 1996 The Board of Trustees of The Leland Stanford
+ * Junior University. All Rights Reserved.
  *
- * This code is derived from software contributed to Berkeley by
- * the Systems Programming Group of the University of Utah Computer
- * Science Department and Ralph Campbell.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * from: Utah Hdr: pte.h 1.11 89/09/03
- *
- *	@(#)pte.h	8.1 (Berkeley) 6/10/93
+ * Permission to use, copy, modify, and distribute this
+ * software and its documentation for any purpose and without
+ * fee is hereby granted, provided that the above copyright
+ * notice appear in all copies.  Stanford University
+ * makes no representations about the suitability of this
+ * software for any purpose.  It is provided "as is" without
+ * express or implied warranty.
  */
 
-/*
- * R2000 hardware page table entry
- */
+#ifndef  __MIPS_PTE_H__
+#define  __MIPS_PTE_H__
 
-#ifndef _LOCORE
-struct pte {
-#if BYTE_ORDER == BIG_ENDIAN
-unsigned int	pg_pfnum:20,		/* HW: core page frame number or 0 */
-		pg_n:1,			/* HW: non-cacheable bit */
-		pg_m:1,			/* HW: modified (dirty) bit */
-		pg_v:1,			/* HW: valid bit */
-		pg_g:1,			/* HW: ignore pid bit */
-		:4,
-		pg_swapm:1,		/* SW: page must be forced to swap */
-		pg_fod:1,		/* SW: is fill on demand (=0) */
-		pg_prot:2;		/* SW: access control */
-#endif
-#if BYTE_ORDER == LITTLE_ENDIAN
-unsigned int	pg_prot:2,		/* SW: access control */
-		pg_fod:1,		/* SW: is fill on demand (=0) */
-		pg_swapm:1,		/* SW: page must be forced to swap */
-		:4,
-		pg_g:1,			/* HW: ignore pid bit */
-		pg_v:1,			/* HW: valid bit */
-		pg_m:1,			/* HW: modified (dirty) bit */
-		pg_n:1,			/* HW: non-cacheable bit */
-		pg_pfnum:20;		/* HW: core page frame number or 0 */
+
+#if defined(MIPS1) && defined(MIPS3)
+#error  Cannot yet upport both  "MIPS1" (r2000 family) and "MIP3" (r4000 family) in the same kernel.
 #endif
-};
 
-typedef union pt_entry {
-	unsigned int	pt_entry;	/* for copying, etc. */
-	struct pte	pt_pte;		/* for getting to bits by name */
-} pt_entry_t;	/* Mach page table entry */
-#endif /* _LOCORE */
+#ifdef MIPS1
+#include <pmax/mips1_pte.h>
+#endif
 
-#define	PT_ENTRY_NULL	((pt_entry_t *) 0)
+#ifdef MIPS3
+#include <pmax/mips3_pte.h>
+#endif
 
-#define	PG_PROT		0x00000003
-#define PG_RW		0x00000000
-#define PG_RO		0x00000001
-#define PG_WIRED	0x00000002
-#define	PG_G		0x00000100
-#define	PG_V		0x00000200
-#define	PG_NV		0x00000000
-#define	PG_M		0x00000400
-#define	PG_N		0x00000800
-#define	PG_FRAME	0xfffff000
-#define PG_SHIFT	12
-#define	PG_PFNUM(x)	(((x) & PG_FRAME) >> PG_SHIFT)
 
 #if defined(_KERNEL) && !defined(_LOCORE)
 /*
@@ -104,4 +41,6 @@ typedef union pt_entry {
 
 extern	pt_entry_t *Sysmap;		/* kernel pte table */
 extern	u_int Sysmapsize;		/* number of pte's in Sysmap */
-#endif
+#endif	/* defined(_KERNEL) && !defined(_LOCORE) */
+
+#endif /* __MIPS_PTE_H__ */
diff --git a/sys/arch/pmax/include/reloc.h b/sys/arch/pmax/include/reloc.h
index 1a91b52c46b..5a3eaaa5e49 100644
--- a/sys/arch/pmax/include/reloc.h
+++ b/sys/arch/pmax/include/reloc.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: reloc.h,v 1.5 1996/03/19 22:18:45 jonathan Exp $	*/
+/*	$NetBSD: reloc.h,v 1.6 1996/10/07 03:15:03 jonathan Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -37,6 +37,8 @@
  * from: Header: reloc.h,v 1.6 92/06/20 09:59:37 torek Exp
  */
 
+#ifndef __MIPS_RELOC_H__
+#define __MIPS_RELOC_H__
 /*
  * MIPS relocation types.
  */
@@ -71,5 +73,8 @@ struct reloc_info_mips {
 	long	r_addend;	/* value to add to symbol value */
 };
 
-#define relocation_info reloc_info_mips
+/* For the pmax we only use the next line TTTTT  */
+/* #define relocation_info reloc_info_mips       */
+
 #define relocation_info_pmax reloc_info_mips
+#endif /* __MIPS_RELOC_H__ */
diff --git a/sys/arch/pmax/include/tc_machdep.h b/sys/arch/pmax/include/tc_machdep.h
index 1d41e5d8e03..a8770f29341 100644
--- a/sys/arch/pmax/include/tc_machdep.h
+++ b/sys/arch/pmax/include/tc_machdep.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: tc_machdep.h,v 1.3.4.1 1996/05/30 04:07:39 mhitch Exp $	*/
+/*	$NetBSD: tc_machdep.h,v 1.5 1996/10/06 06:29:51 jonathan Exp $	*/
 
 /*
  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
@@ -105,7 +105,7 @@ int tc_checkslot __P((tc_addr_t slotbase, char *namep));
 
 extern int tc_findconsole __P((int preferred_slot));
 extern void config_tcbus __P((struct device *parent, int cputype,
-			      int printfn __P((void*, char*)) ));
+			      int printfn __P((void*, const char*)) ));
 
 
 #endif /* __MACHINE_TC_MACHDEP_H__*/
diff --git a/sys/arch/pmax/include/vmparam.h b/sys/arch/pmax/include/vmparam.h
index 6215614fcf1..1e7cc3c2dd3 100644
--- a/sys/arch/pmax/include/vmparam.h
+++ b/sys/arch/pmax/include/vmparam.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.5 1994/10/26 21:10:10 cgd Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.6 1996/10/16 06:10:41 jonathan Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -68,13 +68,13 @@
 #define	DFLDSIZ		(32*1024*1024)		/* initial data size limit */
 #endif
 #ifndef MAXDSIZ
-#define	MAXDSIZ		(32*1024*1024)		/* max data size */
+#define	MAXDSIZ		(256*1024*1024)		/* max data size */
 #endif
 #ifndef	DFLSSIZ
 #define	DFLSSIZ		(1024*1024)		/* initial stack size limit */
 #endif
 #ifndef	MAXSSIZ
-#define	MAXSSIZ		MAXDSIZ			/* max stack size */
+#define	MAXSSIZ		(32*1024*1024)		/* max stack size */
 #endif
 
 /*