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authorMark Kettenis <kettenis@cvs.openbsd.org>2024-01-23 19:51:11 +0000
committerMark Kettenis <kettenis@cvs.openbsd.org>2024-01-23 19:51:11 +0000
commit323337ff90f076c3c2e3a5c9c648c395bc5cef19 (patch)
tree6844cf1eb2fb314999ac2e968ba48500ee7f49e2 /sys/arch/riscv64/include
parent80db97c71660e7395f4a8f5a9d5ff79293bbe955 (diff)
T-Head implemented a page attribute extension that violates the RISC-V
specification. The default attributes result in memory being uncached which makes the system perform like a slug. So implement a workaround that is designed to make implementation of the Svpbmt extension that is part of the latest published RISC-V specification. This gets us a bit further booting OpenBSD on an Allwinner D1 SoC. ok mlarkin@, jca@
Diffstat (limited to 'sys/arch/riscv64/include')
-rw-r--r--sys/arch/riscv64/include/pmap.h5
-rw-r--r--sys/arch/riscv64/include/pte.h10
2 files changed, 9 insertions, 6 deletions
diff --git a/sys/arch/riscv64/include/pmap.h b/sys/arch/riscv64/include/pmap.h
index 1f52a260ee5..1d5f3f31c6d 100644
--- a/sys/arch/riscv64/include/pmap.h
+++ b/sys/arch/riscv64/include/pmap.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pmap.h,v 1.10 2023/12/13 18:26:41 jca Exp $ */
+/* $OpenBSD: pmap.h,v 1.11 2024/01/23 19:51:10 kettenis Exp $ */
/*
* Copyright (c) 2019-2020 Brian Bamsch <bbamsch@google.com>
@@ -44,8 +44,7 @@
/* cache flags */
// XXX These are duplicated from arm64 and may need some reworking
#define PMAP_CACHE_CI (PMAP_MD0) /* cache inhibit */
-#define PMAP_CACHE_WT (PMAP_MD1) /* writethru */
-#define PMAP_CACHE_WB (PMAP_MD1|PMAP_MD0) /* writeback */
+#define PMAP_CACHE_WB (PMAP_MD1) /* writeback */
#define PMAP_CACHE_DEV (PMAP_MD2) /* device mapping */
#define PMAP_CACHE_BITS (PMAP_MD0|PMAP_MD1|PMAP_MD2)
diff --git a/sys/arch/riscv64/include/pte.h b/sys/arch/riscv64/include/pte.h
index 2dc05790b72..658ec7b18d7 100644
--- a/sys/arch/riscv64/include/pte.h
+++ b/sys/arch/riscv64/include/pte.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pte.h,v 1.2 2021/05/12 01:20:52 jsg Exp $ */
+/* $OpenBSD: pte.h,v 1.3 2024/01/23 19:51:10 kettenis Exp $ */
/*
* Copyright (c) 2019 Brian Bamsch <bbamsch@google.com>
@@ -39,8 +39,12 @@
#define PTE_RWX (PTE_R | PTE_W | PTE_X)
#define PTE_RX (PTE_R | PTE_X)
#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D)
-#define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_A | PTE_G | PTE_U | \
- PTE_SW_MANAGED | PTE_SW_WIRED
+
+/* T-Head extended page attributes */
+#define PTE_THEAD_SO (1ULL << 63)
+#define PTE_THEAD_C (1ULL << 62)
+#define PTE_THEAD_B (1ULL << 61)
+#define PTE_THEAD_SH (1ULL << 60)
/* Level 0 table, 512GiB per entry */
#define L0_SHIFT 39