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authorVisa Hankala <visa@cvs.openbsd.org>2018-02-24 11:42:32 +0000
committerVisa Hankala <visa@cvs.openbsd.org>2018-02-24 11:42:32 +0000
commit64346d8316f590e48b846c940afd66e048a60e0d (patch)
treeef3897d301deb544b63647b215962651f7e3d7f1 /sys/arch/sgi/localbus/int.c
parent143accdff4683311f176cdaac352bac26677cbf1 (diff)
Declare ci_ipl volatile to prevent the compiler from optimizing
or reordering accesses to the variable. Assume that the assembler preserves the correct sequence of instructions, which allows the removal of the explicit noreorder/reorder toggles from the C code. With ci_ipl being volatile, drop mips_sync() calls that follow the accesses of the variable. The sync is redundant as a compiler barrier. In addition, the MIPS64 CPU designs should not need the sync for pipeline or write buffer control. According to miod@, the use of the instruction is a carryover from code targeting early MIPS designs that lack tight integration with the cache and write buffer. Discussed with and testing help from miod@. Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000, R4400, R8000, R10000 and R16000.
Diffstat (limited to 'sys/arch/sgi/localbus/int.c')
-rw-r--r--sys/arch/sgi/localbus/int.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/sys/arch/sgi/localbus/int.c b/sys/arch/sgi/localbus/int.c
index ef251db20b0..69c4653625d 100644
--- a/sys/arch/sgi/localbus/int.c
+++ b/sys/arch/sgi/localbus/int.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: int.c,v 1.14 2017/02/11 03:44:22 visa Exp $ */
+/* $OpenBSD: int.c,v 1.15 2018/02/24 11:42:31 visa Exp $ */
/* $NetBSD: int.c,v 1.24 2011/07/01 18:53:46 dyoung Exp $ */
/*
@@ -248,10 +248,7 @@ int2_splx(int newipl)
struct cpu_info *ci = curcpu();
register_t sr;
- __asm__ (".set noreorder");
ci->ci_ipl = newipl;
- mips_sync();
- __asm__ (".set reorder\n");
sr = disableintr(); /* XXX overkill? */
int2_write(INT2_LOCAL1_MASK, (int2_intem >> 8) & ~int2_l1imask[newipl]);