diff options
| author | Miod Vallat <miod@cvs.openbsd.org> | 2009-10-14 20:21:17 +0000 |
|---|---|---|
| committer | Miod Vallat <miod@cvs.openbsd.org> | 2009-10-14 20:21:17 +0000 |
| commit | 1c47ce566de2c840c27df8a5f3cbd282fa3c5ec1 (patch) | |
| tree | ceb69f9019d506069bd6fd99c57534ff175ade2c /sys/arch/sgi/pci | |
| parent | 6c51d9766cfc5e17704f527d68eccf76495e3f47 (diff) | |
On IP30 and IP35 systems, try harder to figure out exactly what model we are
running on, and report this both as the hw.product sysctl and in dmesg.
Fuel and Origin 350 are no longer reported as being Origin 300 systems!
Diffstat (limited to 'sys/arch/sgi/pci')
| -rw-r--r-- | sys/arch/sgi/pci/iocreg.h | 45 |
1 files changed, 39 insertions, 6 deletions
diff --git a/sys/arch/sgi/pci/iocreg.h b/sys/arch/sgi/pci/iocreg.h index 6f28557cfa5..c9c2fa54909 100644 --- a/sys/arch/sgi/pci/iocreg.h +++ b/sys/arch/sgi/pci/iocreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: iocreg.h,v 1.3 2009/08/18 19:32:47 miod Exp $ */ +/* $OpenBSD: iocreg.h,v 1.4 2009/10/14 20:21:14 miod Exp $ */ /* * Copyright (c) 2008 Joel Sing. @@ -29,11 +29,36 @@ #define IOCDEV_RTC 4 #define IOCDEV_EF 5 -#define IOC3_SIO_IR 0x0000001c -#define IOC3_SIO_IES 0x00000020 -#define IOC3_SIO_IEC 0x00000024 -#define IOC3_SIO_CR 0x00000028 -#define IOC3_MCR 0x00000030 +/* SuperIO registers */ +#define IOC3_SIO_IR 0x0000001c /* SIO interrupt register */ +#define IOC3_SIO_IES 0x00000020 /* SIO interrupt enable */ +#define IOC3_SIO_IEC 0x00000024 /* SIO interrupt disable */ +#define IOC3_SIO_CR 0x00000028 /* SIO control register */ +#define IOC3_MCR 0x00000030 /* MicroLan control register */ + +/* GPIO registers */ +#define IOC3_GPCR_S 0x00000034 /* GPIO control bit set */ +#define IOC3_GPCR_C 0x00000038 /* GPIO control bit clear */ +#define IOC3_GPDR 0x0000003c /* GPIO data */ +#define IOC3_GPPR_BASE 0x00000040 /* 9 GPIO pin registers */ +#define IOC3_GPPR(x) (IOC3_GPPR_BASE + (x) * 4) + +/* Non-16550 mode UART registers */ +#define IOC3_UARTA_SSCR 0x000000b8 /* control register */ +#define IOC3_UARTA_STPIR 0x000000bc /* TX producer index register */ +#define IOC3_UARTA_STCIR 0x000000c0 /* TX consumer index register */ +#define IOC3_UARTA_SRPIR 0x000000c4 /* RX producer index register */ +#define IOC3_UARTA_SRCIR 0x000000c8 /* RX consumer index register */ +#define IOC3_UARTA_SRTR 0x000000cc /* receive timer register */ +#define IOC3_UARTA_SHADOW 0x000000d0 /* 16550 shadow register */ + +#define IOC3_UARTB_SSCR 0x000000d4 +#define IOC3_UARTB_STPIR 0x000000d8 +#define IOC3_UARTB_STCIR 0x000000dc +#define IOC3_UARTB_SRPIR 0x000000e0 +#define IOC3_UARTB_SRCIR 0x000000e4 +#define IOC3_UARTB_SRTR 0x000000e8 +#define IOC3_UARTB_SHADOW 0x000000ec /* bits in the SIO interrupt register */ #define IOC3_IRQ_UARTA 0x00000040 /* UART A passthrough */ @@ -41,6 +66,14 @@ #define IOC3_IRQ_LPT 0x00040000 /* parallel port passthrough */ #define IOC3_IRQ_KBC 0x00400000 /* keyboard controller */ +/* bits in GPCR */ +#define IOC3_GPCR_UARTA_PIO 0x00000040 /* UARTA in PIO mode */ +#define IOC3_GPCR_UARTB_PIO 0x00000080 /* UARTB in PIO mode */ +#define IOC3_GPCR_MLAN 0x00200000 /* MicroLan enable */ + +/* bits in SSCR */ +#define IOC3_SSCR_RESET 0x80000000 + #define IOC3_LPT_BASE 0x00000080 #define IOC3_LPT_SIZE 0x0000001c |