Introduce a new pci routine, pci_conf_size(), which returns the size of a

given pcitag_t configuration address space. Currently, all pci controllers
will return the usual 0x100 bytes of PCI configuration space, but this will
eventually change on PCIe-capable controlers.
ok kettenis@

3 files changed, 40 insertions, 3 deletions

diff --git a/sys/arch/sgi/pci/macepcibridge.c b/sys/arch/sgi/pci/macepcibridge.c
index 1929f2e1149..0dde121fd35 100644
--- a/sys/arch/sgi/pci/macepcibridge.c
+++ b/sys/arch/sgi/pci/macepcibridge.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: macepcibridge.c,v 1.40 2010/09/22 02:28:37 jsg Exp $ */
+/*	$OpenBSD: macepcibridge.c,v 1.41 2010/12/04 17:06:31 miod Exp $ */
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -82,6 +82,7 @@ void	 mace_pcibr_attach_hook(struct device *, struct device *,
 int	 mace_pcibr_bus_maxdevs(void *, int);
 pcitag_t mace_pcibr_make_tag(void *, int, int, int);
 void	 mace_pcibr_decompose_tag(void *, pcitag_t, int *, int *, int *);
+int	 mace_pcibr_conf_size(void *, pcitag_t);
 pcireg_t mace_pcibr_conf_read(void *, pcitag_t, int);
 void	 mace_pcibr_conf_write(void *, pcitag_t, int, pcireg_t);
 int	 mace_pcibr_get_widget(void *);
@@ -239,6 +240,7 @@ mace_pcibrattach(struct device *parent, struct device *self, void *aux)
 	sc->sc_pc.pc_make_tag = mace_pcibr_make_tag;
 	sc->sc_pc.pc_decompose_tag = mace_pcibr_decompose_tag;
 	sc->sc_pc.pc_bus_maxdevs = mace_pcibr_bus_maxdevs;
+	sc->sc_pc.pc_conf_size = mace_pcibr_conf_size;
 	sc->sc_pc.pc_conf_read = mace_pcibr_conf_read;
 	sc->sc_pc.pc_conf_write = mace_pcibr_conf_write;
 	sc->sc_pc.pc_get_widget = mace_pcibr_get_widget;
@@ -365,6 +367,12 @@ mace_pcibr_bus_maxdevs(void *cpv, int busno)
 	return busno == 0 ? 6 : 32;
 }
 
+int
+mace_pcibr_conf_size(void *cpv, pcitag_t tag)
+{
+	return PCI_CONFIG_SPACE_SIZE;
+}
+
 pcireg_t
 mace_pcibr_conf_read(void *cpv, pcitag_t tag, int offset)
 {
diff --git a/sys/arch/sgi/pci/pci_machdep.h b/sys/arch/sgi/pci/pci_machdep.h
index 51190bca23d..c2a6c8f1093 100644
--- a/sys/arch/sgi/pci/pci_machdep.h
+++ b/sys/arch/sgi/pci/pci_machdep.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pci_machdep.h,v 1.11 2010/06/29 22:08:29 jordan Exp $ */
+/*	$OpenBSD: pci_machdep.h,v 1.12 2010/12/04 17:06:31 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -44,6 +44,7 @@ struct mips_pci_chipset {
     pcitag_t	(*pc_make_tag)(void *, int, int, int);
     void	(*pc_decompose_tag)(void *, pcitag_t, int *,
 		    int *, int *);
+    int		(*pc_conf_size)(void *, pcitag_t);
     pcireg_t	(*pc_conf_read)(void *, pcitag_t, int);
     void	(*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
     int		(*pc_get_widget)(void *);
@@ -75,6 +76,8 @@ struct mips_pci_chipset {
     (*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
 #define	pci_decompose_tag(c, t, bp, dp, fp)				\
     (*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
+#define	pci_conf_size(c, t)						\
+    (*(c)->pc_conf_size)((c)->pc_conf_v, (t))
 #define	pci_conf_read(c, t, r)						\
     (*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
 #define	pci_conf_write(c, t, r, v)					\
diff --git a/sys/arch/sgi/xbow/xbridge.c b/sys/arch/sgi/xbow/xbridge.c
index 1cd92168b9e..88d60a9f9d9 100644
--- a/sys/arch/sgi/xbow/xbridge.c
+++ b/sys/arch/sgi/xbow/xbridge.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xbridge.c,v 1.77 2010/11/27 18:21:05 miod Exp $	*/
+/*	$OpenBSD: xbridge.c,v 1.78 2010/12/04 17:06:32 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009  Miodrag Vallat.
@@ -204,6 +204,7 @@ void	xbridge_attach_hook(struct device *, struct device *,
 int	xbridge_bus_maxdevs(void *, int);
 pcitag_t xbridge_make_tag(void *, int, int, int);
 void	xbridge_decompose_tag(void *, pcitag_t, int *, int *, int *);
+int	xbridge_conf_size(void *, pcitag_t);
 pcireg_t xbridge_conf_read(void *, pcitag_t, int);
 void	xbridge_conf_write(void *, pcitag_t, int, pcireg_t);
 int	xbridge_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
@@ -580,6 +581,7 @@ xbpci_attach(struct device *parent, struct device *self, void *aux)
 	xb->xb_pc.pc_make_tag = xbridge_make_tag;
 	xb->xb_pc.pc_decompose_tag = xbridge_decompose_tag;
 	xb->xb_pc.pc_bus_maxdevs = xbridge_bus_maxdevs;
+	xb->xb_pc.pc_conf_size = xbridge_conf_size;
 	xb->xb_pc.pc_conf_read = xbridge_conf_read;
 	xb->xb_pc.pc_conf_write = xbridge_conf_write;
 	xb->xb_pc.pc_get_widget = xbridge_get_widget;
@@ -691,6 +693,30 @@ xbridge_bus_maxdevs(void *cookie, int busno)
 	return busno == 0 ? xb->xb_nslots : 32;
 }
 
+int
+xbridge_conf_size(void *cookie, pcitag_t tag)
+{
+#if 0
+	struct xbpci_softc *xb = cookie;
+	int bus, dev, fn;
+
+	xbridge_decompose_tag(cookie, tag, &bus, &dev, &fn);
+
+	/*
+	 * IOC3 devices only implement a subset of the PCI configuration
+	 * registers. Although xbridge_conf_{read,write} correctly
+	 * handle the unimplemented registers, better provide a limited
+	 * configuration space to userland.
+	 */
+
+	if (bus == 0 && xb->xb_devices[dev].id ==
+	    PCI_ID_CODE(PCI_VENDOR_SGI, PCI_PRODUCT_SGI_IOC3))
+		return PCI_INTERRUPT_REG + 4;
+#endif
+
+	return PCI_CONFIG_SPACE_SIZE;
+}
+
 pcireg_t
 xbridge_conf_read(void *cookie, pcitag_t tag, int offset)
 {