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authorMiod Vallat <miod@cvs.openbsd.org>2010-02-13 14:07:31 +0000
committerMiod Vallat <miod@cvs.openbsd.org>2010-02-13 14:07:31 +0000
commita39abfe300fee0e53216f744f86e1b2d36ee97c4 (patch)
treec7a741c0d6e2724811aaf2949f3ec07c9a195ca7 /sys/arch/sgi
parente124446575d590a7ba2232d8ad8f2cbd1be155ca (diff)
Since the TLB handler exception code is now always a trampoline to branch
to the handler code in the kernel, we can use relative branches in it to make it a bit faster. Also, get rid of the tlbmiss handler and have both the tlb and xtlb refill exceptions branch to the xtlbmiss handler.
Diffstat (limited to 'sys/arch/sgi')
-rw-r--r--sys/arch/sgi/sgi/machdep.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index bae4b29b70c..8f5e6a7b042 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.98 2010/01/22 21:45:26 miod Exp $ */
+/* $OpenBSD: machdep.c,v 1.99 2010/02/13 14:07:30 miod Exp $ */
/*
* Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
@@ -144,7 +144,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
char *cp;
int i;
u_int cputype;
- vaddr_t tlb_handler, xtlb_handler;
+ vaddr_t xtlb_handler;
extern char start[], edata[], end[];
extern char exception[], e_exception[];
extern char *hw_vendor;
@@ -466,24 +466,20 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
* This is also necessary on RM52x0 and most RM7k/RM9k,
* and is a documented errata for these chips.
*/
- extern void tlb_miss_err_r5k;
extern void xtlb_miss_err_r5k;
- tlb_handler = (vaddr_t)&tlb_miss_err_r5k;
xtlb_handler = (vaddr_t)&xtlb_miss_err_r5k;
}
break;
#endif
default:
{
- extern void tlb_miss;
extern void xtlb_miss;
- tlb_handler = (vaddr_t)&tlb_miss;
xtlb_handler = (vaddr_t)&xtlb_miss;
}
break;
}
- build_trampoline(TLB_MISS_EXC_VEC, tlb_handler);
+ build_trampoline(TLB_MISS_EXC_VEC, xtlb_handler);
build_trampoline(XTLB_MISS_EXC_VEC, xtlb_handler);
/*