Add cache operation functions pointers to struct cpu_info; the various

cache lines and sizes are already there, after all.

The ConfigCache cache routine is responsible for filling these function
pointers; cache routine invocation macros are updated to use the cpu_info
fields, but may still be overriden in <machine/cpu.h> on platforms where
only one set of cache routines is used.

4 files changed, 22 insertions, 62 deletions

diff --git a/sys/arch/sgi/include/autoconf.h b/sys/arch/sgi/include/autoconf.h
index 7a6f08c6cc7..88d72509152 100644
--- a/sys/arch/sgi/include/autoconf.h
+++ b/sys/arch/sgi/include/autoconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: autoconf.h,v 1.37 2012/05/29 17:37:09 mikeb Exp $ */
+/*	$OpenBSD: autoconf.h,v 1.38 2012/06/24 16:26:04 miod Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -44,14 +44,6 @@ struct sys_rec {
 	int	system_type;
 	int	system_subtype;		/* IP35 only */
 
-	/* Published cache operations. */
-	void    (*_SyncCache)(struct cpu_info *);
-	void    (*_InvalidateICache)(struct cpu_info *, vaddr_t, size_t);
-	void    (*_SyncDCachePage)(struct cpu_info *, vaddr_t, paddr_t);
-	void    (*_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t);
-	void    (*_IOSyncDCache)(struct cpu_info *, vaddr_t, size_t, int);
-	void    (*_HitInvalidateDCache)(struct cpu_info *, vaddr_t, size_t);
-
 	/* Serial console configuration. */
 	struct mips_bus_space console_io;
 };
@@ -68,7 +60,7 @@ struct mainbus_attach_args {
 
 /*
  * Device physical location information.  Used to match console and boot
- * devices.
+ * devices on IP27 and IP30 kernels.
  */
 struct sgi_device_location {
 	int16_t		nasid;		/* node identifier */
diff --git a/sys/arch/sgi/include/cpu.h b/sys/arch/sgi/include/cpu.h
index 2aa2e9e4877..18181df485a 100644
--- a/sys/arch/sgi/include/cpu.h
+++ b/sys/arch/sgi/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.13 2012/04/21 12:20:30 miod Exp $ */
+/*	$OpenBSD: cpu.h,v 1.14 2012/06/24 16:26:04 miod Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -58,21 +58,6 @@ void hw_ipi_intr_clear(u_long);
 void hw_cpu_init_secondary(struct cpu_info *);
 #endif	/* MULTIPROCESSOR && !_LOCORE */
 
-/*
- * Define soft selected cache functions.
- */
-#define	Mips_SyncCache(ci)			\
-	(*(sys_config._SyncCache))((ci))
-#define	Mips_InvalidateICache(ci, va, l)	\
-	(*(sys_config._InvalidateICache))((ci), (va), (l))
-#define	Mips_SyncDCachePage(ci, va, pa)		\
-	(*(sys_config._SyncDCachePage))((ci), (va), (pa))
-#define	Mips_HitSyncDCache(ci, va, l)	\
-	(*(sys_config._HitSyncDCache))((ci), (va), (l))
-#define	Mips_IOSyncDCache(ci, va, l, h)	\
-	(*(sys_config._IOSyncDCache))((ci), (va), (l), (h))
-#define	Mips_HitInvalidateDCache(ci, va, l)	\
-	(*(sys_config._HitInvalidateDCache))((ci), (va), (l))
 
 #endif/* _KERNEL */
 
diff --git a/sys/arch/sgi/sgi/ip30_machdep.c b/sys/arch/sgi/sgi/ip30_machdep.c
index d21d4526267..d3f9162c7f3 100644
--- a/sys/arch/sgi/sgi/ip30_machdep.c
+++ b/sys/arch/sgi/sgi/ip30_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip30_machdep.c,v 1.52 2012/04/03 21:17:35 miod Exp $	*/
+/*	$OpenBSD: ip30_machdep.c,v 1.53 2012/06/24 16:26:04 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -168,8 +168,9 @@ ip30_setup()
 	 * may consider this an evil abuse of bus_space knowledge, though.
 	 */
 
-	xbow_build_bus_space(&sys_config.console_io, 0, 15);
-	sys_config.console_io.bus_base = ip30_widget_long(0, 15) +
+	xbow_build_bus_space(&sys_config.console_io, 0, IP30_BRIDGE_WIDGET);
+	sys_config.console_io.bus_base =
+	    ip30_widget_long(0, IP30_BRIDGE_WIDGET) +
 	    BRIDGE_PCI0_MEM_SPACE_BASE + 0x500000;
 
 	comconsaddr = IOC3_UARTA_BASE;
@@ -233,7 +234,7 @@ ip30_autoconf(struct device *parent)
 			 */
 			bcopy(&bootcpu_hwinfo, &hw, sizeof(struct cpu_hwinfo));
 			hw.c0prid = 
-		           *(volatile uint32_t *)(mpconf + MPCONF_PRID(cpuid));
+			    *(volatile uint32_t *)(mpconf + MPCONF_PRID(cpuid));
 			hw.type = (hw.c0prid >> 8) & 0xff;
 			hw.l2size = 1 << *(volatile uint32_t *)
 			    (mpconf + MPCONF_SCACHESZ(cpuid));
@@ -258,7 +259,7 @@ ip30_autoconf(struct device *parent)
 paddr_t
 ip30_widget_short(int16_t nasid, u_int widget)
 {
-	return PHYS_TO_XKPHYS((uint64_t)((widget) << 24) | (1ULL << 28), CCA_NC);
+	return PHYS_TO_XKPHYS(((uint64_t)widget << 24) | (1ULL << 28), CCA_NC);
 }
 
 paddr_t
@@ -291,8 +292,7 @@ ip30_widget_id(int16_t nasid, u_int widget, uint32_t *wid)
 {
 	paddr_t linkpa, wpa;
 
-	if (widget != 0)
-	{
+	if (widget != 0) {
 		if (widget < WIDGET_MIN || widget > WIDGET_MAX)
 			return EINVAL;
 
@@ -605,18 +605,19 @@ hw_ipi_intr_clear(u_long cpuid)
 void
 hw_cpu_init_secondary(struct cpu_info *ci)
 {
-       /*
-        * When attaching secondary processors, cache information is not
-        * available yet.  But since the MP-capable systems we run on
-        * currently all have R10k-style caches, we can quickly compute
-        * the needed values.
-        */
+	/*
+	 * When attaching secondary processors, cache information is not
+	 * available yet.  But since the MP-capable systems we run on
+	 * currently all have R10k-style caches, we can quickly compute
+	 * the needed values.
+	 */
 	ci->ci_cacheways = 2;
 	ci->ci_l1instcachesize = 32 * 1024;
 	ci->ci_l1instcacheline = 64;
 	ci->ci_l1datacachesize = 32 * 1024;
-	ci->ci_l1datacacheline = 64;
+	ci->ci_l1datacacheline = 32;
 	ci->ci_l2size = ci->ci_hw.l2size;
+	ci->ci_l2line = 64;			/* safe default */
 	ci->ci_l3size = 0;
 }
 #endif
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index c0150956c24..0fbb2daaaf8 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.125 2012/05/29 17:37:09 mikeb Exp $ */
+/*	$OpenBSD: machdep.c,v 1.126 2012/06/24 16:26:04 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -445,35 +445,17 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 	switch (cputype) {
 #ifdef CPU_R4000
 	case MIPS_R4000:
-		Mips4k_ConfigCache(curcpu());
-		sys_config._SyncCache = Mips4k_SyncCache;
-		sys_config._InvalidateICache = Mips4k_InvalidateICache;
-		sys_config._SyncDCachePage = Mips4k_SyncDCachePage;
-		sys_config._HitSyncDCache = Mips4k_HitSyncDCache;
-		sys_config._IOSyncDCache = Mips4k_IOSyncDCache;
-		sys_config._HitInvalidateDCache = Mips4k_HitInvalidateDCache;
+		Mips4k_ConfigCache(ci);
 		break;
 #endif
 #if defined(CPU_R4600) || defined(CPU_R5000) || defined(CPU_RM7000)
 	case MIPS_R5000:
-		Mips5k_ConfigCache(curcpu());
-		sys_config._SyncCache = Mips5k_SyncCache;
-		sys_config._InvalidateICache = Mips5k_InvalidateICache;
-		sys_config._SyncDCachePage = Mips5k_SyncDCachePage;
-		sys_config._HitSyncDCache = Mips5k_HitSyncDCache;
-		sys_config._IOSyncDCache = Mips5k_IOSyncDCache;
-		sys_config._HitInvalidateDCache = Mips5k_HitInvalidateDCache;
+		Mips5k_ConfigCache(ci);
 		break;
 #endif
 #ifdef CPU_R10000
 	case MIPS_R10000:
-		Mips10k_ConfigCache(curcpu());
-		sys_config._SyncCache = Mips10k_SyncCache;
-		sys_config._InvalidateICache = Mips10k_InvalidateICache;
-		sys_config._SyncDCachePage = Mips10k_SyncDCachePage;
-		sys_config._HitSyncDCache = Mips10k_HitSyncDCache;
-		sys_config._IOSyncDCache = Mips10k_IOSyncDCache;
-		sys_config._HitInvalidateDCache = Mips10k_HitInvalidateDCache;
+		Mips10k_ConfigCache(ci);
 		break;
 #endif
 	default: