Move cache information from global variables to per-cpu_info fields; this

allows processors with different cache sizes to be used.

Cache management routines now take a struct cpu_info * as first parameter.

5 files changed, 39 insertions, 34 deletions

diff --git a/sys/arch/sgi/include/autoconf.h b/sys/arch/sgi/include/autoconf.h
index f638cd0a560..b2325bd0212 100644
--- a/sys/arch/sgi/include/autoconf.h
+++ b/sys/arch/sgi/include/autoconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: autoconf.h,v 1.28 2010/01/09 20:33:16 miod Exp $ */
+/*	$OpenBSD: autoconf.h,v 1.29 2010/01/09 23:34:29 miod Exp $ */
 
 /*
  * Copyright (c) 2001-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -38,17 +38,19 @@
 /*
  * Structure holding all misc config information.
  */
+struct cpu_info;
+
 struct sys_rec {
 	int	system_type;
 	int	system_subtype;		/* IP35 only */
 
 	/* Published cache operations. */
-	void    (*_SyncCache)(void);
-	void    (*_InvalidateICache)(vaddr_t, size_t);
-	void    (*_SyncDCachePage)(vaddr_t);
-	void    (*_HitSyncDCache)(vaddr_t, size_t);
-	void    (*_IOSyncDCache)(vaddr_t, size_t, int);
-	void    (*_HitInvalidateDCache)(vaddr_t, size_t);
+	void    (*_SyncCache)(struct cpu_info *);
+	void    (*_InvalidateICache)(struct cpu_info *, vaddr_t, size_t);
+	void    (*_SyncDCachePage)(struct cpu_info *, vaddr_t);
+	void    (*_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t);
+	void    (*_IOSyncDCache)(struct cpu_info *, vaddr_t, size_t, int);
+	void    (*_HitInvalidateDCache)(struct cpu_info *, vaddr_t, size_t);
 
 	/* Serial console configuration. */
 	struct mips_bus_space console_io;
diff --git a/sys/arch/sgi/include/cpu.h b/sys/arch/sgi/include/cpu.h
index 9bfd6a126c6..cfa370c3622 100644
--- a/sys/arch/sgi/include/cpu.h
+++ b/sys/arch/sgi/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.7 2009/12/28 07:18:39 syuu Exp $ */
+/*	$OpenBSD: cpu.h,v 1.8 2010/01/09 23:34:29 miod Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -75,18 +75,18 @@ void hw_ipi_intr_clear(u_long);
 /*
  * Define soft selected cache functions.
  */
-#define	Mips_SyncCache()			\
-	(*(sys_config._SyncCache))()
-#define	Mips_InvalidateICache(va, l)		\
-	(*(sys_config._InvalidateICache))((va), (l))
-#define	Mips_SyncDCachePage(va, pa)		\
-	(*(sys_config._SyncDCachePage))((va))
-#define	Mips_HitSyncDCache(va, pa, l)		\
-	(*(sys_config._HitSyncDCache))((va), (l))
-#define	Mips_IOSyncDCache(va, pa, l, h)		\
-	(*(sys_config._IOSyncDCache))((va), (l), (h))
-#define	Mips_HitInvalidateDCache(va, pa, l)	\
-	(*(sys_config._HitInvalidateDCache))((va), (l))
+#define	Mips_SyncCache(ci)			\
+	(*(sys_config._SyncCache))((ci))
+#define	Mips_InvalidateICache(ci, va, l)	\
+	(*(sys_config._InvalidateICache))((ci), (va), (l))
+#define	Mips_SyncDCachePage(ci, va, pa)		\
+	(*(sys_config._SyncDCachePage))((ci), (va))
+#define	Mips_HitSyncDCache(ci, va, pa, l)	\
+	(*(sys_config._HitSyncDCache))((ci), (va), (l))
+#define	Mips_IOSyncDCache(ci, va, pa, l, h)	\
+	(*(sys_config._IOSyncDCache))((ci), (va), (l), (h))
+#define	Mips_HitInvalidateDCache(ci, va, pa, l)	\
+	(*(sys_config._HitInvalidateDCache))((ci), (va), (l))
 
 #endif/* _KERNEL */
 
diff --git a/sys/arch/sgi/sgi/bus_dma.c b/sys/arch/sgi/sgi/bus_dma.c
index 7a226d4bf79..f5967a1c60f 100644
--- a/sys/arch/sgi/sgi/bus_dma.c
+++ b/sys/arch/sgi/sgi/bus_dma.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bus_dma.c,v 1.16 2009/12/25 21:02:18 miod Exp $ */
+/*	$OpenBSD: bus_dma.c,v 1.17 2010/01/09 23:34:29 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -312,6 +312,7 @@ _dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t addr,
 #define SYNC_X 2	/* WB writeback + invalidate, WT invalidate */
 	int nsegs;
 	int curseg;
+	struct cpu_info *ci = curcpu();
 
 	nsegs = map->dm_nsegs;
 	curseg = 0;
@@ -353,20 +354,22 @@ _dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t addr,
 			 */
 			if (op & BUS_DMASYNC_PREWRITE) {
 #ifdef TGT_COHERENT
-				Mips_IOSyncDCache(vaddr, paddr, ssize, SYNC_W);
+				Mips_IOSyncDCache(ci, vaddr, paddr,
+				    ssize, SYNC_W);
 #else
 				if (op & BUS_DMASYNC_PREREAD)
-					Mips_IOSyncDCache(vaddr, paddr, ssize,
-					    SYNC_X);
+					Mips_IOSyncDCache(ci, vaddr, paddr,
+					    ssize, SYNC_X);
 				else
-					Mips_IOSyncDCache(vaddr, paddr, ssize,
-					    SYNC_W);
+					Mips_IOSyncDCache(ci, vaddr, paddr,
+					    ssize, SYNC_W);
 #endif
 			} else
 			if (op & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_POSTREAD)) {
 #ifdef TGT_COHERENT
 #else
-				Mips_IOSyncDCache(vaddr, paddr, ssize, SYNC_R);
+				Mips_IOSyncDCache(ci, vaddr, paddr,
+				    ssize, SYNC_R);
 #endif
 			}
 			size -= ssize;
diff --git a/sys/arch/sgi/sgi/ip30_machdep.c b/sys/arch/sgi/sgi/ip30_machdep.c
index 64392b292ed..a5802857308 100644
--- a/sys/arch/sgi/sgi/ip30_machdep.c
+++ b/sys/arch/sgi/sgi/ip30_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip30_machdep.c,v 1.30 2010/01/09 20:33:16 miod Exp $	*/
+/*	$OpenBSD: ip30_machdep.c,v 1.31 2010/01/09 23:34:29 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -416,7 +416,7 @@ hw_cpu_hatch(struct cpu_info *ci)
         */
        setsr(getsr() | SR_KX | SR_UX);
 
-       Mips10k_ConfigCache();
+	Mips10k_ConfigCache(ci);
 
 	tlb_set_page_mask(TLB_PAGE_MASK);
 	tlb_set_wired(0);
@@ -433,7 +433,7 @@ hw_cpu_hatch(struct cpu_info *ci)
        /*
         * Clear out the I and D caches.
         */
-       Mips_SyncCache();
+       Mips_SyncCache(ci);
 
        cpu_startclock(ci);
 
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index b05941d6829..1b26fdef6b8 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.96 2010/01/09 20:33:16 miod Exp $ */
+/*	$OpenBSD: machdep.c,v 1.97 2010/01/09 23:34:29 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -385,7 +385,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 	default:
 #if defined(CPU_R5000) || defined(CPU_RM7000)
 	case MIPS_R5000:
-		Mips5k_ConfigCache();
+		Mips5k_ConfigCache(curcpu());
 		sys_config._SyncCache = Mips5k_SyncCache;
 		sys_config._InvalidateICache = Mips5k_InvalidateICache;
 		sys_config._SyncDCachePage = Mips5k_SyncDCachePage;
@@ -396,7 +396,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 #endif
 #ifdef CPU_R10000
 	case MIPS_R10000:
-		Mips10k_ConfigCache();
+		Mips10k_ConfigCache(curcpu());
 		sys_config._SyncCache = Mips10k_SyncCache;
 		sys_config._InvalidateICache = Mips10k_InvalidateICache;
 		sys_config._SyncDCachePage = Mips10k_SyncDCachePage;
@@ -494,7 +494,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 	/*
 	 * Clear out the I and D caches.
 	 */
-	Mips_SyncCache();
+	Mips_SyncCache(curcpu());
 
 #ifdef DDB
 	db_machine_init();