netbsd port, now we merge our changes back in

1 files changed, 57 insertions, 47 deletions

diff --git a/sys/arch/sparc/dev/dmareg.h b/sys/arch/sparc/dev/dmareg.h
index d19c5c2960e..3998581845a 100644
--- a/sys/arch/sparc/dev/dmareg.h
+++ b/sys/arch/sparc/dev/dmareg.h
@@ -1,9 +1,7 @@
-/*	$NetBSD: dmareg.h,v 1.5 1994/11/20 20:52:06 deraadt Exp $ */
+/*	$NetBSD: dmareg.h,v 1.8 1996/04/22 02:34:58 abrown Exp $ */
 
 /*
  * Copyright (c) 1994 Peter Galbavy.  All rights reserved.
- * Copyright (c) 1995 Theo de Raadt.  All rights reserved.
- *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -14,8 +12,7 @@
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
- *	This product includes software developed by Peter Galbavy and
- *	Theo de Raadt.
+ *	This product includes software developed by Peter Galbavy.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  *
@@ -31,51 +28,64 @@
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#define DMACSRBITS "\020\01INT\02ERR\03DR1\04DR2\05IEN\011WRITE\016ENCNT\017TC\032DMAON"
+
 struct dma_regs {
-	volatile u_long	csr;		/* DMA CSR */
-#define D_INT_PEND	0x00000001	/* interrupt pending */
-#define D_ERR_PEND	0x00000002	/* error pending */
-#define D_DRAINING	0x0000000c	/* fifo draining */
-#define D_INT_EN	0x00000010	/* interrupt enable */
-#define D_INVALIDATE	0x00000020	/* invalidate fifo */
-#define D_SLAVE_ERR	0x00000040	/* slave access size error */
-#define D_DRAIN		0x00000040	/* drain fifo if DMAREV_1 */
-#define D_RESET		0x00000080	/* reset scsi */
-#define D_WRITE		0x00000100	/* 1 = dev -> mem */
-#define D_EN_DMA	0x00000200	/* enable DMA requests */
-#define D_R_PEND	0x00000400	/* no reset/flush allowed! */
-#define D_BYTEADDR	0x00001800	/* next byte to be accessed by esp */
-#define D_EN_CNT	0x00002000	/* enable byte counter */
-#define D_TC		0x00004000	/* terminal count */
-#define D_ILLAC		0x00008000	/* enable lance ethernet */
-#define D_DSBL_CSR_DRN	0x00010000	/* disable fifo drain on csr */
-#define D_DSBL_SCSI_DRN	0x00020000	/* disable fifo drain on reg */
-#define D_BURST_SIZE	0x000c0000	/* sbus read/write burst size */
-#define D_DIAG		0x00100000	/* disable fifo drain on addr */
-#define D_TWO_CYCLE	0x00200000	/* 2 clocks per transfer */
-#define D_FASTER	0x00400000	/* 3 clocks per transfer */
-#define D_TCI_DIS	0x00800000	/* disable intr on D_TC */
-#define D_EN_NEXT	0x01000000	/* enable auto next address */
-#define D_DMA_ON	0x02000000	/* enable dma from scsi */
-#define D_A_LOADED	0x04000000	/* address loaded */
-#define D_NA_LOADED	0x08000000	/* next address loaded */
-#define D_DEV_ID	0xf0000000	/* device ID */
-#define	 DMAREV_4300	0x00000000	/* Sunray DMA */
-#define  DMAREV_ESC1	0x40000000	/* ESC gate array */
-#define  DMAREV_1	0x80000000	/* 'DMA' */
-#define  DMAREV_PLUS	0x90000000	/* 'DMA+' */
-#define  DMAREV_2	0xa0000000	/* 'DMA2' */
+	volatile u_long		csr;		/* DMA CSR */
+#define  D_INT_PEND		0x00000001	/* interrupt pending */
+#define  D_ERR_PEND		0x00000002	/* error pending */
+#define  D_DRAINING		0x0000000c	/* fifo draining */
+#define  D_INT_EN		0x00000010	/* interrupt enable */
+#define  D_INVALIDATE		0x00000020	/* invalidate fifo */
+#define  D_SLAVE_ERR		0x00000040	/* slave access size error */
+#define  D_DRAIN		0x00000040	/* drain fifo if DMAREV_1 */
+#define  D_RESET		0x00000080	/* reset scsi */
+#define  D_WRITE		0x00000100	/* 1 = dev -> mem */
+#define  D_EN_DMA		0x00000200	/* enable DMA requests */
+#define  D_R_PEND		0x00000400	/* something only on ver < 2 */
+#define  D_EN_CNT		0x00002000	/* enable byte counter */
+#define  D_TC			0x00004000	/* terminal count */
+#define  D_DSBL_CSR_DRN		0x00010000	/* disable fifo drain on csr */
+#define  D_DSBL_SCSI_DRN	0x00020000	/* disable fifo drain on reg */
+#define  D_BURST_SIZE		0x000c0000	/* sbus read/write burst size */
+#define   D_BURST_0		0x00080000	/*   no bursts (SCSI-only) */
+#define   D_BURST_16		0x00040000	/*   16-byte bursts */
+#define   D_BURST_32    	0x00000000	/*   32-byte bursts */
+#define  D_DIAG			0x00100000	/* disable fifo drain on addr */
+#define  D_TWO_CYCLE		0x00200000	/* 2 clocks per transfer */
+#define  D_FASTER		0x00400000	/* 3 clocks per transfer */
+#define	 DE_AUI_TP		0x00400000	/* 1 for TP, 0 for AUI */
+#define  D_TCI_DIS		0x00800000	/* disable intr on D_TC */
+#define  D_EN_NEXT		0x01000000	/* enable auto next address */
+#define  D_DMA_ON		0x02000000	/* enable dma from scsi */
+#define  D_A_LOADED		0x04000000	/* address loaded */
+#define  D_NA_LOADED		0x08000000	/* next address loaded */
+#define  D_DEV_ID		0xf0000000	/* device ID */
+#define   DMAREV_0		0x00000000	/* Sunray DMA */
+#define   DMAREV_1		0x80000000	/* 'DMA' */
+#define   DMAREV_PLUS		0x90000000	/* 'DMA+' */
+#define   DMAREV_2		0xa0000000	/* 'DMA2' */
 
-	volatile caddr_t addr;
-#define DMA_D_ADDR	0x01		/* DMA ADDR */
+	volatile caddr_t	addr;
+#define DMA_D_ADDR		0x01		/* DMA ADDR (in u_longs) */
 
-	/*
-	 * some versions of dma controller lack the following
-	 * two registers -- do not use them!
-	 */
+	volatile u_long		bcnt;		/* DMA COUNT (in u_longs) */
+#define  D_BCNT_MASK		0x00ffffff	/* only 24 bits */
 
-	volatile u_long	bcnt;		/* DMA COUNT */
-#define  D_BCNT_MASK	0x00ffffff	/* only 24 bits */
+	volatile u_long		test;		/* DMA TEST (in u_longs) */
+#define en_testcsr	addr			/* enet registers overlap */
+#define en_cachev	bcnt
+#define en_bar		test
 
-	volatile u_long	test;		/* DMA TEST (in u_longs) */
 };
+
+/*
+ * PROM-reported DMA burst sizes for the SBus
+ */
+#define SBUS_BURST_1	0x1
+#define SBUS_BURST_2	0x2
+#define SBUS_BURST_4	0x4
+#define SBUS_BURST_8	0x8
+#define SBUS_BURST_16	0x10
+#define SBUS_BURST_32	0x20
+#define SBUS_BURST_64	0x40