diff options
| author | Jason Downs <downsj@cvs.openbsd.org> | 1997-08-08 08:27:49 +0000 |
|---|---|---|
| committer | Jason Downs <downsj@cvs.openbsd.org> | 1997-08-08 08:27:49 +0000 |
| commit | c6af50ae96c114059441edde31a2879102e32d99 (patch) | |
| tree | e77d44cd72b4d881fb3461d76bdd50f77adc0966 /sys/arch/sparc/dev/dmavar.h | |
| parent | c1492b0f5209b759b0ab6624db56b310c28e48e2 (diff) | |
Mostly sync to NetBSD-current 970804.
GENERIC currently compiles and runs; some devices (isp) are not complete and
not yet enabled.
Diffstat (limited to 'sys/arch/sparc/dev/dmavar.h')
| -rw-r--r-- | sys/arch/sparc/dev/dmavar.h | 32 |
1 files changed, 4 insertions, 28 deletions
diff --git a/sys/arch/sparc/dev/dmavar.h b/sys/arch/sparc/dev/dmavar.h index 6bc42333a98..57fbbcad5e4 100644 --- a/sys/arch/sparc/dev/dmavar.h +++ b/sys/arch/sparc/dev/dmavar.h @@ -1,4 +1,5 @@ -/* $NetBSD: dmavar.h,v 1.8 1996/04/22 02:35:00 abrown Exp $ */ +/* $OpenBSD: dmavar.h,v 1.4 1997/08/08 08:24:59 downsj Exp $ */ +/* $NetBSD: dmavar.h,v 1.11 1996/11/27 21:49:53 pk Exp $ */ /* * Copyright (c) 1994 Peter Galbavy. All rights reserved. @@ -35,7 +36,7 @@ struct dma_softc { struct le_softc *sc_le; /* my ethernet */ struct dma_regs *sc_regs; /* the registers */ int sc_active; /* DMA active ? */ - int sc_rev; /* revision */ + u_int sc_rev; /* revision */ int sc_node; /* PROM node ID */ int sc_burst; /* DVMA burst size in effect */ caddr_t sc_dvmakaddr; /* DVMA cookies */ @@ -53,32 +54,7 @@ struct dma_softc { #define DMACSR(sc) (sc->sc_regs->csr) #define DMADDR(sc) (sc->sc_regs->addr) - -/* - * We are not allowed to touch the DMA "flush" and "drain" bits - * while it is still thinking about a request (DMA_RP). - */ - -/* - * TIME WAIT (to debug hanging machine problem) - */ - -#define TIME_WAIT(COND, MSG, SC) { int count = 500000; \ - while (--count > 0 && (COND)) DELAY(1); \ - if (count == 0) { \ - printf("CSR = %lx\n",\ - SC->sc_regs->csr);\ - panic(MSG); } \ - } - -#define DMAWAIT(sc) TIME_WAIT((sc->sc_regs->csr & D_R_PEND), "DMAWAIT", sc) -#define DMAWAIT1(sc) TIME_WAIT((sc->sc_regs->csr & D_DRAINING), "DMAWAIT1", sc) -#define DMAREADY(sc) TIME_WAIT((!(sc->sc_regs->csr & D_DMA_ON)), "DMAREADY", sc) - -#define DMA_DRAIN(sc) if (sc->sc_rev < DMAREV_2) { \ - DMACSR(sc) |= D_DRAIN; \ - DMAWAIT1(sc); \ - } +#define DMACNT(sc) (sc->sc_regs->bcnt) /* DMA engine functions */ #define DMA_ENINTR(r) (((r)->enintr)(r)) |