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authorMark Kettenis <kettenis@cvs.openbsd.org>2008-07-10 09:29:34 +0000
committerMark Kettenis <kettenis@cvs.openbsd.org>2008-07-10 09:29:34 +0000
commit6b5b3279f0b20db9ea02aed5f3f788e2af01fa28 (patch)
treed3a1dd6d8ad73bc8cca6ec99ea64c354587fcf30 /sys/arch/sparc64/include
parent53a75d7d59fcfe75c0fec20bbad71a82254a6aff (diff)
Add support for Fujitsu SPARC64-VI CPUs.
UltraSPARC I/II has a 41-bit physical address space, UltraSPARC III/IV has a 43-bit physical address space. The Fujitsu SPARC64-VI extends this to 46 bits. Adjust the TTE masks to take this into account and adjust some locore code that truncated physical addresses to 41 bits (fixing a potential bug for UltraSPARC III/IV too). While there, fix the locore code for UltraSPARC Architecture 2007 CPUs, which may support up to 56 bits of physical address space.
Diffstat (limited to 'sys/arch/sparc64/include')
-rw-r--r--sys/arch/sparc64/include/pte.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/arch/sparc64/include/pte.h b/sys/arch/sparc64/include/pte.h
index 9d453fafd54..bcc04d693ef 100644
--- a/sys/arch/sparc64/include/pte.h
+++ b/sys/arch/sparc64/include/pte.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: pte.h,v 1.11 2008/04/20 09:18:52 kettenis Exp $ */
+/* $OpenBSD: pte.h,v 1.12 2008/07/10 09:29:33 kettenis Exp $ */
/* $NetBSD: pte.h,v 1.7 2001/07/31 06:55:46 eeh Exp $ */
/*
@@ -168,7 +168,7 @@ void smp_tlb_flush_ctx(int);
#define SUN4U_TLB_IE 0x0800000000000000LL
#define SUN4U_TLB_SOFT2_MASK 0x07fc000000000000LL
#define SUN4U_TLB_RESERVED_MASK 0x0003f80000000000LL
-#define SUN4U_TLB_PA_MASK 0x000007ffffffe000LL
+#define SUN4U_TLB_PA_MASK 0x00007fffffffe000LL
#define SUN4U_TLB_SOFT_MASK 0x0000000000001f80LL
/* S/W bits */
#define SUN4U_TLB_ACCESS 0x0000000000000200LL