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authorMark Kettenis <kettenis@cvs.openbsd.org>2008-03-08 19:15:57 +0000
committerMark Kettenis <kettenis@cvs.openbsd.org>2008-03-08 19:15:57 +0000
commitcd9a04c090b3fbea3d3ebe6553ecb7b07f93a803 (patch)
treeddd84069fb7c18d1b058d583a6951a54f9aae44c /sys/arch/sparc64
parent21642aeb1b060a20071ffb86cee35d04f6cfb940 (diff)
UltraSPARC Hypervisor interfaces for sun4v.
Diffstat (limited to 'sys/arch/sparc64')
-rw-r--r--sys/arch/sparc64/include/hypervisor.h167
-rw-r--r--sys/arch/sparc64/sparc64/hvcall.S322
2 files changed, 489 insertions, 0 deletions
diff --git a/sys/arch/sparc64/include/hypervisor.h b/sys/arch/sparc64/include/hypervisor.h
new file mode 100644
index 00000000000..eacf6f2afad
--- /dev/null
+++ b/sys/arch/sparc64/include/hypervisor.h
@@ -0,0 +1,167 @@
+/* $OpenBSD: hypervisor.h,v 1.1 2008/03/08 19:15:56 kettenis Exp $ */
+
+/*
+ * Copyright (c) 2008 Mark Kettenis
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * UltraSPARC Hypervisor API.
+ */
+
+/*
+ * API versioning
+ */
+
+int64_t hv_api_get_version(uint64_t api_group,
+ uint64_t *major_number, uint64_t *minor_number);
+
+/*
+ * Domain services
+ */
+
+int64_t hv_mach_set_soft_state(uint64_t software_state,
+ paddr_t software_description_ptr);
+
+#define SIS_NORMAL 0x1
+#define SIS_TRANSITION 0x2
+
+/*
+ * CPU services
+ */
+
+int64_t hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries);
+
+#define CPU_MONDO_QUEUE 0x3c
+#define DEVICE_MONDO_QUEUE 0x3d
+
+int64_t hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data);
+int64_t hv_cpu_myid(uint64_t *cpuid);
+
+/*
+ * MMU services
+ */
+
+int64_t hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags);
+int64_t hv_mmu_demap_ctx(uint64_t context, uint64_t flags);
+int64_t hv_mmu_demap_all(uint64_t flags);
+int64_t hv_mmu_map_perm_addr(vaddr_t vaddr, uint64_t tte, uint64_t flags);
+int64_t hv_mmu_unmap_perm_addr(vaddr_t vaddr, uint64_t flags);
+int64_t hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte,
+ uint64_t flags);
+int64_t hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags);
+
+#define MAP_DTLB 0x1
+#define MAP_ITLB 0x2
+
+struct tsb_desc {
+ uint16_t td_idxpgsz;
+ uint16_t td_assoc;
+ uint32_t td_size;
+ uint32_t td_ctxidx;
+ uint32_t td_pgsz;
+ paddr_t td_pa;
+ uint64_t td_reserved;
+};
+
+int64_t hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr);
+int64_t hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr);
+
+/*
+ * Cache and memory services
+ */
+
+int64_t hv_mem_scrub(paddr_t raddr, psize_t length);
+int64_t hv_mem_sync(paddr_t raddr, psize_t length);
+
+/*
+ * Device interrupt services
+ */
+
+int64_t hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino,
+ uint64_t *sysino);
+int64_t hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled);
+int64_t hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled);
+int64_t hv_intr_getstate(uint64_t sysino, uint64_t *intr_state);
+int64_t hv_intr_setstate(uint64_t sysino, uint64_t intr_state);
+int64_t hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid);
+int64_t hv_intr_settarget(uint64_t sysino, uint64_t cpuid);
+
+#define INTR_DISABLED 0
+#define INTR_ENABLED 1
+
+#define INTR_IDLE 0
+#define INTR_RECEIVED 1
+#define INTR_DELIVERED 2
+
+/*
+ * Time of day services
+ */
+
+int64_t hv_tod_get(uint64_t *tod);
+int64_t hv_tod_set(uint64_t tod);
+
+/*
+ * Console services
+ */
+
+int64_t hv_cons_getchar(int64_t *ch);
+int64_t hv_cons_putchar(int64_t ch);
+int64_t hv_api_putchar(int64_t ch);
+
+/*
+ * PCI I/O services
+ */
+
+int64_t hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid,
+ uint64_t nttes, uint64_t io_attributes, paddr_t io_page_list_p,
+ uint64_t *nttes_mapped);
+int64_t hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid,
+ uint64_t nttes, uint64_t *nttes_demapped);
+int64_t hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid,
+ uint64_t *io_attributes, paddr_t *r_addr);
+int64_t hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr,
+ uint64_t io_attributes, uint64_t *io_addr);
+
+int64_t hv_pci_config_get(uint64_t devhandle, uint64_t pci_device,
+ uint64_t pci_config_offset, uint64_t size,
+ uint64_t *error_flag, uint64_t *data);
+int64_t hv_pci_config_put(uint64_t devhandle, uint64_t pci_device,
+ uint64_t pci_config_offset, uint64_t size, uint64_t data,
+ uint64_t *error_flag);
+
+#define PCI_MAP_ATTR_READ 0x01 /* From memory */
+#define PCI_MAP_ATTR_WRITE 0x02 /* To memory */
+
+/*
+ * Error codes
+ */
+
+#define H_EOK 0
+#define H_ENOCPU 1
+#define H_ENORADDR 2
+#define H_ENOINTR 3
+#define H_EBADPGSZ 4
+#define H_EBADTSB 5
+#define H_EINVAL 6
+#define H_EBADTRAP 7
+#define H_EBADALIGN 8
+#define H_EWOULDBLOCK 9
+#define H_ENOACCESS 10
+#define H_EIO 11
+#define H_ECPUERROR 12
+#define H_ENOTSUPPORTED 13
+#define H_ENOMAP 14
+#define H_ETOOMANY 15
+#define H_ECHANNEL 16
diff --git a/sys/arch/sparc64/sparc64/hvcall.S b/sys/arch/sparc64/sparc64/hvcall.S
new file mode 100644
index 00000000000..ff19183db57
--- /dev/null
+++ b/sys/arch/sparc64/sparc64/hvcall.S
@@ -0,0 +1,322 @@
+/* $OpenBSD: hvcall.S,v 1.1 2008/03/08 19:15:56 kettenis Exp $ */
+
+/*
+ * Copyright (c) 2008 Mark Kettenis
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include "assym.h"
+#include <machine/asm.h>
+
+#define FAST_TRAP 0x80
+#define MMU_MAP_ADDR 0x83
+#define MMU_UNMAP_ADDR 0x84
+#define CORE_TRAP 0xff
+
+#define MACH_EXIT 0x00
+#define MACH_DESC 0x01
+#define MACH_SIR 0x02
+#define MACH_SET_SOFT_STATE 0x03
+#define MACH_GET_SOFT_STATE 0x04
+#define MACH_SET_WATCHDOG 0x05
+
+#define CPU_START 0x10
+#define CPU_STOP 0x11
+#define CPU_YIELD 0x12
+#define CPU_QCONF 0x14
+#define CPU_QINFO 0x15
+#define CPU_MYID 0x16
+#define CPU_STATE 0x17
+#define CPU_SET_RTBA 0x18
+#define CPU_GET_RTBA 0x19
+
+#define MMU_TSB_CTX0 0x20
+#define MMU_TSB_CTXNON0 0x21
+#define MMU_DEMAP_PAGE 0x22
+#define MMU_DEMAP_CTX 0x23
+#define MMU_DEMAP_ALL 0x24
+#define MMU_MAP_PERM_ADDR 0x25
+#define MMU_FAULT_AREA_CONF 0x26
+#define MMU_ENABLE 0x27
+#define MMU_UNMAP_PERM_ADDR 0x28
+#define MMU_TSB_CTX0_INFO 0x29
+#define MMU_TSB_CTXNON0_INFO 0x2a
+#define MMU_FAULT_AREA_INFO 0x2b
+
+#define MEM_SCRUB 0x30
+#define MEM_SYNC 0x31
+
+#define CPU_MONDO_SEND 0x42
+
+#define TOD_GET 0x50
+#define TOD_SET 0x51
+
+#define CONS_GETCHAR 0x60
+#define CONS_PUTCHAR 0x61
+
+#define INTR_DEVINO2SYSINO 0xa0
+#define INTR_GETENABLED 0xa1
+#define INTR_SETENABLED 0xa2
+#define INTR_GETSTATE 0xa3
+#define INTR_SETSTATE 0xa4
+#define INTR_GETTARGET 0xa5
+#define INTR_SETTARGET 0xa6
+
+#define PCI_IOMMU_MAP 0xb0
+#define PCI_IOMMU_DEMAP 0xb1
+#define PCI_IOMMU_GETMAP 0xb2
+#define PCI_IOMMU_GETBYPASS 0xb3
+#define PCI_CONFIG_GET 0xb4
+#define PCI_CONFIG_PUT 0xb5
+
+#define API_SET_VERSION 0x00
+#define API_PUTCHAR 0x01
+#define API_EXIT 0x02
+#define API_GET_VERSION 0x03
+
+
+ENTRY(hv_api_putchar)
+ mov API_PUTCHAR, %o5
+ ta CORE_TRAP
+ retl
+ nop
+
+ENTRY(hv_api_get_version)
+ mov %o2, %o4
+ mov %o1, %o3
+ mov API_GET_VERSION, %o5
+ ta CORE_TRAP
+ stx %o1, [%o3]
+ retl
+ stx %o2, [%o4]
+
+ENTRY(hv_mach_set_soft_state)
+ mov MACH_SET_SOFT_STATE, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_cpu_qconf)
+ mov CPU_QCONF, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_cpu_mondo_send)
+ mov CPU_MONDO_SEND, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_cpu_myid)
+ mov %o0, %o2
+ mov CPU_MYID, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o2]
+
+ENTRY(hv_mmu_tsb_ctx0)
+ mov MMU_TSB_CTX0, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mmu_tsb_ctxnon0)
+ mov MMU_TSB_CTXNON0, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mmu_demap_page)
+ mov %o2, %o4
+ mov %o1, %o3
+ mov %o0, %o2
+ clr %o1
+ clr %o0
+ mov MMU_DEMAP_PAGE, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mmu_demap_ctx)
+ mov %o1, %o3
+ mov %o0, %o2
+ clr %o1
+ clr %o0
+ mov MMU_DEMAP_CTX, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mmu_demap_all)
+ mov %o1, %o3
+ mov %o0, %o2
+ clr %o1
+ clr %o0
+ mov MMU_DEMAP_CTX, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mmu_map_perm_addr)
+ mov %o2, %o3
+ mov %o1, %o2
+ clr %o1
+ mov MMU_MAP_PERM_ADDR, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mmu_unmap_perm_addr)
+ mov %o1, %o2
+ clr %o1
+ mov MMU_UNMAP_PERM_ADDR, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mmu_map_addr)
+ ta MMU_MAP_ADDR
+ retl
+ nop
+
+ENTRY(hv_mmu_unmap_addr)
+ ta MMU_UNMAP_ADDR
+ retl
+ nop
+
+ENTRY(hv_mem_scrub)
+ mov MEM_SCRUB, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_mem_sync)
+ mov MEM_SYNC, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_tod_get)
+ mov %o0, %o2
+ mov TOD_GET, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o2]
+
+ENTRY(hv_tod_set)
+ mov TOD_SET, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_cons_getchar)
+ mov %o0, %o2
+ mov CONS_GETCHAR, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o2]
+
+ENTRY(hv_cons_putchar)
+ mov CONS_PUTCHAR, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_intr_devino_to_sysino)
+ mov INTR_DEVINO2SYSINO, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o2]
+
+ENTRY(hv_intr_getenabled)
+ mov %o1, %o2
+ mov INTR_GETENABLED, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o2]
+
+ENTRY(hv_intr_setenabled)
+ mov INTR_SETENABLED, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_intr_getstate)
+ mov %o1, %o2
+ mov INTR_GETSTATE, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o2]
+
+ENTRY(hv_intr_setstate)
+ mov INTR_SETSTATE, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_intr_gettarget)
+ mov %o1, %o2
+ mov INTR_GETTARGET, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o2]
+
+ENTRY(hv_intr_settarget)
+ mov INTR_SETTARGET, %o5
+ ta FAST_TRAP
+ retl
+ nop
+
+ENTRY(hv_pci_iommu_map)
+ mov %o5, %g5
+ mov PCI_IOMMU_MAP, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%g5]
+
+ENTRY(hv_pci_iommu_demap)
+ mov PCI_IOMMU_DEMAP, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o3]
+
+ENTRY(hv_pci_iommu_getmap)
+ mov %o2, %o4
+ mov PCI_IOMMU_GETMAP, %o5
+ ta FAST_TRAP
+ stx %o1, [%o4]
+ retl
+ stx %o2, [%o3]
+
+ENTRY(hv_pci_iommu_getbypass)
+ mov PCI_IOMMU_GETBYPASS, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%o3]
+
+ENTRY(hv_pci_config_get)
+ mov %o5, %g5
+ mov PCI_CONFIG_GET, %o5
+ ta FAST_TRAP
+ stx %o1, [%o4]
+ retl
+ stx %o2, [%g5]
+
+ENTRY(hv_pci_config_put)
+ mov %o5, %g5
+ mov PCI_CONFIG_PUT, %o5
+ ta FAST_TRAP
+ retl
+ stx %o1, [%g5]