Get all of the bit definitions from ad1848reg, apcdmareg, and cs4231reg

headers.

2 files changed, 151 insertions, 536 deletions

diff --git a/sys/arch/sparc/dev/cs4231.c b/sys/arch/sparc/dev/cs4231.c
index 51a8c8e9b64..a5aa59e71fc 100644
--- a/sys/arch/sparc/dev/cs4231.c
+++ b/sys/arch/sparc/dev/cs4231.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cs4231.c,v 1.8 2002/01/11 16:51:14 jason Exp $	*/
+/*	$OpenBSD: cs4231.c,v 1.9 2002/01/11 22:12:18 jason Exp $	*/
 
 /*
  * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
@@ -56,6 +56,9 @@
 #include <sys/audioio.h>
 #include <dev/audio_if.h>
 #include <dev/auconv.h>
+#include <dev/ic/apcdmareg.h>
+#include <dev/ic/ad1848reg.h>
+#include <dev/ic/cs4231reg.h>
 #include <sparc/dev/cs4231reg.h>
 #include <sparc/dev/cs4231var.h>
 
@@ -100,6 +103,13 @@
 #define	DPRINTF(x)
 #endif
 
+/* Sun uses these pins in pin control register as GPIO */
+#define	CS_PC_LINEMUTE		XCTL0_ENABLE	/* mute line */
+#define	CS_PC_HDPHMUTE		XCTL1_ENABLE	/* mute headphone */
+
+/* cs4231 playback interrupt */
+#define CS_AFS_PI		0x10		/* playback interrupt */
+
 int	cs4231_match	__P((struct device *, void *, void *));
 void	cs4231_attach	__P((struct device *, struct device *, void *));
 int	cs4231_intr	__P((void *));
@@ -259,26 +269,26 @@ cs4231_intr(v)
 	csr = regs->dma_csr;
 	regs->dma_csr = csr;
 
-	if ((csr & CS_DMACSR_EIE) && (csr & CS_DMACSR_EI)) {
+	if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) {
 		printf("%s: error interrupt\n", sc->sc_dev.dv_xname);
 		r = 1;
 	}
 
-	if ((csr & CS_DMACSR_PIE) && (csr & CS_DMACSR_PI)) {
+	if ((csr & APC_CSR_PIE) && (csr & APC_CSR_PI)) {
 		/* playback interrupt */
 		r = 1;
 	}
 
-	if ((csr & CS_DMACSR_GIE) && (csr & CS_DMACSR_GI)) {
+	if ((csr & APC_CSR_GIE) && (csr & APC_CSR_GI)) {
 		/* general interrupt */
 		status = regs->status;
-		if (status & (CS_STATUS_INT | CS_STATUS_SER)) {
-			regs->iar = CS_IAR_AFS;
+		if (status & (INTERRUPT_STATUS | SAMPLE_ERROR)) {
+			regs->iar = CS_IRQ_STATUS;
 			reg = regs->idr;
 			if (reg & CS_AFS_PI) {
-				regs->iar = CS_IAR_PBLB;
+				regs->iar = SP_LOWER_BASE_COUNT;
 				regs->idr = 0xff;
-				regs->iar = CS_IAR_PBUB;
+				regs->iar = SP_UPPER_BASE_COUNT;
 				regs->idr = 0xff;
 			}
 			regs->status = 0;
@@ -286,7 +296,7 @@ cs4231_intr(v)
 		r = 1;
 	}
 
-	if ((csr & CS_DMACSR_PMIE) && (csr & CS_DMACSR_PMI)) {
+	if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) {
 		u_int32_t nextaddr, togo;
 
 		p = sc->sc_nowplaying;
@@ -309,7 +319,7 @@ cs4231_intr(v)
 	}
 
 #if 0
-	if (csr & CS_DMACSR_CI) {
+	if (csr & APC_CSR_CI) {
 		if (sc->sc_rintr != NULL) {
 			r = 1;
 			(*sc->sc_rintr)(sc->sc_rarg);
@@ -328,23 +338,23 @@ cs4231_mute_monitor(sc, mute)
 	struct cs4231_regs *regs = sc->sc_regs;
 
 	if (mute) {
-		regs->iar = CS_IAR_LDACOUT;		/* left dac */
-		regs->idr |= CS_LDACOUT_LDM;
-		regs->iar = CS_IAR_RDACOUT;		/* right dac */
-		regs->idr |= CS_RDACOUT_RDM;
+		regs->iar = SP_LEFT_OUTPUT_CONTROL;	/* left dac */
+		regs->idr |= OUTPUT_MUTE;
+		regs->iar = SP_RIGHT_OUTPUT_CONTROL;	/* right dac */
+		regs->idr |= OUTPUT_MUTE;
 #if 0
-		regs->iar = CS_IAR_MONO;		/* mono */
-		regs->idr |= CS_MONO_MOM;
+		regs->iar = CS_MONO_IO_CONTROL;		/* mono */
+		regs->idr |= MONO_OUTPUT_MUTE;
 #endif
 	}
 	else {
-		regs->iar = CS_IAR_LDACOUT;		/* left dac */
-		regs->idr &= ~CS_LDACOUT_LDM;
-		regs->iar = CS_IAR_RDACOUT;		/* right dac */
-		regs->idr &= ~CS_RDACOUT_RDM;
+		regs->iar = SP_LEFT_OUTPUT_CONTROL;	/* left dac */
+		regs->idr &= ~OUTPUT_MUTE;
+		regs->iar = SP_RIGHT_OUTPUT_CONTROL;	/* right dac */
+		regs->idr &= ~OUTPUT_MUTE;
 #if 0
-		regs->iar = CS_IAR_MONO;		/* mono */
-		regs->idr &= ~CS_MONO_MOM;
+		regs->iar = CS_MONO_IO_CONTROL;		/* mono */
+		regs->idr &= ~MONO_OUTPUT_MUTE;
 #endif
 	}
 }
@@ -366,21 +376,21 @@ cs4231_set_speed(sc, argp)
 	u_long arg = *argp;
 
 	static speed_struct speed_table[] = {
-		{5510,	(0 << 1) | CS_FSPB_C2SL_XTAL2},
-		{5510,	(0 << 1) | CS_FSPB_C2SL_XTAL2},
-		{6620,	(7 << 1) | CS_FSPB_C2SL_XTAL2},
-		{8000,	(0 << 1) | CS_FSPB_C2SL_XTAL1},
-		{9600,	(7 << 1) | CS_FSPB_C2SL_XTAL1},
-		{11025,	(1 << 1) | CS_FSPB_C2SL_XTAL2},
-		{16000,	(1 << 1) | CS_FSPB_C2SL_XTAL1},
-		{18900,	(2 << 1) | CS_FSPB_C2SL_XTAL2},
-		{22050,	(3 << 1) | CS_FSPB_C2SL_XTAL2},
-		{27420,	(2 << 1) | CS_FSPB_C2SL_XTAL1},
-		{32000,	(3 << 1) | CS_FSPB_C2SL_XTAL1},
-		{33075,	(6 << 1) | CS_FSPB_C2SL_XTAL2},
-		{33075,	(4 << 1) | CS_FSPB_C2SL_XTAL2},
-		{44100,	(5 << 1) | CS_FSPB_C2SL_XTAL2},
-		{48000,	(6 << 1) | CS_FSPB_C2SL_XTAL1},
+		{5510,	(0 << 1) | CLOCK_XTAL2},
+		{5510,	(0 << 1) | CLOCK_XTAL2},
+		{6620,	(7 << 1) | CLOCK_XTAL2},
+		{8000,	(0 << 1) | CLOCK_XTAL1},
+		{9600,	(7 << 1) | CLOCK_XTAL1},
+		{11025,	(1 << 1) | CLOCK_XTAL2},
+		{16000,	(1 << 1) | CLOCK_XTAL1},
+		{18900,	(2 << 1) | CLOCK_XTAL2},
+		{22050,	(3 << 1) | CLOCK_XTAL2},
+		{27420,	(2 << 1) | CLOCK_XTAL1},
+		{32000,	(3 << 1) | CLOCK_XTAL1},
+		{33075,	(6 << 1) | CLOCK_XTAL2},
+		{33075,	(4 << 1) | CLOCK_XTAL2},
+		{44100,	(5 << 1) | CLOCK_XTAL2},
+		{48000,	(6 << 1) | CLOCK_XTAL1},
 	};
 
 	int i, n, selected = -1;
@@ -428,18 +438,18 @@ cs4231_wait(sc)
 
 	DELAY(100);
 
-	regs->iar = ~(CS_IAR_MCE);
+	regs->iar = ~(MODE_CHANGE_ENABLE);
 	tries = CS_TIMEOUT;
-	while (regs->iar == CS_IAR_INIT && tries--) {
+	while (regs->iar == SP_IN_INIT && tries--) {
 		DELAY(100);
 	}
 	if (!tries)
 		printf("%s: waited too long to reset iar\n",
 		    sc->sc_dev.dv_xname);
 
-	regs->iar = CS_IAR_ERRINIT;
+	regs->iar = SP_TEST_AND_INIT;
 	tries = CS_TIMEOUT;
-	while (regs->idr == CS_ERRINIT_ACI && tries--) {
+	while (regs->idr == AUTO_CAL_IN_PROG && tries--) {
 		DELAY(100);
 	}
 	if (!tries)
@@ -468,54 +478,36 @@ cs4231_open(addr, flags)
 	sc->sc_pintr = 0;
 	sc->sc_parg = 0;
 
-	regs->dma_csr = CS_DMACSR_RESET;
+	regs->dma_csr = APC_CSR_RESET;
 	DELAY(10);
 	regs->dma_csr = 0;
 	DELAY(10);
-	regs->dma_csr |= CS_DMACSR_CODEC_RESET;
+	regs->dma_csr |= APC_CSR_CODEC_RESET;
 
 	DELAY(20);
 
-	regs->dma_csr &= ~(CS_DMACSR_CODEC_RESET);
-	regs->iar |= CS_IAR_MCE;
+	regs->dma_csr &= ~(APC_CSR_CODEC_RESET);
+	regs->iar |= MODE_CHANGE_ENABLE;
 
 	cs4231_wait(sc);
 
-	regs->iar = CS_IAR_MCE | CS_IAR_MODEID;
-	regs->idr = CS_MODEID_MODE2;
-
-	regs->iar = CS_IAR_VID;
-	if ((regs->idr & CS_VID_CHIP_MASK) == CS_VID_CHIP_CS4231) {
-		switch (regs->idr & CS_VID_VER_MASK) {
-		case CS_VID_VER_CS4231A:
-		case CS_VID_VER_CS4231:
-		case CS_VID_VER_CS4232:
-			break;
-		default:
-			printf("%s: unknown CS version: %d\n",
-			    sc->sc_dev.dv_xname, regs->idr & CS_VID_VER_MASK);
-		}
-	}
-	else {
-		printf("%s: unknown CS chip/version: %d/%d\n",
-		    sc->sc_dev.dv_xname, regs->idr & CS_VID_CHIP_MASK,
-		    regs->idr & CS_VID_VER_MASK);
-	}
+	regs->iar = MODE_CHANGE_ENABLE | SP_MISC_INFO;
+	regs->idr = MODE2;
 
 	/* XXX TODO: setup some defaults */
 
-	regs->iar = ~(CS_IAR_MCE);
+	regs->iar = ~(MODE_CHANGE_ENABLE);
 	cs4231_wait(sc);
 
-	regs->iar = CS_IAR_PC;
-	regs->idr |= CS_PC_IEN;
+	regs->iar = SP_PIN_CONTROL;
+	regs->idr |= INTERRUPT_ENABLE;
 
-	regs->iar = CS_IAR_MCE | CS_IAR_IC;
+	regs->iar = MODE_CHANGE_ENABLE | SP_INTERFACE_CONFIG;
 	reg = regs->idr;
-	regs->iar = CS_IAR_MCE | CS_IAR_IC;
-	regs->idr = reg & ~(CS_IC_CAL_CONV);
+	regs->iar = MODE_CHANGE_ENABLE | SP_INTERFACE_CONFIG;
+	regs->idr = reg & ~(AUTO_CAL_ENABLE);
 
-	regs->iar = ~(CS_IAR_MCE);
+	regs->iar = ~(MODE_CHANGE_ENABLE);
 	cs4231_wait(sc);
 
 	cs4231_setup_output(sc);
@@ -528,40 +520,40 @@ cs4231_setup_output(sc)
 {
 	struct cs4231_regs *regs = sc->sc_regs;
 
-	regs->iar = CS_IAR_PC;
+	regs->iar = SP_PIN_CONTROL;
 	regs->idr |= CS_PC_HDPHMUTE | CS_PC_LINEMUTE;
-	regs->iar = CS_IAR_MONO;
-	regs->idr |= CS_MONO_MOM;
+	regs->iar = CS_MONO_IO_CONTROL;
+	regs->idr |= MONO_OUTPUT_MUTE;
 
 	switch (sc->sc_out_port) {
 	case CSPORT_HEADPHONE:
 		if (sc->sc_mute[CSPORT_SPEAKER]) {
-			regs->iar = CS_IAR_PC;
+			regs->iar = SP_PIN_CONTROL;
 			regs->idr &= ~CS_PC_HDPHMUTE;
 		}
 		break;
 	case CSPORT_SPEAKER:
 		if (sc->sc_mute[CSPORT_SPEAKER]) {
-			regs->iar = CS_IAR_MONO;
-			regs->idr &= ~CS_MONO_MOM;
+			regs->iar = CS_MONO_IO_CONTROL;
+			regs->idr &= ~MONO_OUTPUT_MUTE;
 		}
 		break;
 	case CSPORT_LINEOUT:
 		if (sc->sc_mute[CSPORT_SPEAKER]) {
-			regs->iar = CS_IAR_PC;
+			regs->iar = SP_PIN_CONTROL;
 			regs->idr &= ~CS_PC_LINEMUTE;
 		}
 		break;
 	}
 
-	regs->iar = CS_IAR_LDACOUT;
-	regs->idr &= ~CS_LDACOUT_LDA_MASK;
+	regs->iar = SP_LEFT_OUTPUT_CONTROL;
+	regs->idr &= ~OUTPUT_ATTEN_BITS;
 	regs->idr |= (~(sc->sc_volume[CSPORT_SPEAKER].left >> 2)) &
-	    CS_LDACOUT_LDA_MASK;
-	regs->iar = CS_IAR_RDACOUT;
-	regs->idr &= ~CS_RDACOUT_RDA_MASK;
+	    OUTPUT_ATTEN_BITS;
+	regs->iar = SP_RIGHT_OUTPUT_CONTROL;
+	regs->idr &= ~OUTPUT_ATTEN_BITS;
 	regs->idr |= (~(sc->sc_volume[CSPORT_SPEAKER].right >> 2)) &
-	    CS_RDACOUT_RDA_MASK;
+	    OUTPUT_ATTEN_BITS;
 }
 
 void
@@ -573,8 +565,8 @@ cs4231_close(addr)
 
 	cs4231_halt_input(sc);
 	cs4231_halt_output(sc);
-	regs->iar = CS_IAR_PC;
-	regs->idr &= ~CS_PC_IEN;
+	regs->iar = SP_PIN_CONTROL;
+	regs->idr &= ~INTERRUPT_ENABLE;
 	sc->sc_open = 0;
 }
 
@@ -682,29 +674,29 @@ cs4231_set_params(addr, setmode, usemode, p, r)
 
 	switch (enc) {
 	case AUDIO_ENCODING_ULAW:
-		bits = CS_CDF_FMT_ULAW >> 5;
+		bits = FMT_ULAW >> 5;
 		break;
 	case AUDIO_ENCODING_ALAW:
-		bits = CS_CDF_FMT_ALAW >> 5;
+		bits = FMT_ALAW >> 5;
 		break;
 	case AUDIO_ENCODING_ADPCM:
-		bits = CS_CDF_FMT_ADPCM >> 5;
+		bits = FMT_ADPCM >> 5;
 		break;
 	case AUDIO_ENCODING_SLINEAR_LE:
 		if (p->precision == 16)
-			bits = CS_CDF_FMT_LINEAR_LE >> 5;
+			bits = FMT_TWOS_COMP >> 5;
 		else
 			return (EINVAL);
 		break;
 	case AUDIO_ENCODING_SLINEAR_BE:
 		if (p->precision == 16)
-			bits = CS_CDF_FMT_LINEAR_BE >> 5;
+			bits = FMT_TWOS_COMP_BE >> 5;
 		else
 			return (EINVAL);
 		break;
 	case AUDIO_ENCODING_ULINEAR_LE:
 		if (p->precision == 8)
-			bits = CS_CDF_FMT_ULINEAR >> 5;
+			bits = FMT_PCM8 >> 5;
 		else
 			return (EINVAL);
 		break;
@@ -756,26 +748,26 @@ cs4231_commit_settings(addr)
 
 	fs = sc->sc_speed_bits | (sc->sc_format_bits << 5);
 	if (sc->sc_channels == 2)
-		fs |= CS_FSPB_SM_STEREO;
+		fs |= FMT_STEREO;
 
-	regs->iar = CS_IAR_MCE | CS_IAR_FSPB;
+	regs->iar = MODE_CHANGE_ENABLE | SP_CLOCK_DATA_FORMAT;
 	regs->idr = fs;
 	x = regs->idr;
 	x = regs->idr;
 	tries = 100000;
-	while (tries-- && regs->idr == CS_IAR_INIT);
+	while (tries-- && regs->idr == SP_IN_INIT);
 	if (tries == 0) {
 		printf("%s: timeout committing fspb\n", sc->sc_dev.dv_xname);
 		splx(s);
 		return (0);
 	}
 
-	regs->iar = CS_IAR_MCE | CS_IAR_CDF;
+	regs->iar = MODE_CHANGE_ENABLE | CS_REC_FORMAT;
 	regs->idr = fs;
 	x = regs->idr;
 	x = regs->idr;
 	tries = 100000;
-	while (tries-- && regs->idr == CS_IAR_INIT);
+	while (tries-- && regs->idr == SP_IN_INIT);
 	if (tries == 0) {
 		printf("%s: timeout committing cdf\n", sc->sc_dev.dv_xname);
 		splx(s);
@@ -800,11 +792,11 @@ cs4231_halt_output(addr)
 	struct cs4231_regs *regs = sc->sc_regs;
 	u_int8_t r;
 
-	regs->dma_csr &= ~(CS_DMACSR_EI | CS_DMACSR_GIE | CS_DMACSR_PIE |
-	    CS_DMACSR_EIE | CS_DMACSR_PDMA_GO | CS_DMACSR_PMIE);
-	regs->iar = CS_IAR_IC;
-	r = regs->idr & (~CS_IC_PEN);
-	regs->iar = CS_IAR_IC;
+	regs->dma_csr &= ~(APC_CSR_EI | APC_CSR_GIE | APC_CSR_PIE |
+	    APC_CSR_EIE | APC_CSR_PDMA_GO | APC_CSR_PMIE);
+	regs->iar = SP_INTERFACE_CONFIG;
+	r = regs->idr & (~PLAYBACK_ENABLE);
+	regs->iar = SP_INTERFACE_CONFIG;
 	regs->idr = r;
 	sc->sc_locked = 0;
 	return (0);
@@ -817,9 +809,9 @@ cs4231_halt_input(addr)
 	struct cs4231_softc *sc = (struct cs4231_softc *)addr;
 	struct cs4231_regs *regs = sc->sc_regs;
 
-	regs->dma_csr = CS_DMACSR_CAPTURE_PAUSE;
-	regs->iar = CS_IAR_IC;
-	regs->idr &= ~CS_IC_CEN;
+	regs->dma_csr = APC_CSR_CAPTURE_PAUSE;
+	regs->iar = SP_INTERFACE_CONFIG;
+	regs->idr &= ~CAPTURE_ENABLE;
 	sc->sc_locked = 0;
 	return (0);
 }
@@ -848,20 +840,20 @@ cs4231_set_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LACIN1;
+			sc->sc_regs->iar = SP_LEFT_AUX1_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] &
-			    CS_LACIN1_GAIN_MASK;
+			    AUX_INPUT_ATTEN_BITS;
 		}
 		else if (cp->un.value.num_channels == 2) {
-			sc->sc_regs->iar = CS_IAR_LACIN1;
+			sc->sc_regs->iar = SP_LEFT_AUX1_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] &
-			    CS_LACIN1_GAIN_MASK;
-			sc->sc_regs->iar = CS_IAR_RACIN1;
+			    AUX_INPUT_ATTEN_BITS;
+			sc->sc_regs->iar = SP_RIGHT_AUX1_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] &
-			    CS_RACIN1_GAIN_MASK;
+			    AUX_INPUT_ATTEN_BITS;
 		} else
 			break;
 		error = 0;
@@ -870,20 +862,20 @@ cs4231_set_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LLI;
+			sc->sc_regs->iar = CS_LEFT_LINE_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] &
-			    CS_LLI_GAIN_MASK;
+			    AUX_INPUT_ATTEN_BITS;
 		}
 		else if (cp->un.value.num_channels == 2) {
-			sc->sc_regs->iar = CS_IAR_LLI;
+			sc->sc_regs->iar = CS_LEFT_LINE_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] &
-			    CS_LLI_GAIN_MASK;
-			sc->sc_regs->iar = CS_IAR_RLI;
+			    AUX_INPUT_ATTEN_BITS;
+			sc->sc_regs->iar = CS_RIGHT_LINE_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] &
-			    CS_RLI_GAIN_MASK;
+			    AUX_INPUT_ATTEN_BITS;
 		} else
 			break;
 		error = 0;
@@ -893,10 +885,10 @@ cs4231_set_port(addr, cp)
 			break;
 		if (cp->un.value.num_channels == 1) {
 #if 0
-			sc->sc_regs->iar = CS_IAR_MONO;
+			sc->sc_regs->iar = CS_MONO_IO_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] &
-			    CS_MONO_MIA_MASK;
+			    MONO_INPUT_ATTEN_BITS;
 #endif
 		} else
 			break;
@@ -906,21 +898,21 @@ cs4231_set_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LACIN2;
+			sc->sc_regs->iar = SP_LEFT_AUX2_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] &
-			    CS_LACIN2_GAIN_MASK;
+			    AUX_INPUT_ATTEN_BITS;
 			error = 0;
 		}
 		else if (cp->un.value.num_channels == 2) {
-			sc->sc_regs->iar = CS_IAR_LACIN2;
+			sc->sc_regs->iar = SP_LEFT_AUX2_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] &
-			    CS_LACIN2_GAIN_MASK;
-			sc->sc_regs->iar = CS_IAR_RACIN2;
+			    AUX_INPUT_ATTEN_BITS;
+			sc->sc_regs->iar = SP_RIGHT_AUX2_CONTROL;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] &
-			    CS_RACIN2_GAIN_MASK;
+			    AUX_INPUT_ATTEN_BITS;
 			error = 0;
 		}
 		else
@@ -930,7 +922,7 @@ cs4231_set_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LOOP;
+			sc->sc_regs->iar = SP_DIGITAL_MIX;
 			sc->sc_regs->idr =
 			    cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] << 2;
 		}
@@ -1033,17 +1025,17 @@ cs4231_get_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LACIN1;
+			sc->sc_regs->iar = SP_LEFT_AUX1_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
-			    sc->sc_regs->idr & CS_LACIN1_GAIN_MASK;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
 		}
 		else if (cp->un.value.num_channels == 2) {
-			sc->sc_regs->iar = CS_IAR_LACIN1;
+			sc->sc_regs->iar = SP_LEFT_AUX1_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
-			    sc->sc_regs->idr & CS_LACIN1_GAIN_MASK;
-			sc->sc_regs->iar = CS_IAR_RACIN1;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
+			sc->sc_regs->iar = SP_RIGHT_AUX1_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
-			    sc->sc_regs->idr & CS_RACIN1_GAIN_MASK;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
 		} else
 			break;
 		error = 0;
@@ -1052,17 +1044,17 @@ cs4231_get_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LLI;
+			sc->sc_regs->iar = CS_LEFT_LINE_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
-			    sc->sc_regs->idr & CS_LLI_GAIN_MASK;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
 		}
 		else if (cp->un.value.num_channels == 2) {
-			sc->sc_regs->iar = CS_IAR_LLI;
+			sc->sc_regs->iar = CS_LEFT_LINE_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
-			    sc->sc_regs->idr & CS_LLI_GAIN_MASK;
-			sc->sc_regs->iar = CS_IAR_RLI;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
+			sc->sc_regs->iar = CS_RIGHT_LINE_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
-			    sc->sc_regs->idr & CS_RLI_GAIN_MASK;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
 		} else
 			break;
 		error = 0;
@@ -1072,9 +1064,9 @@ cs4231_get_port(addr, cp)
 			break;
 		if (cp->un.value.num_channels == 1) {
 #if 0
-			sc->sc_regs->iar = CS_IAR_MONO;
+			sc->sc_regs->iar = CS_MONO_IO_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
-			    sc->sc_regs->idr & CS_MONO_MIA_MASK;
+			    sc->sc_regs->idr & MONO_INPUT_ATTEN_BITS;
 #endif
 		} else
 			break;
@@ -1084,18 +1076,18 @@ cs4231_get_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LACIN2;
+			sc->sc_regs->iar = SP_LEFT_AUX2_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
-			    sc->sc_regs->idr & CS_LACIN2_GAIN_MASK;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
 			error = 0;
 		}
 		else if (cp->un.value.num_channels == 2) {
-			sc->sc_regs->iar = CS_IAR_LACIN2;
+			sc->sc_regs->iar = SP_LEFT_AUX2_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_LEFT] =
-			    sc->sc_regs->idr & CS_LACIN2_GAIN_MASK;
-			sc->sc_regs->iar = CS_IAR_RACIN2;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
+			sc->sc_regs->iar = SP_RIGHT_AUX2_CONTROL;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] =
-			    sc->sc_regs->idr & CS_RACIN2_GAIN_MASK;
+			    sc->sc_regs->idr & AUX_INPUT_ATTEN_BITS;
 			error = 0;
 		}
 		else
@@ -1105,7 +1097,7 @@ cs4231_get_port(addr, cp)
 		if (cp->type != AUDIO_MIXER_VALUE)
 			break;
 		if (cp->un.value.num_channels == 1) {
-			sc->sc_regs->iar = CS_IAR_LOOP;
+			sc->sc_regs->iar = SP_DIGITAL_MIX;
 			cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] =
 			    sc->sc_regs->idr >> 2;
 		}
@@ -1487,18 +1479,18 @@ cs4231_trigger_output(addr, start, end, blksize, intr, arg, param)
 	regs->dma_pnva = (u_int32_t)p->addr_dva;
 	regs->dma_pnc = n;
 
-	if ((csr & CS_DMACSR_PDMA_GO) == 0 || (csr & CS_DMACSR_PPAUSE) != 0) {
-		regs->dma_csr &= ~(CS_DMACSR_PIE | CS_DMACSR_PPAUSE);
-		regs->dma_csr |= CS_DMACSR_EI | CS_DMACSR_GIE |
-				 CS_DMACSR_PIE | CS_DMACSR_EIE |
-				 CS_DMACSR_PMIE | CS_DMACSR_PDMA_GO;
-		regs->iar = CS_IAR_PBLB;
+	if ((csr & APC_CSR_PDMA_GO) == 0 || (csr & APC_CSR_PPAUSE) != 0) {
+		regs->dma_csr &= ~(APC_CSR_PIE | APC_CSR_PPAUSE);
+		regs->dma_csr |= APC_CSR_EI | APC_CSR_GIE |
+				 APC_CSR_PIE | APC_CSR_EIE |
+				 APC_CSR_PMIE | APC_CSR_PDMA_GO;
+		regs->iar = SP_LOWER_BASE_COUNT;
 		regs->idr = 0xff;
-		regs->iar = CS_IAR_PBUB;
+		regs->iar = SP_UPPER_BASE_COUNT;
 		regs->idr = 0xff;
-		regs->iar = CS_IAR_IC;
-		reg = regs->idr | CS_IC_PEN;
-		regs->iar = CS_IAR_IC;
+		regs->iar = SP_INTERFACE_CONFIG;
+		reg = regs->idr | PLAYBACK_ENABLE;
+		regs->iar = SP_INTERFACE_CONFIG;
 		regs->idr = reg;
 	}
 	return (0);
diff --git a/sys/arch/sparc/dev/cs4231reg.h b/sys/arch/sparc/dev/cs4231reg.h
index fe92a339a76..679725176e7 100644
--- a/sys/arch/sparc/dev/cs4231reg.h
+++ b/sys/arch/sparc/dev/cs4231reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cs4231reg.h,v 1.1 1999/06/06 04:48:24 jason Exp $	*/
+/*	$OpenBSD: cs4231reg.h,v 1.2 2002/01/11 22:12:18 jason Exp $	*/
 
 /*
  * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
@@ -60,380 +60,3 @@ struct cs4231_regs {
 	volatile u_int32_t	dma_pnva;	/* playback next virtual addr */
 	volatile u_int32_t	dma_pnc;	/* playback next count */
 };
-
-/*
- * The CS4231 has 4 direct access registers: iar, idr, status, pior
- *
- * iar and idr are used to access either 16 or 32 (mode 2 only) "indirect
- * registers".
- */
-
-/*
- * Direct mapped registers
- */
-
-/* cs4231_reg.iar: index address register */
-#define CS_IAR_IR_MASK		0x1f		/* indirect register mask */
-#define CS_IAR_TRD		0x20		/* transfer request disable */
-#define CS_IAR_MCE		0x40		/* mode change enable */
-#define CS_IAR_INIT		0x80		/* initialization */
-
-/* indirect register numbers (mode1/mode2) */
-#define CS_IAR_LADCIN		0x00		/* left adc input control */
-#define CS_IAR_RADCIN		0x01		/* right adc input control */
-#define CS_IAR_LACIN1		0x02		/* left aux #1 input control */
-#define CS_IAR_RACIN1		0x03		/* right aux #1 input control */
-#define CS_IAR_LACIN2		0x04		/* left aux #2 input control */
-#define CS_IAR_RACIN2		0x05		/* right aux #2 input control */
-#define CS_IAR_LDACOUT		0x06		/* left dac output control */
-#define CS_IAR_RDACOUT		0x07		/* right dac output control */
-#define CS_IAR_FSPB		0x08		/* fs and playback format */
-#define CS_IAR_IC		0x09		/* interface configuration */
-#define CS_IAR_PC		0x0a		/* pin control */
-#define CS_IAR_ERRINIT		0x0b		/* error status & init */
-#define CS_IAR_MODEID		0x0c		/* mode and id */
-#define CS_IAR_LOOP		0x0d		/* loopback control */
-#define CS_IAR_PBUB		0x0e		/* playback upper base */
-#define CS_IAR_PBLB		0x0f		/* playback lower base */
-
-/* indirect register numbers (mode2 only) */
-
-#define CS_IAR_AFE1		0x10		/* alt feature enable I */
-#define CS_IAR_AFE2		0x11		/* alt feature enable II */
-#define CS_IAR_LLI		0x12		/* left line input control */
-#define CS_IAR_RLI		0x13		/* right line input control */
-#define CS_IAR_TLB		0x14		/* timer lower base */
-#define CS_IAR_TUB		0x15		/* timer upper base */
-#define CS_IAR_reserved1	0x16		/* reserved */
-#define CS_IAR_AFE3		0x17		/* alt feature enable III */
-#define CS_IAR_AFS		0x18		/* alt feature status */
-#define CS_IAR_VID		0x19		/* version id */
-#define CS_IAR_MONO		0x1a		/* mono input/output control */
-#define CS_IAR_reserved2	0x1b		/* reserved */
-#define CS_IAR_CDF		0x1c		/* capture data format */
-#define CS_IAR_reserved3	0x1d		/* reserved */
-#define CS_IAR_CUB		0x1e		/* capture upper base */
-#define CS_IAR_CLB		0x1f		/* capture lower base */
-
-/* cs4231_reg.idr: index data register */
-/* Contains the data of the indirect register indexed by the iar */
-
-/* cs4231_reg.status: status register */
-#define CS_STATUS_INT		0x01		/* interrupt status(1=active) */
-#define CS_STATUS_PRDY		0x02		/* playback data ready */
-#define CS_STATUS_PL		0x04		/* playback l/r sample */
-#define CS_STATUS_PU		0x08		/* playback up/lw byte needed */
-#define CS_STATUS_SER		0x10		/* sample error */
-#define CS_STATUS_CRDY		0x20		/* capture data ready */
-#define CS_STATUS_CL		0x40		/* capture l/r sample */
-#define CS_STATUS_CU		0x80		/* capture up/lw byte needed */
-
-/* cs4231_reg.pior: programmed i/o register */
-/* On write, this is the playback data byte */
-/* On read, it is the capture data byte */
-
-/*
- * Indirect Mapped Registers
- */
-
-/* Left ADC Input Control: I0 */
-#define CS_LADCIN_GAIN_MASK	0x0f		/* left adc gain */
-#define CS_LADCIN_reserved	0x10		/* reserved */
-#define CS_LADCIN_LMGE		0x20		/* left mic gain enable */
-#define CS_LADCIN_SRC_MASK	0xc0		/* left adc source select */
-
-#define CS_LADCIN_SRC_LINE	0x00		/* left input src: line */
-#define CS_LADCIN_SRC_AUX	0x40		/* left input src: aux */
-#define CS_LADCIN_SRC_MIC	0x80		/* left input src: mic */
-#define CS_LADCIN_SRC_LOOP	0xc0		/* left input src: loopback */
-
-/* Right ADC Input Control: I1 */
-#define CS_RADCIN_GAIN_MASK	0x0f		/* right adc gain */
-#define CS_RADCIN_reserved	0x10		/* reserved */
-#define CS_RADCIN_LMGE		0x20		/* right mic gain enable */
-#define CS_RADCIN_SRC_MASK	0xc0		/* right adc source select */
-
-#define CS_RADCIN_SRC_LINE	0x00		/* right input src: line */
-#define CS_RADCIN_SRC_AUX	0x40		/* right input src: aux */
-#define CS_RADCIN_SRC_MIC	0x80		/* right input src: mic */
-#define CS_RADCIN_SRC_LOOP	0xc0		/* right input src: loopback */
-
-/* Left Auxiliary #1 Input Control: I2 */
-#define CS_LACIN1_GAIN_MASK	0x1f		/* left aux #1 mix gain */
-#define CS_LACIN1_reserved1	0x20		/* reserved */
-#define CS_LACIN1_reserved2	0x40		/* reserved */
-#define CS_LACIN1_LX1M		0x80		/* left aux #1 mute */
-
-/* Right Auxiliary #1 Input Control: I3 */
-#define CS_RACIN1_GAIN_MASK	0x1f		/* right aux #1 mix gain */
-#define CS_RACIN1_reserved1	0x20		/* reserved */
-#define CS_RACIN1_reserved2	0x40		/* reserved */
-#define CS_RACIN1_RX1M		0x80		/* right aux #1 mute */
-
-/* Left Auxiliary #2 Input Control: I4 */
-#define CS_LACIN2_GAIN_MASK	0x1f		/* left aux #2 mix gain */
-#define CS_LACIN2_reserved1	0x20		/* reserved */
-#define CS_LACIN2_reserved2	0x40		/* reserved */
-#define CS_LACIN2_LX2M		0x80		/* left aux #2 mute */
-
-/* Right Auxiliary #2 Input Control: I5 */
-#define CS_RACIN2_GAIN_MASK	0x1f		/* right aux #2 mix gain */
-#define CS_RACIN2_reserved1	0x20		/* reserved */
-#define CS_RACIN2_reserved2	0x40		/* reserved */
-#define CS_RACIN2_RX2M		0x80		/* right aux #2 mute */
-
-/* Left DAC Output Control: I6 */
-#define CS_LDACOUT_LDA_MASK	0x3f		/* left dac attenuator */
-#define CS_LDACOUT_reserved	0x40		/* reserved */
-#define CS_LDACOUT_LDM		0x80		/* left dac mute */
-
-/* Right DAC Output Control: I7 */
-#define CS_RDACOUT_RDA_MASK	0x3f		/* right dac attenuator */
-#define CS_RDACOUT_reserved	0x40		/* reserved */
-#define CS_RDACOUT_RDM		0x80		/* right dac mute */
-
-/* Fs and Playback Data Format: I8 */
-#define CS_FSPB_C2SL		0x01		/* clock 2 source select */
-#define CS_FSPB_CFS_MASK	0x0e		/* clock frequency div select */
-#define CS_FSPB_SM		0x10		/* stereo/mono select */
-#define CS_FSPB_FMT_MASK	0xe0		/* playback format select */
-
-#define CS_FSPB_C2SL_XTAL1	0x00		/* use 24.576 Mhz crystal */
-#define CS_FSPB_C2SL_XTAL2	0x01		/* use 16.9344 Mhz crystal */
-#define CS_FSPB_SM_MONO		0x00		/* use mono output */
-#define CS_FSPB_SM_STEREO	0x10		/* use stereo output */
-#define CS_FSPB_FMT_ULINEAR	0x00		/* fmt: linear 8bit unsigned */
-#define CS_FSPB_FMT_ULAW	0x20		/* fmt: ulaw, 8bit companded */
-#define CS_FSPB_FMT_LINEAR_LE	0x40		/* fmt: linear 16bit little */
-#define CS_FSPB_FMT_ALAW	0x60		/* fmt: alaw, 8bit companded */
-#define CS_FSPB_FMT_reserved1	0x80		/* fmt: reserved */
-#define CS_FSPB_FMT_ADPCM	0xa0		/* fmt: adpcm 4bit */
-#define CS_FSPB_FMT_LINEAR_BE	0xc0		/* fmt: linear 16bit big */
-#define CS_FSPB_FMT_reserved2	0xe0		/* fmt: reserved */
-
-/* Interface Configuration: I9 */
-#define CS_IC_PEN		0x01		/* playback enable */
-#define CS_IC_CEN		0x02		/* capture enable */
-#define CS_IC_SDC		0x04		/* single dma channel */
-#define CS_IC_CAL_MASK		0x18		/* calibration type mask */
-#define CS_IC_reserved		0x20		/* reserved */
-#define CS_IC_PPIO		0x40		/* playback pio enable */
-#define CS_IC_CPIO		0x80		/* capture pio enable */
-
-#define CS_IC_CAL_NONE		0x00		/* no calibration */
-#define CS_IC_CAL_CONV		0x08		/* converter calibration */
-#define CS_IC_CAL_DAC		0x10		/* dac calibration */
-#define CS_IC_CAL_FULL		0x18		/* full calibration */
-
-/* Pin Control: I10 */
-#define CS_PC_reserved1		0x01		/* reserved */
-#define CS_PC_IEN		0x02		/* interrupt enable */
-#define CS_PC_reserved2		0x04		/* reserved */
-#define CS_PC_DEN		0x08		/* dither enable */
-#define CS_PC_reserved3		0x10		/* reserved */
-#define CS_PC_reserved4		0x20		/* reserved */
-#define CS_PC_XCTL_MASK		0xc0		/* xctl control */
-#define	CS_PC_LINEMUTE		0x40		/* mute line */
-#define	CS_PC_HDPHMUTE		0x80		/* mute headphone */
-#define CS_PC_XCTL0		0x40		/* set xtcl0 to 1 */
-#define CS_PC_XCTL1		0x80		/* set xctl1 to 1 */
-
-/* Error Status and Initialization: I11 */
-#define CS_ERRINIT_ORL_MASK	0x03		/* overrange left detect */
-#define CS_ERRINIT_ORR_MASK	0x0c		/* overrange right detect */
-#define CS_ERRINIT_DRQ		0x10		/* drq status */
-#define CS_ERRINIT_ACI		0x20		/* auto-calibrate in progress */
-#define CS_ERRINIT_PUR		0x40		/* playback underrun */
-#define CS_ERRINIT_COR		0x80		/* capture overrun */
-
-#define CS_ERRINIT_ORL_VLOW	0x00		/* < -1.5 dB from full scale */
-#define CS_ERRINIT_ORL_LOW	0x01		/* -1.5dB < x < 0dB */
-#define CS_ERRINIT_ORL_HIGH	0x02		/* 0dB < x < 1.5dB */
-#define CS_ERRINIT_ORL_VHIGH	0x03		/* > 1.5dB overrange */
-#define CS_ERRINIT_ORR_VLOW	0x00		/* < -1.5 dB from full scale */
-#define CS_ERRINIT_ORR_LOW	0x04		/* -1.5dB < x < 0dB */
-#define CS_ERRINIT_ORR_HIGH	0x08		/* 0dB < x < 1.5dB */
-#define CS_ERRINIT_ORR_VHIGH	0x0c		/* > 1.5dB overrange */
-
-/* Mode and ID: I12 */
-#define CS_MODEID_ID_MASK	0x0f		/* Codec ID */
-#define CS_MODEID_reserved1	0x10		/* reserved */
-#define CS_MODEID_reserved2	0x20		/* reserved */
-#define CS_MODEID_MODE2		0x40		/* enable mode2 operation */
-
-#define CS_MODEID_CS4231	0x0a		/* 1010 == cs4231 */
-
-/* Loopback Control: I13 */
-#define CS_LOOP_LBE		0x01		/* loopback enable */
-#define CS_LOOP_reserved	0x02		/* reserved */
-#define CS_LOOP_LBA_MASK	0xfc		/* loopback attenuation */
-
-/* Playback Upper Base: I14 */
-
-/* Playback Lower Base: I15 */
-
-/* Alternate Feature Enable I: I16 */
-#define CS_AFE1_DACZ		0x01		/* dac zero */
-#define CS_AFE1_SPE		0x02		/* serial port enable */
-#define CS_AFE1_SF_MASK		0x0c		/* serial format mask */
-#define CS_AFE1_PMCE		0x10		/* playback mode change enbl */
-#define CS_AFE1_CMCE		0x20		/* capture mode change enable */
-#define CS_AFE1_TE		0x40		/* timer enable */
-#define CS_AFE1_OLB		0x80		/* output level bit */
-
-#define CS_AFE1_SF_64E		0x00		/* 64 bit enhanced */
-#define CS_AFE1_SF_64		0x04		/* 64 bit */
-#define CS_AFE1_SF_32		0x08		/* 32 bit */
-#define CS_AFE1_SF_reserved	0x0c		/* reserved */
-#define CS_AFE1_OLB_2		0x00		/* full scale 2Vpp (-3dB) */
-#define CS_AFE1_OLB_28		0x80		/* full scale 2.8Vpp (0dB) */
-
-/* Alternate Feature Enable II: I17 */
-#define CS_AFE2_HPF		0x01		/* high pass filter enable */
-#define CS_AFE2_XTALE		0x02		/* crystal enable */
-#define CS_AFE2_APAR		0x04		/* ADPCM pb accumulator reset */
-#define CS_AFE2_reserved	0x08		/* reserved */
-#define CS_AFE2_TEST_MASK	0xf0		/* factory test bits */
-
-/* Left Line Input Control: I18 */
-#define CS_LLI_GAIN_MASK	0x1f		/* left line mix gain mask */
-#define CS_LLI_reserved1	0x20		/* reserved */
-#define CS_LLI_reserved2	0x40		/* reserved */
-#define CS_LLI_MUTE		0x80		/* left line mute */
-
-/* Right Line Input Control: I19 */
-#define CS_RLI_GAIN_MASK	0x1f		/* right line mix gain mask */
-#define CS_RLI_reserved1	0x20		/* reserved */
-#define CS_RLI_reserved2	0x40		/* reserved */
-#define CS_RLI_MUTE		0x80		/* right line mute */
-
-/* Timer Lower Base: I20 */
-
-/* Timer Upper Base: I21 */
-
-/* Reserved: I22 */
-
-/* Alternate Feature Enable III: I23 */
-#define CS_AFE3_ACF		0x01		/* ADPCM capture freeze */
-#define CS_AFE3_reserved	0xfe		/* reserved bits */
-
-/* Alternate Feature Status: I24 */
-#define CS_AFS_PU		0x01		/* playback underrun */
-#define CS_AFS_PO		0x02		/* playback overrun */
-#define CS_AFS_CO		0x04		/* capture underrun */
-#define CS_AFS_CU		0x08		/* capture overrun */
-#define CS_AFS_PI		0x10		/* playback interrupt */
-#define CS_AFS_CI		0x20		/* capture interrupt */
-#define CS_AFS_TI		0x40		/* timer interrupt */
-#define CS_AFS_reserved		0x80		/* reserved */
-
-/* Version ID: I25 */
-#define CS_VID_CHIP_MASK	0x07		/* chip id mask */
-#define CS_VID_VER_MASK		0xe0		/* version number mask */
-
-#define CS_VID_CHIP_CS4231	0x00		/* CS4231 and CS4231A */
-#define CS_VID_VER_CS4231	0x80		/* CS4231 */
-#define CS_VID_VER_CS4232	0x82		/* CS4232 */
-#define CS_VID_VER_CS4231A	0xa0		/* CS4231A */
-
-/* Mono Input & Output Control: I26 */
-#define CS_MONO_MIA_MASK	0x0f		/* mono attenuation mask */
-#define CS_MONO_reserved	0x10		/* reserved */
-#define CS_MONO_MBY		0x20		/* mono bypass */
-#define CS_MONO_MOM		0x40		/* mono output mute */
-#define CS_MONO_MIM		0x80		/* mono input mute */
-
-/* Reserved: I27 */
-
-/* Capture Data Format: I28 */
-#define CS_CDF_reserved		0x0f		/* reserved bits */
-#define CS_CDF_SM		0x10		/* Stereo/mono select */
-#define CS_CDF_FMT_MASK		0xe0		/* capture format mask */
-
-#define CS_CDF_SM_MONO		0x00		/* select mono capture */
-#define CS_CDF_SM_STEREO	0x10		/* select stereo capture */
-#define CS_CDF_FMT_ULINEAR	0x00		/* fmt: linear 8bit unsigned */
-#define CS_CDF_FMT_ULAW		0x20		/* fmt: ulaw, 8bit companded */
-#define CS_CDF_FMT_LINEAR_LE	0x40		/* fmt: linear 16bit little */
-#define CS_CDF_FMT_ALAW		0x60		/* fmt: alaw, 8bit companded */
-#define CS_CDF_FMT_reserved1	0x80		/* fmt: reserved */
-#define CS_CDF_FMT_ADPCM	0xa0		/* fmt: adpcm 4bit */
-#define CS_CDF_FMT_LINEAR_BE	0xc0		/* fmt: linear 16bit big */
-#define CS_CDF_FMT_reserved2	0xe0		/* fmt: reserved */
-
-/* Reserved: I29 */
-
-/* Capture Upper Base: I30 */
-
-/* Capture Lower Base: I31 */
-
-/*
- * APC DMA Register definitions
- */
-#define CS_DMACSR_RESET		0x00000001	/* reset */
-#define CS_DMACSR_CDMA_GO	0x00000004	/* capture dma go */
-#define CS_DMACSR_PDMA_GO	0x00000008	/* playback dma go */
-#define CS_DMACSR_CODEC_RESET	0x00000020	/* codec reset */
-#define CS_DMACSR_CPAUSE	0x00000040	/* capture dma pause */
-#define CS_DMACSR_PPAUSE	0x00000080	/* playback dma pause */
-#define CS_DMACSR_CMIE		0x00000100	/* capture pipe empty enb */
-#define CS_DMACSR_CMI		0x00000200	/* capture pipe empty intr */
-#define CS_DMACSR_CD		0x00000400	/* capture nva dirty */
-#define CS_DMACSR_CM		0x00000800	/* capture data lost */
-#define CS_DMACSR_PMIE		0x00001000	/* pb pipe empty intr enable */
-#define CS_DMACSR_PD		0x00002000	/* pb nva dirty */
-#define CS_DMACSR_PM		0x00004000	/* pb pipe empty */
-#define CS_DMACSR_PMI		0x00008000	/* pb pipe empty interrupt */
-#define CS_DMACSR_EIE		0x00010000	/* error interrupt enable */
-#define CS_DMACSR_CIE		0x00020000	/* capture intr enable */
-#define CS_DMACSR_PIE		0x00040000	/* playback intr enable */
-#define CS_DMACSR_GIE		0x00080000	/* general intr enable */
-#define CS_DMACSR_EI		0x00100000	/* error interrupt */
-#define CS_DMACSR_CI		0x00200000	/* capture interrupt */
-#define CS_DMACSR_PI		0x00400000	/* playback interrupt */
-#define CS_DMACSR_GI		0x00800000	/* general interrupt */
-
-#define CS_DMACSR_PLAY			( \
-		CS_DMACSR_EI		| \
-	 	CS_DMACSR_GIE		| \
-		CS_DMACSR_PIE		| \
-		CS_DMACSR_EIE		| \
-		CS_DMACSR_PDMA_GO	| \
-		CS_DMACSR_PMIE		)
-
-#define CS_DMACSR_CAPTURE		( \
-		CS_DMACSR_EI		| \
-	 	CS_DMACSR_GIE		| \
-		CS_DMACSR_CIE		| \
-		CS_DMACSR_EIE		| \
-		CS_DMACSR_CDMA_GO	)
-
-#define CS_DMACSR_PLAY_PAUSE		(~( \
-		CS_DMACSR_PPAUSE	| \
-		CS_DMACSR_GI		| \
-		CS_DMACSR_PI		| \
-		CS_DMACSR_CI		| \
-		CS_DMACSR_EI		| \
-		CS_DMACSR_PMI		| \
-		CS_DMACSR_PMIE		| \
-		CS_DMACSR_CMI		| \
-		CS_DMACSR_CMIE		) )
-
-#define CS_DMACSR_CAPTURE_PAUSE		(~( \
-		CS_DMACSR_PPAUSE	| \
-		CS_DMACSR_GI		| \
-		CS_DMACSR_PI		| \
-		CS_DMACSR_CI		| \
-		CS_DMACSR_EI		| \
-		CS_DMACSR_PMI		| \
-		CS_DMACSR_PMIE		| \
-		CS_DMACSR_CMI		| \
-		CS_DMACSR_CMIE		) )
-
-#define CS_DMACSR_INTR_MASK		( \
-		CS_DMACSR_GI		| \
-		CS_DMACSR_PI		| \
-		CS_DMACSR_CI		| \
-		CS_DMACSR_EI		| \
-		CS_DMACSR_PMI		| \
-		CS_DMACSR_CMI		)