As a late birthday present, a preliminary port to the Solbourne IDT systems

(S3000, S4000 and S4000DX).

Currently limited to diskless and serial console, and userland has issues.
Things will get better in the near future.

11 files changed, 350 insertions, 26 deletions

diff --git a/sys/arch/sparc/conf/files.sparc b/sys/arch/sparc/conf/files.sparc
index 523a1fcc645..74556fee1f9 100644
--- a/sys/arch/sparc/conf/files.sparc
+++ b/sys/arch/sparc/conf/files.sparc
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.sparc,v 1.63 2005/03/08 20:00:24 tdeval Exp $
+#	$OpenBSD: files.sparc,v 1.64 2005/04/19 21:30:18 miod Exp $
 #	$NetBSD: files.sparc,v 1.44 1997/08/31 21:29:16 pk Exp $
 
 # @(#)files.sparc	8.1 (Berkeley) 7/19/93
@@ -26,7 +26,7 @@ device	vmel {[addr = -1], [level = -1], [vect = -1]}
 attach	vmel at mainbus, vme
 device	vmes {[addr = -1], [level = -1], [vect = -1]}
 attach	vmes at mainbus, vme
-file	arch/sparc/dev/obio.c		obio | vmel | vmes | vme
+file	arch/sparc/dev/obio.c		(obio | vmel | vmes | vme) & !solbourne
 
 device	auxreg
 attach	auxreg at mainbus, obio
@@ -43,7 +43,7 @@ attach	timer at mainbus, obio
 
 device	eeprom
 attach	eeprom at obio
-file	arch/sparc/sparc/clock.c
+file	arch/sparc/sparc/clock.c		!solbourne
 
 device	power
 attach	power at obio
@@ -283,7 +283,7 @@ file	arch/sparc/fpu/fpu_mul.c
 file	arch/sparc/fpu/fpu_sqrt.c
 file	arch/sparc/fpu/fpu_subr.c
 
-file	arch/sparc/sparc/autoconf.c
+file	arch/sparc/sparc/autoconf.c		!solbourne
 file	arch/sparc/sparc/cache.c
 file	arch/sparc/sparc/conf.c
 file	arch/sparc/sparc/emul.c
@@ -291,18 +291,16 @@ file	arch/sparc/sparc/in_cksum.c
 file	arch/sparc/sparc/intr.c
 file	arch/sparc/sparc/kgdb_machdep.c	kgdb
 file	arch/sparc/sparc/locore2.c
-file	arch/sparc/sparc/machdep.c
+file	arch/sparc/sparc/machdep.c		!solbourne
 file	arch/sparc/sparc/process_machdep.c
-file	arch/sparc/sparc/mem.c
-file	arch/sparc/sparc/openprom.c
-file	arch/sparc/sparc/pmap.c
+file	arch/sparc/sparc/mem.c			!solbourne
+file	arch/sparc/sparc/openprom.c		!solbourne
+file	arch/sparc/sparc/pmap.c			!solbourne
 file	arch/sparc/sparc/sys_machdep.c
-file	arch/sparc/sparc/trap.c
-file	arch/sparc/sparc/vm_machdep.c
+file	arch/sparc/sparc/trap.c			!solbourne
+file	arch/sparc/sparc/vm_machdep.c		!solbourne
 file	arch/sparc/sparc/disksubr.c
 
-file	kludge_for_in_proto.c		hy needs-flag
-
 file	arch/sparc/sparc/db_interface.c	ddb | kgdb
 file	arch/sparc/sparc/db_trace.c	ddb
 file	arch/sparc/sparc/db_disasm.c	ddb
diff --git a/sys/arch/sparc/dev/if_le.c b/sys/arch/sparc/dev/if_le.c
index a933b5abc38..f7c7ef6045e 100644
--- a/sys/arch/sparc/dev/if_le.c
+++ b/sys/arch/sparc/dev/if_le.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_le.c,v 1.25 2005/02/27 22:01:04 miod Exp $	*/
+/*	$OpenBSD: if_le.c,v 1.26 2005/04/19 21:30:19 miod Exp $	*/
 /*	$NetBSD: if_le.c,v 1.50 1997/09/09 20:54:48 pk Exp $	*/
 
 /*-
@@ -77,6 +77,12 @@
 #include <sparc/dev/if_lereg.h>
 #include <sparc/dev/if_levar.h>
 
+#ifdef solbourne
+#include <sparc/sparc/asm.h>
+#include <machine/idt.h>
+#include <machine/kap.h>
+#endif
+
 int	lematch(struct device *, void *, void *);
 void	leattach(struct device *, struct device *, void *);
 
@@ -131,6 +137,10 @@ hide void lehwinit(struct am7990_softc *);
 #if defined(SUN4M)
 hide void lenocarrier(struct am7990_softc *);
 #endif
+#if defined(solbourne)
+hide void kap_copytobuf(struct am7990_softc *, void *, int, int);
+hide void kap_copyfrombuf(struct am7990_softc *, void *, int, int);
+#endif
 
 hide void
 lewrcsr(sc, port, val)
@@ -392,6 +402,11 @@ lematch(parent, vcf, aux)
 
 	if (strcmp(cf->cf_driver->cd_name, ra->ra_name))
 		return (0);
+#if defined(solbourne)
+	if (CPU_ISKAP) {
+		return (ca->ca_bustype == BUS_OBIO);
+	}
+#endif
 #if defined(SUN4C) || defined(SUN4M)
 	if (ca->ca_bustype == BUS_SBUS) {
 		if (!sbus_testdma((struct sbus_softc *)parent, ca))
@@ -476,6 +491,27 @@ leattach(parent, self, aux)
 	{
 		u_long laddr;
 
+#if defined(solbourne)
+		if (CPU_ISKAP && ca->ca_bustype == BUS_OBIO) {
+			/*
+			 * Use the fixed buffer allocated in pmap_bootstrap().
+			 * for now, until I get the iCU translation to work...
+			 */
+			extern vaddr_t lance_va;
+
+			laddr = PTW1_TO_PHYS(lance_va);
+			sc->sc_mem = (void *)PHYS_TO_PTW2(laddr);
+
+			/* disable ICU translations for ethernet */
+			sta(ICU_TER, ASI_PHYS_IO,
+			    lda(ICU_TER, ASI_PHYS_IO) & ~TER_ETHERNET);
+
+			/* stash the high 15 bits of the physical address */
+			sta(SE_BASE + 0x18, ASI_PHYS_IO,
+			    laddr & 0xfffe0000);
+		} /* else */
+#endif	/* solbourne */
+#if defined(SUN4) || defined(SUN4C) || defined(SUN4M)
 #if defined(SUN4C) || defined(SUN4M)
 		if (sbuschild && CPU_ISSUN4M)
 			laddr = (u_long)dvma_malloc_space(MEMSIZE,
@@ -484,13 +520,24 @@ leattach(parent, self, aux)
 #endif
 			laddr = (u_long)dvma_malloc(MEMSIZE,
 			     &sc->sc_mem, M_NOWAIT);
+#endif	/* SUN4 || SUN4C || SUN4M */
 #if defined (SUN4M)
 		if ((laddr & 0xffffff) >= (laddr & 0xffffff) + MEMSIZE)
 			panic("if_le: Lance buffer crosses 16MB boundary");
 #endif
-		sc->sc_addr = laddr & 0xffffff;
+#if defined(solbourne)
+		if (CPU_ISKAP && ca->ca_bustype == BUS_OBIO)
+			sc->sc_addr = laddr & 0x01ffff;
+		else
+#endif
+			sc->sc_addr = laddr & 0xffffff;
 		sc->sc_memsize = MEMSIZE;
-		sc->sc_conf3 = LE_C3_BSWP | LE_C3_ACON | LE_C3_BCON;
+#if defined(solbourne)
+		if (CPU_ISKAP && ca->ca_bustype == BUS_OBIO)
+			sc->sc_conf3 = LE_C3_BSWP;
+		else
+#endif
+			sc->sc_conf3 = LE_C3_BSWP | LE_C3_ACON | LE_C3_BCON;
 #if defined(SUN4C) || defined(SUN4M)
 		if (dmachild) {
 			lesc->sc_dma = (struct dma_softc *)parent;
@@ -568,6 +615,17 @@ leattach(parent, self, aux)
 
 	am7990_config(sc);
 
+#if defined(solbourne)
+	if (CPU_ISKAP && ca->ca_bustype == BUS_OBIO) {
+		sc->sc_copytodesc = kap_copytobuf;
+		sc->sc_copyfromdesc = kap_copyfrombuf;
+
+		sc->sc_initaddr = 1 << 23 | (sc->sc_initaddr & 0x01ffff);
+		sc->sc_rmdaddr = 1 << 23 | (sc->sc_rmdaddr & 0x01ffff);
+		sc->sc_tmdaddr = 1 << 23 | (sc->sc_tmdaddr & 0x01ffff);
+	}
+#endif
+
 	lesc->sc_ih.ih_fun = am7990_intr;
 #if defined(SUN4M) /*XXX*/
 	if (CPU_ISSUN4M && lesc->sc_dma)
@@ -579,3 +637,16 @@ leattach(parent, self, aux)
 	/* now initialize DMA */
 	lehwreset(sc);
 }
+
+#if defined(solbourne)
+hide void
+kap_copytobuf(struct am7990_softc *sc, void *to, int boff, int len)
+{
+	return (am7990_copytobuf_contig(sc, to, boff & ~(1 << 23), len));
+}
+hide void
+kap_copyfrombuf(struct am7990_softc *sc, void *from, int boff, int len)
+{
+	return (am7990_copyfrombuf_contig(sc, from, boff & ~(1 << 23), len));
+}
+#endif
diff --git a/sys/arch/sparc/dev/if_lereg.h b/sys/arch/sparc/dev/if_lereg.h
index ce4a71e2895..020d4d025f1 100644
--- a/sys/arch/sparc/dev/if_lereg.h
+++ b/sys/arch/sparc/dev/if_lereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_lereg.h,v 1.5 2003/06/02 23:27:54 millert Exp $	*/
+/*	$OpenBSD: if_lereg.h,v 1.6 2005/04/19 21:30:19 miod Exp $	*/
 /*	$NetBSD: if_lereg.h,v 1.5 1995/12/10 10:15:07 mycroft Exp $ */
 
 /*-
@@ -43,5 +43,8 @@
  */
 struct lereg1 {
 	volatile u_int16_t	ler1_rdp;	/* data port */
+#ifdef solbourne
+	volatile u_char		ler1_pad[6];
+#endif
 	volatile u_int16_t	ler1_rap;	/* register select port */
 };
diff --git a/sys/arch/sparc/dev/zs.c b/sys/arch/sparc/dev/zs.c
index 259e6fb8ce4..233679fe18e 100644
--- a/sys/arch/sparc/dev/zs.c
+++ b/sys/arch/sparc/dev/zs.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: zs.c,v 1.40 2004/09/29 07:35:12 miod Exp $	*/
+/*	$OpenBSD: zs.c,v 1.41 2005/04/19 21:30:19 miod Exp $	*/
 /*	$NetBSD: zs.c,v 1.50 1997/10/18 00:00:40 gwr Exp $	*/
 
 /*-
@@ -75,6 +75,10 @@
 #include <sparc/sparc/auxioreg.h>
 #include <sparc/dev/cons.h>
 
+#ifdef solbourne
+#include <machine/prom.h>
+#endif
+
 #include <uvm/uvm_extern.h>
 
 #include "zskbd.h"
@@ -116,10 +120,18 @@ int zs_major = 12;
 
 /* The layout of this is hardware-dependent (padding, order). */
 struct zschan {
+#if defined(SUN4) || defined(SUN4C) || defined(SUN4M)
 	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
 	u_char		zc_xxx0;
 	volatile u_char	zc_data;	/* data */
 	u_char		zc_xxx1;
+#endif
+#if defined(solbourne)
+	volatile u_char	zc_csr;		/* ctrl,status, and indirect access */
+	u_char		zc_xxx0[7];
+	volatile u_char	zc_data;	/* data */
+	u_char		zc_xxx1[7];
+#endif
 };
 struct zsdevice {
 	/* Yes, they are backwards. */
@@ -225,6 +237,12 @@ zs_match(parent, vcf, aux)
 
 	if (strcmp(cf->cf_driver->cd_name, ra->ra_name))
 		return (0);
+
+#ifdef solbourne
+	if (CPU_ISKAP)
+		return (ca->ca_bustype == BUS_OBIO);
+#endif
+
 	if ((ca->ca_bustype == BUS_MAIN && !CPU_ISSUN4) ||
 	    (ca->ca_bustype == BUS_OBIO && CPU_ISSUN4M))
 		return (getpropint(ra->ra_node, "slave", -2) == cf->cf_unit);
@@ -808,6 +826,8 @@ zscnpollc(dev, on)
 
 /*****************************************************************/
 
+#if defined(SUN4) || defined(SUN4C) || defined(SUN4M)
+
 cons_decl(prom);
 
 /*
@@ -912,6 +932,8 @@ promcnputc(dev, c)
 	splx(s);
 }
 
+#endif	/* SUN4 || SUN4C || SUN4M */
+
 /*****************************************************************/
 
 #if 0
@@ -936,6 +958,7 @@ consinit()
 	int channel, zs_unit;
 	int inSource, outSink;
 
+#if defined(SUN4) || defined(SUN4C) || defined(SUN4M)
 	if (promvec->pv_romvec_vers > 2) {
 		/* We need to probe the PROM device tree */
 		int node,fd;
@@ -1043,8 +1066,34 @@ setup_output:
 		inSource = *promvec->pv_stdin;
 		outSink  = *promvec->pv_stdout;
 	}
+#endif	/* SUN4 || SUN4C || SUN4M */
+#ifdef solbourne
+	if (CPU_ISKAP) {
+		const char *dev;
+
+		inSource = PROMDEV_TTYA;	/* default */
+		dev = prom_getenv(ENV_INPUTDEVICE);
+		if (dev != NULL) {
+			if (strcmp(dev, "ttyb") == 0)
+				inSource = PROMDEV_TTYB;
+			if (strcmp(dev, "keyboard") == 0)
+				inSource = PROMDEV_KBD;
+		}
+
+		outSink = PROMDEV_TTYA;	/* default */
+		dev = prom_getenv(ENV_OUTPUTDEVICE);
+		if (dev != NULL) {
+			if (strcmp(dev, "ttyb") == 0)
+				outSink = PROMDEV_TTYB;
+			if (strcmp(dev, "screen") == 0)
+				outSink = PROMDEV_SCREEN;
+		}
+	}
+#endif
 
+#if defined(SUN4) || defined(SUN4C) || defined(SUN4M)
 setup_console:
+#endif
 
 	if (inSource != outSink) {
 		printf("cninit: mismatched PROM output selector\n");
diff --git a/sys/arch/sparc/sparc/cache.c b/sys/arch/sparc/sparc/cache.c
index b2988d2f5ff..70419ee3fd0 100644
--- a/sys/arch/sparc/sparc/cache.c
+++ b/sys/arch/sparc/sparc/cache.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache.c,v 1.16 2002/03/13 00:24:21 miod Exp $	*/
+/*	$OpenBSD: cache.c,v 1.17 2005/04/19 21:30:20 miod Exp $	*/
 /*	$NetBSD: cache.c,v 1.34 1997/09/26 22:17:23 pk Exp $	*/
 
 /*
@@ -70,6 +70,11 @@
 #include <sparc/sparc/cache.h>
 #include <sparc/sparc/cpuvar.h>
 
+#if defined(solbourne)
+#include <machine/idt.h>
+#include <machine/kap.h>
+#endif
+
 struct cachestats cachestats;
 
 int cache_alias_dist;		/* Cache anti-aliasing constants */
@@ -346,6 +351,7 @@ turbosparc_cache_enable()
 }
 #endif /* defined(SUN4M) */
 
+#if defined(SUN4) || defined(SUN4C)
 /*
  * Flush the current context from the cache.
  *
@@ -536,7 +542,7 @@ sun4_cache_flush(base, len)
 			sun4_vcache_flush_context();
 	}
 }
-
+#endif /* defined(SUN4) || defined(SUN4C) */
 
 #if defined(SUN4M)
 /*
@@ -838,3 +844,59 @@ srmmu_pcache_flush_line(va, pa)
 	sta(va, ASI_IDCACHELFP, 0);
 }
 #endif /* SUN4M */
+
+#if defined(solbourne)
+void
+kap_cache_enable()
+{
+	kap_cache_flush(NULL, 0);
+	sta(0, ASI_ICACHE_INVAL, 0);
+
+	sta(ICU_CONF, ASI_PHYS_IO,
+	    lda(ICU_CONF, ASI_PHYS_IO) & ~CONF_ICACHE_DISABLE);
+	CACHEINFO.c_enabled = 1;
+
+	printf("cache enabled\n");
+}
+
+void
+kap_vcache_flush_context()
+{
+	kap_cache_flush(0, 0);
+	sta(0, ASI_DCACHE_INVAL, 0);
+	sta(0, ASI_ICACHE_INVAL, 0);
+}
+
+void
+kap_vcache_flush_page(va)
+	int va;
+{
+	kap_cache_flush((caddr_t)va, PAGE_SIZE);
+}
+
+void
+kap_cache_flush(base, len)
+	caddr_t base;
+	register u_int len;
+{
+	u_int line;
+	u_int32_t mmcr;
+
+	/*
+	 * Due to the small size of the data cache and the fact that we
+	 * would be flushing 4 bytes by 4 bytes, it is faster to flush
+	 * the whole cache instead.
+	 */
+
+	mmcr = lda(0, ASI_MMCR) & ~(MMCR_DSET0 | MMCR_DSET1);
+	/* flush bank 0 */
+	sta(0, ASI_MMCR, mmcr | MMCR_DSET0);
+	for (line = 0; line < DCACHE_LINE(DCACHE_LINES); line += DCACHE_INCR)
+		(void)lda(line, ASI_DCACHE_FLUSH);
+	/* flush bank 1 */
+	sta(0, ASI_MMCR, mmcr | MMCR_DSET1);
+	for (line = 0; line < DCACHE_LINE(DCACHE_LINES); line += DCACHE_INCR)
+		(void)lda(line, ASI_DCACHE_FLUSH);
+}
+
+#endif	/* solbourne */
diff --git a/sys/arch/sparc/sparc/cache.h b/sys/arch/sparc/sparc/cache.h
index b1caebac505..f74a10e7a77 100644
--- a/sys/arch/sparc/sparc/cache.h
+++ b/sys/arch/sparc/sparc/cache.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache.h,v 1.8 2002/03/15 01:20:04 millert Exp $	*/
+/*	$OpenBSD: cache.h,v 1.9 2005/04/19 21:30:20 miod Exp $	*/
 /*	$NetBSD: cache.h,v 1.16 1997/07/06 21:15:14 pk Exp $ */
 
 /*
@@ -157,6 +157,7 @@ void	hypersparc_cache_enable(void);		/* turn it on */
 void	swift_cache_enable(void);		/* turn it on */
 void	cypress_cache_enable(void);		/* turn it on */
 void	turbosparc_cache_enable(void);		/* turn it on */
+void	kap_cache_enable(void);			/* turn it on */
 
 void	sun4_vcache_flush_context(void);	/* flush current context */
 void	sun4_vcache_flush_region(int);		/* flush region in cur ctx */
@@ -181,6 +182,10 @@ void	viking_cache_flush(caddr_t, u_int);
 void	viking_pcache_flush_line(int, int);
 void	srmmu_pcache_flush_line(int, int);
 
+void	kap_vcache_flush_context(void);		/* flush current context */
+void	kap_vcache_flush_page(int va);		/* flush page in cur ctx */
+void	kap_cache_flush(caddr_t, u_int);	/* flush region */
+
 extern void sparc_noop(void);
 
 #define noop_vcache_flush_context \
diff --git a/sys/arch/sparc/sparc/conf.c b/sys/arch/sparc/sparc/conf.c
index b28d6eb002e..64d57a7d9dd 100644
--- a/sys/arch/sparc/sparc/conf.c
+++ b/sys/arch/sparc/sparc/conf.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: conf.c,v 1.40 2005/03/29 16:26:45 miod Exp $	*/
+/*	$OpenBSD: conf.c,v 1.41 2005/04/19 21:30:20 miod Exp $	*/
 /*	$NetBSD: conf.c,v 1.40 1996/04/11 19:20:03 thorpej Exp $ */
 
 /*
@@ -204,7 +204,11 @@ struct cdevsw	cdevsw[] =
 	cdev_notdef(),			/* 67: was /dev/cgsix */
 	cdev_notdef(),			/* 68 */
 	cdev_gen_init(NAUDIO,audio),	/* 69: /dev/audio */
+#if defined(SUN4) || defined(SUN4C) || defined(SUN4M)
 	cdev_openprom_init(1,openprom),	/* 70: /dev/openprom */
+#else
+	cdev_notdef(),			/* 70 */
+#endif
 	cdev_notdef(),			/* 71 */
 	cdev_notdef(),			/* 72 */
 	cdev_notdef(),			/* 73 */
diff --git a/sys/arch/sparc/sparc/cpu.c b/sys/arch/sparc/sparc/cpu.c
index cfcea2aa661..028b0483efa 100644
--- a/sys/arch/sparc/sparc/cpu.c
+++ b/sys/arch/sparc/sparc/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.39 2003/05/10 21:11:14 deraadt Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.40 2005/04/19 21:30:20 miod Exp $	*/
 /*	$NetBSD: cpu.c,v 1.56 1997/09/15 20:52:36 pk Exp $ */
 
 /*
@@ -73,6 +73,12 @@
 #include <sparc/sparc/cpuvar.h>
 #include <sparc/sparc/memreg.h>
 
+#ifdef solbourne
+#include <machine/idt.h>
+#include <machine/kap.h>
+#include <machine/prom.h>
+#endif
+
 /* The following are used externally (sysctl_hw). */
 char	machine[] = MACHINE;		/* from <machine/param.h> */
 char	machine_arch[] = MACHINE_ARCH;	/* from <machine/param.h> */
@@ -365,10 +371,12 @@ void cpumatch_ms(struct cpu_softc *, struct module_info *, int);
 void cpumatch_viking(struct cpu_softc *, struct module_info *, int);
 void cpumatch_hypersparc(struct cpu_softc *, struct module_info *, int);
 void cpumatch_turbosparc(struct cpu_softc *, struct module_info *, int);
+void cpumatch_kap(struct cpu_softc *, struct module_info *, int);
 
 void getcacheinfo_sun4(struct cpu_softc *, int node);
 void getcacheinfo_sun4c(struct cpu_softc *, int node);
 void getcacheinfo_obp(struct cpu_softc *, int node);
+void getcacheinfo_kap(struct cpu_softc *, int node);
 
 void sun4_hotfix(struct cpu_softc *);
 void viking_hotfix(struct cpu_softc *);
@@ -622,6 +630,112 @@ getcacheinfo_sun4c(sc, node)
 }
 #endif /* SUN4C */
 
+#if defined(solbourne)
+struct module_info module_kap = {
+	CPUTYP_UNKNOWN,
+	VAC_WRITEBACK,
+	cpumatch_kap,
+	getcacheinfo_kap,
+	NULL,
+	0,				/* mmu_enable */
+	kap_cache_enable,
+	0,				/* ncontext is irrelevant here */
+	0,
+	0,
+	kap_cache_flush,
+	kap_vcache_flush_page,
+	noop_vcache_flush_segment,	/* unused */
+	noop_vcache_flush_region,	/* unused */
+	kap_vcache_flush_context,
+	noop_pcache_flush_line,
+	noop_pure_vcache_flush,
+	noop_cache_flush_all,
+	0
+};
+
+void
+cpumatch_kap(sc, mp, node)
+	struct cpu_softc *sc;
+	struct module_info *mp;
+	int	node;
+{
+	extern int timerblurb;
+
+	sc->mmu_npmeg = sc->mmu_ncontext = 0;	/* do not matter for idt */
+
+	/*
+	 * Check for the clock speed in the board diagnostic register.
+	 * While there, knowing that there are only two possible values,
+	 * fill the delay constant.
+	 */
+	if ((lda(GLU_DIAG, ASI_PHYS_IO) >> 24) & GD_36MHZ) {
+		sc->hz = 36000000;
+		timerblurb = 14;	/* about 14.40 */
+	} else {
+		sc->hz = 33000000;
+		timerblurb = 13;	/* about 13.20 */
+	}
+
+	if (node != 0) {
+		sysmodel = getpropint(node, "cpu", 0);
+		switch (sysmodel) {
+		case SYS_S4000:
+			break;
+		case SYS_S4100:
+			/* XXX do something about the L2 cache */
+			break;
+		default:
+			panic("cpumatch_kap: unrecognized sysmodel %x",
+			    sysmodel);
+		}
+	}
+}
+
+void
+getcacheinfo_kap(sc, node)
+	struct cpu_softc *sc;
+	int node;
+{
+	struct cacheinfo *ci = &sc->cacheinfo;
+
+	/*
+	 * The KAP processor has 3KB icache and 2KB dcache.
+	 * It is divided in 3 (icache) or 2 (dcache) banks
+	 * of 256 lines, each line being 4 bytes.
+	 * Both caches are virtually addressed.
+	 */
+
+	ci->ic_linesize = 12;
+	ci->ic_l2linesize = 3;	/* XXX */
+	ci->ic_nlines = DCACHE_LINES;
+	ci->ic_associativity = 1;
+	ci->ic_totalsize =
+	    ci->ic_nlines * ci->ic_linesize * ci->ic_associativity;
+	
+	ci->dc_enabled = 1;
+	ci->dc_linesize = 8;
+	ci->dc_l2linesize = 3;
+	ci->dc_nlines = DCACHE_LINES;
+	ci->dc_associativity = 1;
+	ci->dc_totalsize =
+	    ci->dc_nlines * ci->dc_linesize * ci->dc_associativity;
+
+	ci->c_totalsize = ci->ic_totalsize + ci->dc_totalsize;
+	/* ci->c_enabled */
+	ci->c_hwflush = 0;
+	ci->c_linesize = 8;	/* min */
+	ci->c_l2linesize = 3;	/* min */
+	ci->c_nlines = DCACHE_LINES;
+	ci->c_physical = 0;
+	ci->c_associativity = 1;
+	ci->c_split = 1;
+
+	/* no L2 cache (except on 4100 but we don't handle it yet) */
+	
+	ci->c_vactype = VAC_WRITEBACK;
+}
+#endif
+
 void
 sun4_hotfix(sc)
 	struct cpu_softc *sc;
@@ -1111,6 +1225,10 @@ struct cpu_conf {
 	{ CPU_SUN4M, 4, 4, ANY, ANY, "TI_4_4", &module_viking },
 #endif
 
+#if defined(solbourne)
+	{ CPU_KAP, 5, 0, ANY, ANY, "KAP", &module_kap },
+#endif
+
 	{ ANY, ANY, ANY, ANY, ANY, "Unknown", &module_unknown }
 };
 
diff --git a/sys/arch/sparc/sparc/db_interface.c b/sys/arch/sparc/sparc/db_interface.c
index 333d62225ea..1f843f749ea 100644
--- a/sys/arch/sparc/sparc/db_interface.c
+++ b/sys/arch/sparc/sparc/db_interface.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: db_interface.c,v 1.11 2003/05/13 22:25:33 miod Exp $	*/
+/*	$OpenBSD: db_interface.c,v 1.12 2005/04/19 21:30:20 miod Exp $	*/
 /*	$NetBSD: db_interface.c,v 1.18 1997/09/01 00:16:31 pk Exp $ */
 
 /*
@@ -41,6 +41,7 @@
 
 #include <dev/cons.h>
 
+#include <machine/autoconf.h>
 #include <machine/db_machdep.h>
 
 #include <ddb/db_access.h>
@@ -226,7 +227,7 @@ db_prom_cmd(addr, have_addr, count, modif)
 	db_expr_t count;
 	char *modif;
 {
-	promvec->pv_abort();
+	callrom();
 }
 
 struct db_command sparc_db_command_table[] = {
diff --git a/sys/arch/sparc/sparc/disksubr.c b/sys/arch/sparc/sparc/disksubr.c
index 3c8c54ec865..e10e948260b 100644
--- a/sys/arch/sparc/sparc/disksubr.c
+++ b/sys/arch/sparc/sparc/disksubr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: disksubr.c,v 1.31 2005/03/30 07:52:32 deraadt Exp $	*/
+/*	$OpenBSD: disksubr.c,v 1.32 2005/04/19 21:30:20 miod Exp $	*/
 /*	$NetBSD: disksubr.c,v 1.16 1996/04/28 20:25:59 thorpej Exp $ */
 
 /*
@@ -92,6 +92,7 @@ dk_establish(dk, dev)
 		target = bp->val[0];
 		lun = bp->val[1];
 
+#if defined(SUN4)
 		if (CPU_ISSUN4 && dev->dv_xname[0] == 's' &&
 		    target == 0 && sbsc->sc_link[0][0] == NULL) {
 			/*
@@ -103,9 +104,12 @@ dk_establish(dk, dev)
 			target = 3;	/* remap to 3 */
 			lun = 0;
 		}
+#endif
 
+#if defined(SUN4C)
 		if (CPU_ISSUN4C && dev->dv_xname[0] == 's')
 			target = sd_crazymap(target);
+#endif
 
 		if (sbsc->sc_link[target][lun] != NULL &&
 		    sbsc->sc_link[target][lun]->device_softc == (void *)dev) {
diff --git a/sys/arch/sparc/sparc/intreg.h b/sys/arch/sparc/sparc/intreg.h
index 8a8915d36ec..5ea2f416352 100644
--- a/sys/arch/sparc/sparc/intreg.h
+++ b/sys/arch/sparc/sparc/intreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intreg.h,v 1.6 2003/06/02 23:27:55 millert Exp $	*/
+/*	$OpenBSD: intreg.h,v 1.7 2005/04/19 21:30:20 miod Exp $	*/
 /*	$NetBSD: intreg.h,v 1.6 1997/07/22 20:19:10 pk Exp $ */
 
 /*
@@ -60,6 +60,14 @@
  * be cleared in software.  This is done in locore.s.  The ALLIE bit must
  * be cleared to clear asynchronous memory error (level 15) interrupts.
  */
+#ifdef solbourne
+#define	IE_L14		14
+#define	IE_L10		10
+#define	IE_L8		8
+#define	IE_L6		6
+#define	IE_L4		4
+#define	IE_L1		1
+#else
 #define	IE_L14		0x80	/* enable level 14 (counter 1) interrupts */
 #define	IE_L10		0x20	/* enable level 10 (counter 0) interrupts */
 #define	IE_L8		0x10	/* enable level 8 interrupts */
@@ -67,6 +75,7 @@
 #define	IE_L4		0x04	/* request software level 4 interrupt */
 #define	IE_L1		0x02	/* request software level 1 interrupt */
 #define	IE_ALLIE	0x01	/* enable interrupts */
+#endif
 
 #ifndef _LOCORE
 void	ienab_bis(int bis);	/* set given bits */