update from netbsd

7 files changed, 321 insertions, 21 deletions

diff --git a/sys/arch/vax/include/cpu.h b/sys/arch/vax/include/cpu.h
index b7cdd1855a1..12ce8363e99 100644
--- a/sys/arch/vax/include/cpu.h
+++ b/sys/arch/vax/include/cpu.h
@@ -1,4 +1,4 @@
-/*      $NetBSD: cpu.h,v 1.12 1995/06/05 17:17:57 ragge Exp $      */
+/*      $NetBSD: cpu.h,v 1.13 1995/12/13 18:57:57 ragge Exp $      */
 
 /*
  * Copyright (c) 1994 Ludd, University of Lule}, Sweden
@@ -41,15 +41,16 @@
 #define	cpu_swapout(p)
 
 
-extern volatile int cpunumber;
+extern int cpunumber, cpu_type;
 extern struct cpu_dep cpu_calls[];
 
 struct	cpu_dep {
-	int	(*cpu_loinit)(); /* Locore init before everything else */
+	int	(*cpu_steal_pages)(); /* Pmap init before mm is on */
 	int	(*cpu_clock)();	 /* CPU dependent clock handling */
 	int	(*cpu_mchk)();   /* Machine check handling */
 	int	(*cpu_memerr)(); /* Memory subsystem errors */
 	int	(*cpu_conf)();	 /* Autoconfiguration */
+/*	int	(*cpu_cmrerr)(); /* Memory parity errors */
 };
 
 struct clockframe {
diff --git a/sys/arch/vax/include/ka650.h b/sys/arch/vax/include/ka650.h
new file mode 100644
index 00000000000..237402cac5c
--- /dev/null
+++ b/sys/arch/vax/include/ka650.h
@@ -0,0 +1,235 @@
+/*	$NetBSD: ka650.h,v 1.1 1995/12/13 18:58:05 ragge Exp $	*/
+/*
+ * Copyright (c) 1988 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Mt. Xinu.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)ka650.h	7.5 (Berkeley) 6/28/90
+ */
+
+/*
+ *
+ * Definitions specific to the ka650 (uVAX 3600/3602) cpu card.
+ */
+
+/*
+ * CAER: Memory System Error Register (IPR 39)
+ */
+#define CAER_DAL	0x00000040	/* CDAL or level 2 cache data parity */
+#define CAER_MCD	0x00000020	/* mcheck due to DAL parity error */
+#define CAER_MCC	0x00000010	/* mcheck due to 1st lev cache parity */
+#define CAER_DAT	0x00000002	/* data parity in 1st level cache */
+#define CAER_TAG	0x00000001	/* tag parity in 1st level cache */
+
+/*
+ * CADR: Cache Disable Register (IPR 37)
+ */
+#define CADR_STMASK	0x000000f0	/* 1st level cache state mask */
+#define CADR_SEN2	0x00000080	/* 1st level cache set 2 enabled */
+#define CADR_SEN1	0x00000040	/* 1st level cache set 1 enabled */
+#define CADR_CENI	0x00000020	/* 1st level I-stream caching enabled */
+#define CADR_CEND	0x00000010	/* 1st level D-stream caching enabled */
+
+/*
+ * Internal State Info 2: (for mcheck recovery)
+ */
+#define IS2_VCR		0x00008000	/* VAX Can't Restart flag */
+
+/*
+ * DMA System Error Register (merr_dser)
+ */
+#define DSER_QNXM	0x00000080	/* Q-22 Bus NXM */
+#define DSER_QPE	0x00000020	/* Q-22 Bus parity Error */
+#define DSER_MEM	0x00000010	/* Main mem err due to ext dev DMA */
+#define DSER_LOST	0x00000008	/* Lost error: DSER <7,5,4,0> set */
+#define DSER_NOGRANT	0x00000004	/* No Grant timeout on cpu demand R/W */
+#define DSER_DNXM	0x00000001	/* DMA NXM */
+#define DSER_CLEAR 	(DSER_QNXM | DSER_QPE | DSER_MEM |  \
+			 DSER_LOST | DSER_NOGRANT | DSER_DNXM)
+#define DMASER_BITS \
+"\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM"
+
+#ifndef LOCORE
+/*
+ * Local registers (in I/O space)
+ * This is done in disjoint sections.  Map names are set in locore.s
+ * and they are mapped in routine configcpu()
+ */
+
+/*
+ * memory error & configuration registers
+ */
+struct ka650_merr {
+	u_long	merr_scr;	/* System Config Register */
+	u_long	merr_dser;	/* DMA System Error Register */
+	u_long	merr_qbear;	/* QBus Error Address Register */
+	u_long	merr_dear;	/* DMA Error Address Register */
+	u_long	merr_qbmbr;	/* Q Bus Map Base address Register */
+	u_long	pad[59];
+	u_long	merr_csr[16];	/* Main Memory Config Regs (16 banks) */
+	u_long	merr_errstat;	/* Main Memory Error Status */
+	u_long	merr_cont;	/* Main Memory Control */
+};
+#define KA650_MERR	0x20080000
+
+/*
+ * Main Memory Error Status Register (merr_errstat)
+ */
+#define MEM_EMASK	0xe0000180	/* mask of all err bits */
+#define MEM_RDS		0x80000000	/* uncorrectable main memory */
+#define MEM_RDSHIGH	0x40000000	/* high rate RDS errors */
+#define MEM_CRD		0x20000000	/* correctable main memory */
+#define MEM_DMA		0x00000100	/* DMA read or write error */
+#define MEM_CDAL	0x00000080	/* CDAL Parity error on write */
+#define MEM_PAGE	0x1ffffe00	/* Offending Page Number */
+#define MEM_PAGESHFT	9		/* Shift to normalize page number */
+
+/*
+ * Main Memory Control & Diag Status Reg (merr_cont)
+ */
+#define MEM_CRDINT	0x00001000	/* CRD interrupts enabled */
+#define MEM_REFRESH	0x00000800	/* Forced memory refresh */
+#define MEM_ERRDIS	0x00000400	/* error detect disable	*/
+#define MEM_DIAG	0x00000080	/* Diagnostics mode */
+#define MEM_CHECK	0x0000007f	/* check bits for diagnostic mode */
+
+/*
+ * Main Memory Config Regs (merr_csr[0-15])
+ */
+#define MEM_BNKENBLE	0x80000000	/* Bank Enable */
+#define MEM_BNKNUM	0x03c00000	/* Physical map Bank number */
+#define MEM_BNKUSAGE	0x00000003	/* Bank Usage */
+
+/*
+ * Cache Control & Boot/Diag registers
+ */
+struct ka650_cbd {
+	u_char	cbd_cacr;	/* Low byte: Cache Enable & Parity Err detect */
+	u_char	cbd_cdf1;	/* Cache diagnostic field (unused) */
+	u_char	cbd_cdf2;	/* Cache diagnostic field (unused) */
+	u_char	pad;
+	u_long	cbd_bdr;	/* Boot & Diagnostic Register (unused) */
+};
+#define KA650_CBD	0x20084000
+
+/*
+ * CACR: Cache Control Register (2nd level cache) (cbd_cacr)
+ */
+#define CACR_CEN	0x00000010	/* Cache enable */
+#define CACR_CPE	0x00000020	/* Cache Parity Error */
+
+/*
+ * System Support Chip (SSC) registers
+ */
+struct ka650_ssc {
+	u_long	ssc_sscbr;	/* SSC Base Addr Register */
+	u_long	pad1[3];
+	u_long	ssc_ssccr;	/* SSC Configuration Register */
+	u_long	pad2[3];
+	u_long	ssc_cbtcr;	/* CDAL Bus Timeout Control Register */
+	u_long	pad3[55];
+	u_long	ssc_tcr0;	/* timer control reg 0 */
+	u_long	ssc_tir0;	/* timer interval reg 0 */
+	u_long	ssc_tnir0;	/* timer next interval reg 0 */
+	u_long	ssc_tivr0;	/* timer interrupt vector reg 0 */
+	u_long	ssc_tcr1;	/* timer control reg 1 */
+	u_long	ssc_tir1;	/* timer interval reg 1 */
+	u_long	ssc_tnir1;	/* timer next interval reg 1 */
+	u_long	ssc_tivr1;	/* timer interrupt vector reg 1 */
+	u_long	pad4[184];
+	u_char	ssc_cpmbx;	/* Console Program Mail Box: Lang & Hact */
+	u_char	ssc_terminfo;	/* TTY info: Video Dev, MCS, CRT & ROM flags */
+	u_char	ssc_keyboard;	/* Keyboard code */
+};
+#define KA650_SSC	0x20140000
+
+/*
+ * CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr)
+ */
+#define CBTCR_BTO	0x80000000	/* r/w unimp IPR or unack intr */
+#define CBTCR_RWT	0x40000000	/* CDAL Bus Timeout on CPU or DMA */
+
+/*
+ * TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01])
+ * (The rest of the bits are the same as in the standard VAX
+ *	Interval timer and are defined in clock.h)
+ */
+#define TCR_STP		0x00000004	/* Stop after time-out */
+
+/*
+ * Flags for Console Program Mail Box
+ */
+#define CPMB650_HALTACT	0x03	/* Field for halt action */
+#define CPMB650_RESTART	0x01	/* Restart */
+#define CPMB650_REBOOT	0x02	/* Reboot */
+#define CPMB650_HALT	0x03	/* Halt */
+#define CPMB650_BIP	0x04	/* Bootstrap in progress */
+#define CPMB650_RIP	0x08	/* Restart in progress */
+#define CPMB650_LANG	0xf0	/* Language field */
+
+/*
+ * Inter Processor Communication Register
+ * To determine if memory error was from QBUS device DMA (as opposed to cpu).
+ */
+struct ka650_ipcr {
+	u_long	pad[80];
+	u_short	ipcr0;		/* InterProcessor Comm Reg for arbiter */
+};
+#define KA650_IPCR	0x20001e00
+
+#endif	LOCORE
+
+/*
+ * Physical start address of the Qbus memory.
+ * The q-bus memory size is 4 meg.
+ * Physical start address of the I/O space (where the 8Kbyte I/O page is).
+ */
+#define KA650_QMEM	0x30000000
+#define KA650_QMEMSIZE	(512*8192)
+#define KA650_QDEVADDR	0x20000000
+
+/*
+ * Mapping info for Cache Entries, including
+ * Size (in bytes) of 2nd Level Cache for cache flush operation
+ */
+#define KA650_CACHE	0x10000000
+#define KA650_CACHESIZE	(64*1024)
+
+/*
+ * Useful ROM addresses
+ */
+#define	KA650ROM_SIDEX	0x20060004	/* system ID extension */
+#define	KA650ROM_GETC	0x20060008	/* (jsb) get character from console */
+#define	KA650ROM_PUTS	0x2006000c	/* (jsb) put string to console */
+#define	KA650ROM_GETS	0x20060010	/* (jsb) read string with prompt */
+#define KA650_CONSTYPE	0x20140401	/* byte at which console type resides */
diff --git a/sys/arch/vax/include/macros.h b/sys/arch/vax/include/macros.h
index 9b1bf44c026..969735a6640 100644
--- a/sys/arch/vax/include/macros.h
+++ b/sys/arch/vax/include/macros.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: macros.h,v 1.5 1995/10/20 12:55:06 ragge Exp $	*/
+/*	$NetBSD: macros.h,v 1.6 1995/12/13 18:56:01 ragge Exp $	*/
 
 /*
  * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
@@ -176,15 +176,6 @@ static __inline__ int max(int a, int b){
 }
 #endif
 
-#define	waitabit(tid)	\
-({	\
-	asm __volatile ("mfpr $27,r0;addl2 %0,r0;1:;mfpr $27,r1; \
-			cmpl r0,r1;bneq 1b;"	\
-			:		\
-			: "g"(tid)	\
-			: "r0","r1");	\
-})
-
 static __inline__ void blkcpy(const void*from, void*to, u_int len) {
 	asm __volatile("
 			movl    %0,r1
diff --git a/sys/arch/vax/include/nexus.h b/sys/arch/vax/include/nexus.h
index 9586ae7f41b..7f65fcae77d 100644
--- a/sys/arch/vax/include/nexus.h
+++ b/sys/arch/vax/include/nexus.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: nexus.h,v 1.5 1995/11/12 14:37:22 ragge Exp $	*/
+/*	$NetBSD: nexus.h,v 1.6 1995/12/13 18:55:27 ragge Exp $	*/
 
 /*-
  * Copyright (c) 1982, 1986 The Regents of the University of California.
@@ -35,6 +35,8 @@
  *	@(#)nexus.h	7.3 (Berkeley) 5/9/91
  */
 
+#ifndef _VAX_NEXUS_H_
+#define _VAX_NEXUS_H_
 /*
  * Information about nexus's.
  *
@@ -174,3 +176,5 @@ extern caddr_t *nex_vec;
 #ifndef	ASSEMBLER
 struct	nexus *nexus;
 #endif
+
+#endif /* _VAX_NEXUS_H_ */
diff --git a/sys/arch/vax/include/scb.h b/sys/arch/vax/include/scb.h
index 6d5234088b7..372d614919b 100644
--- a/sys/arch/vax/include/scb.h
+++ b/sys/arch/vax/include/scb.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: scb.h,v 1.3 1995/11/12 14:38:31 ragge Exp $	*/
+/*	$NetBSD: scb.h,v 1.4 1995/12/13 18:54:56 ragge Exp $	*/
 
 /*
  * Copyright (c) 1994 Ludd, University of Lule}, Sweden.
@@ -31,7 +31,76 @@
  */
 
 
+/*
+ * Definition of the System Control Block. More about it can be
+ * found in the Vax Architecture Reference Manual, section 6.6.
+ */
 struct scb {
+	void	*scb_unused;	/* First unused vector */
+	void	*scb_mcheck;
+	void	*scb_kspinv;
+	void	*scb_powfail;
+	void	*scb_privinst;	/* 10 Privileged Instruction fault */
+	void	*scb_xfcinst;
+	void	*scb_resop;
+	void	*scb_resad;
+	void	*scb_accessv;	/* 20 Access Control violation fault */
+	void	*scb_transinv;
+	void	*scb_trace;
+	void	*scb_breakp;
+	void	*scb_compat;	/* 30 Compatibility instruction fault */
+	void	*scb_arith;
+	void	*scb_unused1;
+	void	*scb_unused2;
+	void	*scb_chmk;	/* 40 CHMK */
+	void	*scb_chme;
+	void	*scb_chms;
+	void	*scb_chmu;
+	void	*scb_sbisilo;	/* 50 SBI Silo compare */
+	void	*scb_cmrd;
+	void	*scb_sbialert;
+	void	*scb_sbifault;
+	void	*scb_memwtimo;	/* 60 Memory write timeout */
+	void	*scb_unused3;
+	void	*scb_unused4;
+	void	*scb_unused5;
+	void	*scb_unused6;	/* 70 unused */
+	void	*scb_unused7;
+	void	*scb_unused8;
+	void	*scb_unused9;
+	void	*scb_unused10;	/* 80 unused */
+	void	*scb_softint1;
+	void	*scb_softint2;
+	void	*scb_softint3;
+	void	*scb_softint4;	/* 90 Software interrupt level 4 */
+	void	*scb_softint5;
+	void	*scb_softint6;
+	void	*scb_softint7;
+	void	*scb_softint8;	/* A0 Software interrupt level 8 */
+	void	*scb_softint9;
+	void	*scb_softinta;
+	void	*scb_softintb;
+	void	*scb_softintc;	/* B0 Software interrupt level C */
+	void	*scb_softintd;
+	void	*scb_softinte;
+	void	*scb_softintf;
+	void	*scb_timer;	/* C0 Interval timer */
+	void	*scb_unused11;
+	void	*scb_unused12;
+	void	*scb_unused13;
+	void	*scb_unused14;	/* D0 Unused */
+	void	*scb_unused15;
+	void	*scb_unused16;
+	void	*scb_unused17;
+	void	*scb_unused18;	/* E0 Unused */
+	void	*scb_unused19;
+	void	*scb_unused20;
+	void	*scb_unused21;
+	void	*scb_csrint;
+	void	*scb_cstint;	/* F0 Console storage transmit interrupt */
+	void	*scb_ctrint;
+	void	*scb_cttint;
+	struct	ivec_dsp *scb_nexvec[4][16];	/* Nexus interrupt vectors */
 };
 
 #ifdef _KERNEL
diff --git a/sys/arch/vax/include/trap.h b/sys/arch/vax/include/trap.h
index 2eb245a4de4..3efef61a1de 100644
--- a/sys/arch/vax/include/trap.h
+++ b/sys/arch/vax/include/trap.h
@@ -1,4 +1,4 @@
-/*      $NetBSD: trap.h,v 1.9 1995/11/12 14:33:11 ragge Exp $     */
+/*      $NetBSD: trap.h,v 1.10 1995/12/13 18:54:03 ragge Exp $     */
 
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
@@ -118,7 +118,7 @@ struct ivec_dsp {
 	char	pushlarg;	/* $? */
 	char	nop;      	/* nop, for foolish gcc */
 	char	calls[3]; 	/* calls $1,? */
-	u_int	hoppaddr;	/* jump for calls */
+	void	(*hoppaddr)();	/* jump for calls */
 	char	popr;	  	/* popr $0x3f */
 	char	poprarg;
 	char	rei;      	/* rei */
diff --git a/sys/arch/vax/include/vmparam.h b/sys/arch/vax/include/vmparam.h
index 41b7e2d30d7..8f449eabbd3 100644
--- a/sys/arch/vax/include/vmparam.h
+++ b/sys/arch/vax/include/vmparam.h
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.9 1995/08/22 04:28:20 ragge Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.10 1995/12/13 18:53:15 ragge Exp $	*/
 
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
@@ -106,9 +106,9 @@
  * Ptsizes are in PTEs.
  */
 
-#define	USRPTSIZE 	((MAXDSIZ >> PG_SHIFT) * maxproc)
-#define	KALLOCMEM	(((1*1024*1024*maxproc)>>PG_SHIFT)/4)
-#define SYSPTSIZE	(((USRPTSIZE * 4) >> PG_SHIFT) + UPAGES * maxproc + \
+#define	USRPTSIZE 	((MAXDSIZ >> PGSHIFT) * maxproc)
+#define	KALLOCMEM	(((1*1024*1024*maxproc)>>PGSHIFT)/4)
+#define SYSPTSIZE	(((USRPTSIZE * 4) >> PGSHIFT) + UPAGES * maxproc + \
 			    KALLOCMEM)
 
 /*